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DV-L70U
Pin No.
Pin name
GPI/O signal (4-pin)
122,123
GPAI/O [1:0]
2
GPSI
159
GPSO
PLL signal (6-pin)
129
GCLK
126
GCLK1
128
XO
136
PLLCA
137,135
PLLCFG [1:0]
Digital video port (24-pin)
92, 94~97,
Y [7:0]
99~101
102,
C [7:0]
104~107,
109~111
OSDPEL[3:0]
(C[3:0])
OSDPLT (C[4])
124
VCLKX2
84
VCLK
90
HSYNC
89
VSYNC
91
FI
88
CBLANK
85
VMASTER
87
VDEN#
Digital audio port (8-pin)
132
AMCLK
117
S/PDIF(AOUT[3])
116~114
AOUT [2:0]
112
AIN
118
ALRCLK
119
ABCLK
Type
I/O
General purpose bidirectional pin for monitor and control with ADP microcode.
3-S
I/O
After resetting, this pin is defined as the input. If ADP command is used, setting is possible.
I
I
General purpose input for monitor with DVP microcode.
O
O
General purpose output for control with DVP microcode.
I
I
27,000MHz clock or crystal input for main processor
27,000MHz master clock input for audio. It must be connected to GCLK during ordinary
I
I
operation.
O
O
Output to crystal connected to GCLK. If crystal is not used in GCLK, XO is not connected.
Capacitor connection pin for PLL. Connect 47nF capacitor. Connect the other terminal
of the capacitor to PLLGND.
PLL configuration input. Change is possible during reset only. In the normal use, both pins
I
I
must be connected to (digital) GND.
In the 16-bit video mode (Video8 = 0), the line becomes the luminance output.
In the 8-bit mode (Video8 = 1), it becomes the luminance/color difference output
3-S
O
which is timely multiple-processed according to ITU-R656 standard (regardless
whether SAV, EAV sync code is present or not).
In the 16-bit video mode (Video8 = 0), the line becomes the color difference output.
3-S
I/O
In the 8-bit mode (Video8 = 1), the pin 3 (C[7:5]) of m.s. line is not used, and 1.s.5 pin
(C[4:0]) is specified as the input which is received from the external OSD device.
OSD pixel input. The four signals are used as the entry to on-chip OSD pallet.
On-chip OSD pallet selector. OSDPallete0 is selected for the low level, and
OSDpallete1 is selected for the high level.
3-S
I/O
Main video clock input or output. 27,000MHz
VCLKx2 signal is divided into two parts. The signal is used as the qualifier of the data
3-S
I/O
and sync signal.
3-S
I/O
Horizontally sync bidirection signal pin. The polarity and length are programmable.
3-S
I/O
Vertically sync bidirectional signal pin. The polarity and length are programmable.
3-S
I/O
Field identification bidirectional signal pin. The polarity is programmable.
O
O
Composite blank output. The waveform including the polarity is programmable.
Video master/slave selection input. For the high level, the video synchronization of
MD36710X goes into the master mode. (Accordingly, the video SYNC signal and
clock are output.)
I
I
For the low level, the video synchronization goes into the slave mode. (Accordingly,
the video SYNC signal and clock are input.)
Only in the reset mode, the setting of the terminal can be changed.
Video enable input (active low). When it is active, MD36710X outputs the video data.
When it is deasserted, the pixel output goes into the 3-state. (However, the sync
I
I
signal and clock are kept to be active.)
Though this input can be changed at any time, it is valid at the following VCKx2 time.
Audio master clock input/output. The sampling frequencies of 384fs, 256fs, 192fs
3-S
O
and 128fs can be selected (programmable).
S/DDIF transmitter output. Moreover, it can be connected to DAC as the 4th audio
O
O
output (AOUT[3]). After resetting, the pin outputs the low level.
Serial output of PCM stereo audio for DAC. After resetting, the pin outputs the low
O
O
level. Only for AOUT[0], the sample width of 24 bits is supported.
I
I
Serial input of PCM stereo audio for ADC.
LR clock output of AOUT[3.0] and ATN. For the sampling frequency, it is a rectangular
O
O
wave.
The polarity of LR is programmable.
Bit clock output of AOUT[3.0] and AIN. AOUT is output at the rise/fall edges of the
O
O
clock (programmable), and AIN is latched.
Function
9-11
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