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MAIN BOARD IC1800 MB89F538L-F501-X101 (SUB SYSTEM CONTROLLER)
Pin No.
Pin Name
1
2
3
REG-TEMP
4 to 9
CUR1 to CUR6
CUR7/D-AMP-
10
TEMP-AD
11
12
13
14
15
AC-OFF
16
PWM-MODE
17, 18
DC1, DC2
19
20, 21
MOD0, MOD1
22
23
24
25
VOL-CLK
26
VOL-DATA
TE
L 13942296513
27
VOL-LAT
28
DAC-MUTE
29, 30
(P23), (P22)
31
32
SUR (A) RY
33
SUR (B) RY
34
35
HIC-TEMP
36
37
38
39
40
41
SOFT-MUTE
42
U-SUB1
43
44
45
46
www
47
FRONT (A) RY
48
FRONT (B) RY
49
.
50
51
52
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I/O
I-LIMIT
I
Abnormal current detection signal input from the digital power amplifier
MOD2
—
Not used (Pull down)
I
Thermistor connection terminal for abnormal temperature detection
Current detection terminal for speaker output section
I
Not used (Connected to ground)
I
Abnormal temperature detection terminal for the power amplifier
AVCC
—
Power supply (+3.3V)
AVR
I
Reference voltage (+3.3V) input terminal
AVSS
—
Ground
U-MAIN
I
Clock signal input from main system controller
I
AC off detection signal input terminal
I
PWM mode setting terminal
I
DC offset detection signal input terminal
RST
I
System reset signal input from the main system controller
I
Setting terminal for memory access mode
X0
I
System clock input terminal (12.5 MHz)
X1
O
System clock output terminal (12.5 MHz)
VSS
—
Ground
Serial data transfer clock signal output to the power amplifier power supply
O
control D/A converter
O
Serial data output to the power amplifier power supply control D/A converter
Serial data latch pulse signal output to the power amplifier power supply control
O
D/A converter
Muting on/off control signal output to the power amplifier power supply control
O
circuit
—
Not used
4/8SW
I
IMPEDANCE SELECTOR switch input terminal
O
Relay drive signal (for surround speaker) output terminal
O
Relay drive signal (for surround speaker) output terminal
4/8OUT
I
Relay drive signal (for selection) output terminal
I
Over temperature detection signal input from the digital power amplifier
EN
O
Enable/Disable control signal output to the digital power amplifier
DC3
I
DC offset detection signal input terminal
INIT
O
System reset signal output to the stream processor
DC4
I
DC offset detection signal input terminal
(P10)
—
Not used
O
Muting on/off control signal output to the stream processor
I
Serial data input from main system controller
LAT4
O
Serial data latch pulse signal (for surround back) output terminal
LAT3
O
Serial data latch pulse signal (for surround) output terminal
LAT2
O
Serial data latch pulse signal (for center) output terminal
LAT1
O
Serial data latch pulse signal (for front) output to the stream processor
O
Relay drive signal (for front speaker A) output terminal
O
Relay drive signal (for front speaker B) output terminal
x
ao
y
NC
—
Not used (Open)
i
DC5
I
DC offset detection signal input terminal
SHIFT
O
Serial data transfer clock signal output to the stream processor
SCDT
O
Serial data output to the stream processor
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8
Pin Description
Normally: fixed at "H"
Q Q
3
6 7
1 3
u163
.
2 9
9 4
2 8
"L": AC off
Not used
"L": reset
1 5
0 5
8
2 9
9 4
Not used
Not used (Open)
Not used (Open)
Not used (Open)
Not used
Not used
Not used
Not used
m
Not used (Open)
Not used (Open)
co
Not used
TA-F501ES
9 9
Not used
Not used
2 8
9 9
Not used
45
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