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DV-203/2070/DVF-5010/9010/K7010
QQ
3 7 63 1515 0
DSP/D.R.I.V.E.¿ ¿ : KAN06 (X32 : IC2)
7.
7-1 Pin description
Pin No. Pin Name
1
MUTE
2
BCK
3
DATA
4
LRCK
5
RST
6
VSS
7
IBF
8
IIS
9
IUD
10
IW0
11
IW1
12
VSS
13-16
NCON3-0
17
VDD
18
DR0N0
19
DR0N1
20
NT
21
RND0
22
RND1
TE
L 13942296513
23
OBF
7-2 Block diagram
THRMN
DRON0
DRON1
FILN
LRCK
S/P
BCK
DATA
LRCK
BCK
DATA
MMOD0
MMOD1
CLOCK Gen.
ICTH
www
.
20
CIRCUIT DESCRIPTION
I/O
Descriptions
I
Mute(H:on)
I
BCK input port
I
Data input port
I
LRCK input port
I
Reset input port(L:reset)
-
GND
I
Input format setting(1)
I
Input format setting(2)
I
Inverted input port of LRCK
I
Input data period setting(1)
I
Input data period setting(2)
-
GND
O
Test port
-
Power supply port
I
ROM compensation on/off
I
Filter compensation on/off
I
Connect H level
I
Open
I
Open
I
Output format setting(1)
DELAY
FILTER1
FILTER2
differential
differential
x
ao
y
Data detection
i
8
Pin No. Pin Name
24
OIS
25
OLRRL
26
OUD
27
FILN
28
VSS
29
LRCKO
30
DATAO
31
BCKO
32
DRVW
33
THRMN
34
ICTH
35
VDD
36
CK
37
X0
38
VSS
39
VDD
40,41
MCK0,1
Q Q
42
VSS
3
6 7
1 3
43,44
MMOD0,1
SEL
correction
amp
amp
u163
L. P. F.
.
2 9
9 4
2 8
I/O
Descriptions
I
Output format setting(2)
I
Output change port
I
Edge setting of LRCK0
I
Connect H level
-
GND
O
LRCK output port
O
DATA output port
O
BCK output port
I
Connect H level
I
Through mode
I
Phase setting of internal
oscillation
-
Power supply port
I
Master clock input port
O
Crystal output port
-
GND
-
Power supply port
O
Master clock output port
-
GND
1 5
0 5
8
2 9
9 4
I
Master clock frequency setting
Data
P/S
m
co
9 9
2 8
9 9
LRCK0
BCK0
DATA0
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