Pioneer TS5 Service Manual page 44

TS5, BCT-1510, BCT-1520,
BCT-1530
•
Pin Function (3/5)
Pin
MemAddr2-23 out
MemData0-31
MemRdnotWr out
MemReq
MemGrant
MemWait i
notMemCAS0,2
notMemCAS1
notMemCAS3
notMemRAS0
notMemRAS1
notMemRAS2
notMemRAS3
notMemCSROM
notSDRAMCS0
notMemOE
notMemBE0-3
notMemCS2
BootSource0-1
ProcClockOut
Pin
AD0-12 out
DQ0-15
notSDCS0
notSDCS1/AD13
notSDCAS out
notSDRAS out
notSDWE out
MEMCLKIN
MEMCLKOUT
DQML
DQMU
44
In/Out Function
Address bus
in/out Data bus. MemData0 is the least significant bit (LSB) and MemData31 is the most
significant bit (MSB).
ReadnotWrite strobe
in Direct memory access request
out Direct memory access granted
n Memory cycle extender
out CAS strobes for SDRAM/DRAM in Banks 0 and 1
out CAS strobe for DRAM or SDRAM clock
out CAS strobe for DRAM or sub-bank chip select for bank 3
out RAS strobe for SDRAM/DRAM in Bank 0, chip select for Bank0 or
RAS strobe for lowest DRAM sub-bank in Bank0
out RAS strobe for highest DRAM sub-bank in Bank0 or
SDRAM Chip select signal for highest sub-bank of Bank0
out RAS strobe for SDRAM/DRAM in bank 1, chip select for Bank1 or
RAS strobe for lowest DRAM sub-bank in Bank1
out RAS strobe for highest DRAM sub-bank in Bank1 or
SDRAM Chip select signal for Bank1
out Chip select strobe for ROM in bank3.
out SDRAM Chip select signal for Bank0 or lowest sub-bank of Bank0
out Output enable strobe - banks 0-3.
out Byte enable strobes - banks 0-3.
out Chip select strobe for memory in bank 2.
in Boot from ROM or from link.
out Processor clock.
Table 6 STi5512 External memory interface pins
In/Out Function
SDRAM address bus
in/out SDRAM data bus (lower byte)
out SDRAM chip select for first SDRAM
out SDRAM chip select for second SDRAM or AD13
SDRAM CAS
SDRAM RAS
SDRAM write enable
in SDRAM memory clock input
out SDRAM memory clock output
out DQ mask enable (lower)
out DQ mask enable (upper)
Table 7 Shared SDRAM interface pins