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MG8 / 2FX
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IC BLOCK DIAGRAM （IC ブロック図）
3 7 63 1515 0
PCM1742KEG/2K (X3538A00) Digital to Analog Converter
DSP: ICM08
BCK
Audio
LRCK
Serial
Port
4x/8x
DATA
Oversampling
Digital Filter
with
Function
ML
Controller
Serial
MC
Control
Port
MD
System Clock
System Clock
SCK
Manager
AK5381VT-E2 (X5219A00) Analog to Digital Converter
DSP: ICM04
VA AGND VD DGND
6
5
7
8
Decimation
2
AINL
TE
Modulator
L 13942296513
Decimation
1
AINR
Modulator
Voltage
VCOM
4
Reference
15
3
16
CKS2
CKS1
CKS0
LB1412M (X5838A00)
LED Driver
IC803,IC805
MAIN:
VZ
RESET
OSC ILED
13
12
14
OSC
-
+
OUT2
11
-
+
-
+ -
+
IN2
10
-
+
OUT1
9
-
+
-
+
IN1
8
-
+
-
+
www
R
-
S Q
+
R
Q
-
S Q
+
R
Q
VCC
16
-
S Q
+
.
R
Q
-
S Q
+
R
Q
-
S Q
+
7
GND
16
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Output Amp and
DAC
Low-Pass Filter
Enhanced
Multilevel
Delta-Sigma
Modulator
Output Amp and
DAC
Low-Pass Filter
Zero Detect
Power Supply
MCLK
11
AINR
AINL
Clock
Divider
CKS1
VCOM
LRCK
10
AGND
Filter
12
SCLK
Filter
DGND
Serial I/O
9
SDTO
Interface
13
14
PDN
DIF
NJM4556AL (XP844A00)
Dual Operational Amplifier
MAIN: IC806
15
CURENT
DRIVER
D1
17
18
D2
19
D3
D4
20
CURENT
A
DRIVER
D5
21
1
D6
22
OUT
A
23
D7
D8
2
x
ao
D9
y
3
D10
4
i
D11
5
D12
6
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8
BCK
1
16
DATA
2
15
LRCK
3
14
V
L
OUT
DGND
4
13
PCM1742
V
5
12
DD
V
6
11
CC
V
V
L
7
10
COM
OUT
V
R
8
9
OUT
V
R
OUT
Pin No. Pin Name
1
CKS0
16
1
2
2
15
CKS2
3
3
14
DIF
4
PDN
4
13
Top View
Q Q
5
5
SCLK
12
3
6 7
1 3
6
VA
6
11
MCLK
7
VD
LRCK
7
10
8
SDTO
8
9
9
10
11
12
13
14
15
16
Note: All input pins should not be left floating.
B
2
3
4
5
6
7
8
-
+
-
+
-
OUT
+
A
A
V
B
B
B
V
u163
.
2 9
9 4
2 8
PIN ASSIGNMENTS
PIN
NAME
TYPE
FUNCTION
SCK
1
BCK
IN
Audio Data Bit Clock Input.
2
DATA
IN
Audio Data Digital Input.
ML
3
LRCK
IN
L-Channel and R-Channel Audio Data Latch En-
MC
able Input.
(1)
4
DGND
Digital Ground
MD
5
V
Digital Power Supply, +3.3V
DD
ZEROL/NA
6
V
Analog Power Supply, +5V
CC
7
V
L
OUT
Analog Output for L-Channel.
ZEROR/ZEROA
OUT
8
V
R
OUT
Analog Output for R-Channel.
OUT
V
COM
9
AGND
Analog Ground
AGND
10
V
Common Voltage Decoupling.
COM
11
ZEROR/
OUT
Zero Flag Output for R-Channel/Zero Flag Output
ZEROA
for L/R-Channel.
12
ZEROL/NA
OUT
Zero Flag Output for L-Channel/No Assign.
13
MD
IN
Mode Control Data Input.
14
MC
IN
Mode Control Clock Input.
15
ML
IN
Mode Control Latch Input.
16
SCK
IN
System Clock Input.
NOTES: (1) Schmitt-trigger input, 5V tolerant. (2) Schmitt-trigger with internal
pull-down, 5V tolerant.
I/O
Function
AINR
I
Rch Analog Input Pin
AINL
I
Lch Analog input Pin
CKS1
I
Mode Select 1 Pin
VCOM
O
Common Voltage Output Pin, VA/2
Bias voltage of ADC input.
AGND
-
Analog Ground Pin
1 5
0 5
8
2 9
9 4
VA
-
Analog Power Supply Pin, 4.5 ~ 5.5V
VD
-
Digital Power Supply Pin,
2.7 ~ 5.5V(Fs=4K ~ 48kHz), 3.0 ~ 5.5V(Fs=48k ~ 96kHz)
DGND
-
Digital Ground Pin
SDTO
O
Audio Serial Data Output Pin
"L" Output at Power-down mode.
LRCK
I/O
Output Channel Clock Pin
"L" Output in Master Mode at Power-down mode.
MCLK
I
Master Clock Input Pin
SCLK
I/O
Audio Serial Data Clock Pin
"L" Output in Master Mode at Power-down mode.
PDN
I
Power Down mode Pin
"H":Power up, "L":Power down
DIF
I
Audio Interface Format Pin
"H":24bit I
S Compatible, "L":24bit MSB justified
2
CKS2
I
Mode Select 2 Pin
CKS0
I
Mode Select 0 Pin
●
NJM4580M-D (X5025A00)
NJM4558M (X5676A00)
NJM2068M-D (X3505A0)
Dual Operational Amplifier
MAIN:IC101, 201, 301, 401, 801, 804
MAIN:IC103, 304, 404, 503
MAIN:IC202, 302, 303, 402, 403, 501,
IC502, 701, 702, 802
DSP:ICM09, 11
+DC Voltage
Output A
1
+V
8
Supply
Inverting
2
7
Output B
Input A
-
+
Non-Inverting
Inverting
3
6
+
-
Input B
Input A
m
Non-Inverting
-DC Voltage Supply
4
-V
5
Input B
co
9 9
(1)
(1)
(2)
(2)
(2)
2 8
9 9
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