Page 1 MICROCOMPUTER MN103001G/F01K LSI User’s Manual MN1030 Pub.No.23101-050E...
Page 3 PanaX Series is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names, logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations. Request for your special attention and precautions in using the technical informaition and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and Foreign...
Page 5 Table of Contents/List of Figures and Tables General Specifications Extension Instruction Specifications Memory Modes Operating Mode Clock Generator Internal Memory Bus Controller (BC) Interrupt Controller 8-bit Timers 16-bit Timers Watchdog Timer Serial Interface...
Page 7 A/D Converter I/O Ports Internal Flash Memory Ordering Mask ROM Appendix...
Page 9: Table Of Contents/List Of Figures And Tables
Table of Contents/List of Figures and Tables...
Page 10: Table Of Contents
Table of Contents 1. General Specifications Overview ... 1-2 Features ... 1-2 Block Diagram ... 1-4 Pin Description ... 1-5 1.4.1 Pin Assignments ... 1-5 1.4.2 Pin Functions ... 1-7 2. CPU Basic Specifications of CPU ... 2-2 Block Diagram ... 2-3 Programming Model ...
Page 11 5. Operating Mode Overview ... 5-2 Reset Mode ... 5-3 Low Power Mode ... 5-4 6. Clock Generator Overview ... 6-2 Features ... 6-2 Block Diagram ... 6-2 Description of Operation ... 6-3 6.4.1 Input Frequency Setting ... 6-3 6.4.2 Internal Clock Supply ...
Page 12 8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode ... 8-35 8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode ... 8-37 8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode ... 8-39 8.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode ...
Page 13 10.6 Description of Operation ... 10-20 10.6.1 Interval Timers and Timer Output ... 10-20 10.6.2 Event Counting ... 10-24 10.6.3 Cascaded Connection ... 10-26 10.6.4 PWM Output ... 10-31 11. 16-bit Timers 11.1 Overview ... 11-2 11.2 Features ... 11-2 11.3 Block Diagram ...
Page 14 13.4.2 Block Diagram of UART Serial Interface ... 13-37 13.4.3 Description of Registers for the UART Serial Interface ... 13-38 13.4.4 Description of Operation ... 13-45 14. A/D Converter 14.1 Overview ... 14-2 14.2 Features ... 14-3 14.3 Block Diagram ... 14-4 14.4 Description of Registers ...
Page 15 15.9.3 Pin Configurations ... 15-44 15.10 Port 8 ... 15-45 15.10.1 Block Diagram ... 15-45 15.10.2 Register Descriptions ... 15-46 15.10.3 Pin Configurations ... 15-47 15.11 Port 9 ... 15-48 15.11.1 Block Diagram ... 15-48 15.11.2 Register Descriptions ... 15-50 15.11.3 Pin Configurations ...
Page 16 List of Figures and Tables List of Figures General Specifications Fig. 1-3-1 MN103001G Block Diagram ... 1-4 Fig. 1-4-1 Pin Assignments Diagram ... 1-5 Fig. 2-2-1 CPU Core Block Diagram ... 2-3 Fig. 2-3-1 CPU Registers ... 2-4 Fig. 2-3-2 Processor Status Word ...
Page 17 Fig. 8-7-1 Address Format When Accessing External Memory ... 8-26 Fig. 8-7-2 Space Partitioning ... 8-27 Fig. 8-12-1 Internal I/O Space Access ... 8-31 Fig. 8-13-1 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4) ...
Page 18 Fig. 8-13-21 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) ... 8-49 Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK) ...
Page 19 10. 8-bit Timers Fig. 10-3-1 8-bit Timer Block Diagram (Timers 0 to 3) ... 10-3 Fig. 10-3-2 8-bit Timer Block Diagram (Timers 4 to B) ... 10-4 Fig. 10-3-3 8-bit Timer Connection Diagram (Overall)... 10-5 Fig. 10-3-4 8-bit Timer Connection Diagram (Timer 0 to 3 block) ... 10-6 Fig.
Page 20 12. Watchdog Timer Fig. 12-3-1 Block Diagram ... 12-3 Fig. 12-5-1 Operation Diagram 1: When Reset Is Released ... 12-7 Fig. 12-5-2 Operation Diagram 2: When Recovering from STOP Mode ... 12-8 Fig. 12-5-3 Operation Diagram 3: Watchdog Operation ... 12-9 13.
Page 21 Fig. 14-5-2 External Trigger Input Conversion Example (for Channels 0 to 2, One Time Each)... 14-8 Fig. 14-5-3 External Trigger Input Conversion Example ... 14-9 Fig. 14-5-4 External Trigger Input Conversion Example (for Channels 0 to 2, Continuous Conversion) ... 14-10 Fig.
Page 22 17. Ordering Mask ROM Fig. 17-2-1 ROM Ordering Method 1 ... 17-2 Fig. 17-2-2 ROM Ordering Method 2 ... 17-3 Appendix Fig. C-1 Memory Connection Example... Appendix-11 Fig. E-1 Package Outline ... Appendix-14...
Page 23 List of Tables 1. General Specifications Table 1-4-1 Pin Assignments ... 1-6 Table 1-4-2 Pin Function Table (1/2)... 1-7 Table 1-4-2 Pin Function Table (2/2)... 1-8 2. CPU Table 2-3-1 List of Control Registers ... 2-7 Table 2-4-1 Addressing Mode Types ... 2-10 Table 2-4-2 Data Types ...
Page 24 10. 8-bit Timers Table 10-4-1 List of 8-bit Timer Functions ... 10-9 Table 10-5-1 List of 8-bit Timer Registers (1/2) ... 10-10 Table 10-5-1 List of 8-bit Timer Registers (2/2) ... 10-11 Table 10-5-2 PWM Output Waves ... 10-14 Table 10-5-3 8-bit Timer Clock Sources ... 10-15 11.
Page 25 Table 15-13-1Port B Configuration ... 15-60 Table 15-14-1Port C Configuration ... 15-63 Table 15-15-1Treatment of Unused Pins ... 15-64 16. Internal Flash Memory Table 16-4-1 Mode Settings through the External Pins ... 16-3 Table 16-5-1 MN1030 F01K Pin Assignments ... 16-5 Table 16-5-2 Pin Functions ...
Page 26 xviii...
Page 27: General Specifications
General Specifications...
Page 28: Overview
1.1 Overview The MN1030 Series is a 32-bit microcontroller that maintains the software assets of Matsushita Electronics' 16-bit MN102 Series of microcontrollers by offering ease of use and excellent cost-performance with a simple, high- performance architecture. Built around a compact 32-bit CPU core with a basic instruction word length of one byte, the MN103001G (mask ROM version) includes ROM, RAM, a bus control circuit, interrupt control circuit, timers, a serial interface, A/D converter, and input/output ports in a 100-pin QFP.
Page 29 High-speed/high-performance bus interface Can select either separate address/data buses or multiplex address/data bus • Address: 24 bits/Data: 8/16 bits External memory space can be partitioned into four blocks • Chip select signal output for each block • Blocks 2 to 3 can be switched between fixed wait insertion or handshaking •...
Page 30: Block Diagram
Input ports: • 4 (all multipurpose) Output ports: • 15 (all multipurpose) Input/output ports: • 53 (all multipurpose) Flash microcontroller specifications Performance identical to that of a mask ROM product guaranteed Overwriting while on board possible through serial communications Batch/block erase possible Block units 8 KB (multiple blocks can be selected simultaneously) Package •...
Page 31: Top View
1.4 Pin Description 1.4.1 Pin Assignments The pin assignments are shown in Fig. 1-4-1 and Table 1-4-1. * "VDD2" in the case of the MN103001G, "VPP" in the case of the MN1030F01K. TOP VIEW 100-Pin QFP Fig. 1-4-1 Pin Assignments Diagram...
Page 32: Table 1-4-1 Pin Assignments
Pin Name Pin Name 1 PC3/A19 26 PVSS 2 PC2/A18 27 PVDD 3 VDD 28 MMOD1 4 PC1/A17 29 MMOD0 5 PC0/A16 30 RST 6 PB7/ADM15/A15 31 OSCO 7 PB6/ADM14/A14 32 OSCI 8 PB5/ADM13/A13 33 VDD 9 VSS 34 SYSCLK/P97 10 PB4/ADM12/A12 35 VSS 11 PB3/ADM11/A11...
Page 33: Pin Functions
1.4.2 Pin Functions Table 1-4-2 shows the function of each pin of this microcontroller. Category Pin name Power supply VDD2(VPP) Clock OSCI OSCO SYSCLK CKSEL PVDD PVSS Address bus A23 to 0 Data bus D15 to 0 Address/ ADM15 to 0 Data bus Bus control MMOD1 to 0...
Page 34: Table 1-4-2 Pin Function Table (2/2)
Category Pin name Reset Interrupts NMIRQ IRQ7 to 0 Serial interface SBI3 to 0 SBO3 to 0 SBT3 to 0 8-bit timer TM7IO to TM0IO 16-bit timer TM10IOA TM10IOB TM13IO to TM11IO A/D converter VREFH ADTRG AN3 to 0 AVDD AVSS I/O ports P02 to P00...
Page 36: Basic Specifications Of Cpu
2.1 Basic Specifications of CPU • Structure Load/store architecture Data/Address/SP Registers x 9 (Data registers: 32-bit x 4, Address registers: 32-bit x 4, SP: 32-bit x 1) Other Registers (PC: 32-bit x 1, PSW: 16-bit x 1, Multiply/divide register: 32-bit x 1, Branch target registers: 32-bit x 2) •...
Page 37: Block Diagram
2.2 Block Diagram The block diagram for this microcontroller, focusing on the CPU, is shown below. Address register User extension function unit Operand address Data register Program Barrel counter shifter block Operand data Internal data RAM Bus contol block External interface Fig.
Page 38: Programming Model
2.3 Programming Model 2.3.1 CPU Registers • The register set is divided into data registers that are used for arithmetic operations, etc., address registers that are used for pointers, and a stack pointer. This arrangement contributes greatly to the improved performance of the internal architecture, through reduction of instruction code size, improved parallelism in pipeline processing, etc.
Page 39: Fig. 2-3-2 Processor Status Word
Data Register (32-bit x 4) This register can be used generally for all operations. Operations are performed with a 32-bit length and the data size is converted when sending data to and from the memory or by executing the EXTB or EXTH instructions. When loading data, 8-bit data is zero-extended to 32 bits and sent to the register.
Page 40 Z: Zero Flag This flag is set when an operation result is all zeroes, and is cleared by any other result. This flag is also cleared by a reset. N: Negative Flag This flag is set if the MSB of an operation result is "1", and is cleared if the MSB is "0". This flag is also cleared by a reset.
Page 41: Control Registers
2.3.2 Control Registers This microcontroller uses the memory-mapped-I/O method and allocates the peripheral circuit registers to the internal I/O space between addresses x'20000000 and x'3FFFFFFF. The registers listed below are described in this section. For details on other control registers, refer to the respective sections that explain the various internal peripheral functions.
Page 42 Interrupt Vector Register (IVARn) The interrupt vector register (IVAR0 to IVAR6) contains the lower 16 bits of the start address of the interrupt handler for interrupts of the level accepted by the CPU. IVAR0 corresponds to level 0 interrupts; in similar fashion, IVAR1 to IVAR6 correspond to levels 1 to 6, respectively.
Page 43 CPU Mode Register (CPUM) The CPU mode register (CPUM) sets the clock operating mode for the CPU and peripheral blocks. This register is allocated to the internal I/O space at address x'20000040. Bit No. Bit name — — — — Reset Access Bit No.
Page 44: Instructions
2.4 Instructions 2.4.1 Addressing Modes The 32-bit microcontroller is equipped with the following 6 addressing modes which are frequently used with compilers. All 6 addressing modes of register direct, immediate value, register indirect, register indirect with displacement, absolute and register indirect with index can be used with data transfer group instructions. The 2 addressing modes of register direct and immediate addressing can be used with register operation instructions.
Page 45: Data Types
2.4.2 Data Types Data types can be processed in the four types of bit, byte, halfword and word data. Byte data, halfword data and word data can be handled as signed and unsigned data. The sign bit is MSB. The data in the memory must be aligned data. In other words, the two bits on the LSB side of addresses containing word data must be "00"...
Page 46: Instruction Set
2.4.3 Instruction Set The instruction set has a simple organization, and features the generation of compact and optimized code through a C compiler. The instruction code size is reduced by making the basic instruction word length one byte. As a result, increases in the code size of the assembler program can be kept to a minimum even though the instruction set is simple, with data transfers to and from memory limited to load and store operations.
Page 47 • Bit instructions BTST BSET BCLR • Shift instructions ASL2 • Branch instructions SETLB CALL CALLS RETF RETS TRAP • Extension instructions UDFU Note: Interrupts are prohibited and the bus is locked (occupied by the CPU) when executing BSET or BCLR, however, if a BSET or BCLR instruction is executed during program execution in external memory, a bus authority release due to an external bus request may be interposed between the data read and data write by the BSET or BCLR instruction.
Page 48: Interrupts
2.5 Interrupts 2.5.1 Overview of Interrupts The most important key to real-time control is the ability to shift quickly to interrupt handler processing. If an interrupt is generated during the execution of an instruction that requires multiple cycles for execution (multiplication or division instructions, for example), interrupt response is improved by aborting the execution of the instruction and immediately accepting the interrupt.
Page 49: Registers
2.5.2 Registers [Flags in the PSW] (CPU) Interrupt-related flags in the processor status word (PSW) include interrupt enable and interrupt mask level. IE (Interrupt Enable) R/W • This flag allows all interrupts to be accepted except for non-maskable interrupts and reset interrupts. Interrupts are allowed when IE = 1.
Page 50 LV2 to LV0 (Interrupt Priority Level) R/W • This 3-bit field sets the interrupt priority level. When the interrupt priority level set in LV2 to LV0 is higher than the interrupt mask level set in IM2 to IM0 in the PSW (i.e., the value set in LV2 to LV0 is smaller than the value set in IM2 to IM0), interrupts in the corresponding interrupt group are enabled.
Page 51: Fig. 2-5-3 Interrupt Accept Group Register
[Interrupt Accept Group Register (IAGR)] R halfword/byte access During a register read, the interrupt accept group register (IAGR) indicates the smallest group number of the groups that are generating an interrupt of the interrupt levels accepted by the CPU, which are indicated by IM2 to IM0 of the PSW.
Page 52: Interrupt Types
2.5.3 Interrupt Types The three types of interrupts are listed below: [Reset interrupt] The reset interrupt is the interrupt with the highest priority level, and is generated by setting the RST pin to "L" level. As a result of the reset interrupt, the registers, etc., are initialized. When the RST pin goes to "H" level, the microcontroller waits until the oscillation of the internal clock stabilizes, and then begins executing program instructions starting from address x'40000000.
Page 53: Interrupt Definition
[Level interrupts] Level interrupts are interrupts for which the interrupt level can be controlled through the interrupt enable (IE) and interrupt mask (IM2 to IM0) bits in the PSW. Level interrupts are interrupts from the interrupt group controllers external to the CPU (in other words, peripheral interrupts). There are 18 groups, or 35 interrupt factors. Each interrupt group controller includes an interrupt control register (GnICR);...
Page 54: Fig. 2-5-5 Interrupt Sequence Flow
(Example of pre-processing by the interrupt handler) 1. The registers are saved. The saved registers are those used by the interrupt handler. 2. The interrupt group analysis is executed. 2.1 The interrupt acknowledge sequence is executed. Interrupt acknowledge consists of reading out the interrupt accept group register (IAGR) to obtain the group number of the interrupt group with the highest priority among the specified interrupt levels.
Page 55: Fig. 2-5-6 Interrupt Sequence Flow
An even higher interrupt response speed can be realized by assigning only one factor or only a few factors to a single interrupt level. Fig. 2-5-6 shows the interrupt sequence flow when assigning one factor to each interrupt level. Program Interrupt max.
Page 56: Fig. 2-5-7 Stack Frame Configuration
[Stack Frame] When an interrupt is accepted, a stack frame is allocated and the total 6 bytes of information in the PC and PSW are saved in order to return from the interrupt. However, since the transfer of data across the 32-bit boundary is prohibited, the SP value must constantly be set to a multiple of 4.
Page 57: Extension Instruction Specifications
Extension Instruction Specifications...
Page 58: Operation Extension Function
3.1 Operation Extension Function The MN1030 series 32-bit microcontrollers are provided with 32 extension instructions which can be defined by users. This allows the desired processing to be performed at high speed for each model expansion by assigning multiply, multiply-accumulate, saturation and other application-oriented operations to extension instructions and connecting extension function unit via the extension operation interface of the CPU core.
Page 59: Extension Instructions
3.2 Extension Instructions 3.2.1 Explanation of Notations The notations used to describe instruction manual are shown below. Opcode Am, An: Address Register (m, n = 3 to 0) Dm, Dn: Data Register (m, n = 3 to 0) Stack Pointer imm: Immediate value (used as the general meaning) imm8:...
Page 60: Extension Block Register Set
3.2.2 Extension Block Register Set The extension block has the following dedicated registers in which it stores the results of high-speed multiplication operations and multiply-and-accumulate operations. Multiply Register Multiply & Accumulate Register (Higher) Multiply & Accumulate Register (Lower) Multiply & Accumulate Overflow Detect Flag Register Multiply register (32 bits x 1 register) This register is provided for high-speed multiplication instructions.
Page 61: Extension Instruction Details
3.2.3 Extension Instruction Details PUTX (Register transfer instruction for high-speed multiplication: Load) [Instruction Format (Macro Name)] PUTX Dm [Assembler Mnemonic] udf20 Dm, Dm [Operation] The contents of Dm are transferred to the high-speed multiply register MDRQ. [Flag Changes] Flag Change –...
Page 62 PUTCX (Register transfer instruction for multiply-and-accumulate operation: Load) [Instruction Format (Macro Name)] PUTCX Dm, Dn [Assembler Mnemonic] udf21 Dm, Dn [Operation] This instruction transfers the contents of Dm to the multiply-and-accumulate register MCRH. This instruction also transfers the contents of Dn to the multiply-and-accumulate register MCRL. The contents of the V flag are set in the multiply-and-accumulate overflow detect register MCVF.
Page 63 GETX (Register transfer instruction for high-speed multiplication: Store) [Instruction Format (Macro Name)] GETX Dn [Assembler Mnemonic] udf15 Dn, Dn [Operation] The contents of the high-speed multiply register MDRQ are transferred to Dn. [Flag Changes] Flag Change Always 0 Always 0 1 when MSB of the transfer results is 1;...
Page 64 GETCHX (Register high-order 32-bit transfer instruction for multiply-and-accumulate operation: Store) [Instruction Format (Macro Name)] GETCHX Dn [Assembler Mnemonic] udf12 Dn, Dn [Operation] This instruction transfers the contents of the multiply-and-accumulate register MCRH to Dn. The content of the multiply-and-accumulate overflow detect register MCVF is set in the V flag. [Flag Changes] When multiply-and-accumulate operation overflow was not detected (MCVF = 0) Flag...
Page 65 GETCLX (Register low-order 32-bit transfer instruction for multiply-and-accumulate operation: Store) [Instruction Format (Macro Name)] GETCLX Dn [Assembler Mnemonic] udf13 Dn, Dn [Operation] This instruction transfers the contents of the multiply-and-accumulate register MCRL to Dn. The contents of the multiply-and-accumulate overflow detect register MCVF are set in the V flag. [Flag Changes] When multiply-and-accumulate operation overflow was not detected (MCVF = 0) Flag...
Page 66 CLRMAC (Register clear instruction for multiply-and-accumulate operation) [Instruction Format (Macro Name)] CLRMAC [Assembler Mnemonic] udf22 D0, D0 [Operation] This instruction clears the contents of the multiply-and-accumulate registers MCRH and MCRL. This instruction also clears the contents of the multiply-and-accumulate overflow detect register MCVF. [Flag Changes] Flag Change...
Page 67 MULQ (Signed high-speed multiplication instruction: between registers) [Instruction Format (Macro Name)] MULQ Dm, Dn [Assembler Mnemonic] udf00 Dm, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit. The contents of Dm (signed 32-bit integer: multiplicand) and Dn (signed 32-bit integer: multiplier) are multiplied, and the upper 32 bits of the results (64 bits) are written into the high-speed multiply register MDRQ and the lower 32 bits into Dn.
Page 68 MULQI (Signed high-speed multiplication instruction: between immediate value and register) [Instruction Format (Macro Name)] MULQI imm, Dn [Assembler Mnemonic] udf00 imm8, Dn :imm8 is sign-extended udf00 imm16, Dn :imm16 is sign-extended udf00 imm32, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit. The 32-bit data obtained by sign-extending imm (multiplicand) and the contents of Dn (signed 32-bit integer: multiplier) are multiplied, and the upper 32 bits of the results (64 bits) are written into the high-speed multiply register MDRQ and the lower 32 bits into Dn.
Page 69 MULQU (Unsigned high-speed multiplication instruction: between registers) [Instruction Format (Macro Name)] MULQU Dm, Dn [Assembler Mnemonic] udf01 Dm, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit. The contents of Dm (unsigned 32-bit integer: multiplicand) and Dn (unsigned 32-bit integer: multiplier) are multiplied, and the upper 32 bits of the results (64 bits) are written into the high-speed multiply register MDRQ and the lower 32 bits into Dn.
Page 70 MULQIU (Unsigned high-speed multiplication instruction: between immediate value and register) [Instruction Format (Macro Name)] MULQIU imm, Dn [Assembler Mnemonic] udfu01 imm8, Dn :imm8 is zero-extended udfu01 imm16, Dn :imm16 is zero-extended udfu01 imm32, Dn [Operation] This instruction performs multiplication quickly using the multiplier of the extension function unit. The 32-bit data obtained by zero-extending imm (multiplicand) and the contents of Dn (unsigned 32-bit integer: multiplier) are multiplied, and the upper 32 bits of the results (64 bits) are written into the high-speed multiply register MDRQ and the lower 32 bits into Dn.
Page 71 MAC (Signed multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MAC Dm, Dn [Assembler Mnemonic] udf28 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit. The instruction multiplies the contents of Dm (signed 32-bit integer: multiplicand) by the contents of Dn (signed 32-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower...
Page 72 MACH (Signed half word data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACH Dm, Dn [Assembler Mnemonic] udf30 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit. The instruction multiplies the contents of Dm (signed 16-bit integer: multiplicand) by the contents of Dn (signed 16-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower...
Page 73 MACB (Signed byte data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACB Dm, Dn [Assembler Mnemonic] udf32 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit. The instruction multiplies the contents of Dm (signed 8-bit integer: multiplicand) by the contents of Dn (signed 8-bit integer: multiplier), adds the resulting product to the 32-bit cumulative sum that is stored in the multiply-and- accumulate register MCRL, and then stores the new resulting 32-bit cumulative sum back in multiply-and-accumulate register MCRL.
Page 74 MACU (Unsigned multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACU Dm, Dn [Assembler Mnemonic] udf29 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit. The instruction multiplies the contents of Dm (unsigned 32-bit integer: multiplicand) by the contents of Dn (unsigned 32-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower...
Page 75 MACHU (Unsigned half word data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACHU Dm, Dn [Assembler Mnemonic] udf31 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit. The instruction multiplies the contents of Dm (unsigned 16-bit integer: multiplicand) by the contents of Dn (unsigned 16-bit integer: multiplier), it adds the product obtained by this multiplication to the cumulative sum (64 bits) of the upper 32 bits and lower 32 bits stored in the respective multiply-and-accumulate registers MCRH and MCRL, and it then stores the upper 32 bits of the result (64 bits) in the multiply-and-accumulate register MCRH and the lower...
Page 76 MACBU (Unsigned byte data multiply-and-accumulate operation instruction: between registers) [Instruction Format (Macro Name)] MACBU Dm, Dn [Assembler Mnemonic] udf33 Dm, Dn [Operation] This instruction performs the multiply-and-accumulate operation using the multiplier and adder in the extension function unit. The instruction multiplies the contents of Dm (unsigned 8-bit integer: multiplicand) by the contents of Dn (unsigned 8-bit integer: multiplier), adds the resulting product to the 32-bit cumulative sum that is stored in the multiply-and- accumulate register MCRL, and then stores the new resulting 32-bit cumulative sum back in multiply-and-accumulate register MCRL.
Page 77 SAT16 (16-bit saturation operation instruction) [Instruction Format (Macro Name)] SAT16 Dm, Dn [Assembler Mnemonic] udf04 Dm, Dn [Operation] When Dm is a 16-bit signed number which is the maximum positive value (0x00007fff) or more, the maximum positive value (0x00007fff) is written into Dn. When Dm is a 16-bit signed number which is the maximum negative value (0xffff8000) or less, the maximum negative value (0xffff8000) is stored in Dn.
Page 78 SAT24 (24-bit saturation operation instruction) [Instruction Format (Macro Name)] SAT24 Dm, Dn [Assembler Mnemonic] udf05 Dm, Dn [Operation] When Dm is a 24-bit signed number which is the maximum positive value (0x007fffff) or more, the maximum positive value (0x007fffff) is written into Dn. When Dm is a 24-bit signed number which is the maximum negative value (0xff800000) or less, the maximum negative value (0xff800000) is written into Dn.
Page 79 Extension Instruction Specifications MCST (Multiply-and-accumulate operation results 8-, 16-, 32-bit saturation operation instruction) [Instruction Format (Macro Name)] MCST Dm, Dn MCST imm8, Dn [Assembler Mnemonic] udf02 Dm, Dn udf02 imm8, Dn : Only 0x20, 0x10, and 0x08 are valid as values for imm8 [Operation] This instruction sets the contents of the multiply-and-accumulate operation overflow detect register MCVF in the V flag.
Page 80 [Flag Changes] When multiply-and-accumulate operation overflow was not detected (MCVF = 0) Flag Change Indicates that the multiply-and-accumulate operation is valid. Always 0 Undefined Undefined When multiply-and-accumulate operation overflow was detected (MCVF = 1) Flag Change Indicates that the multiply-and-accumulate operation is invalid. Always 0 Undefined Undefined...
Page 81 MCST9 (Multiply-and-accumulate operation results 9-bit saturation operation instruction/positive value conversion instruction) [Instruction Format (Macro Name)] MCST9 Dn [Assembler Mnemonic] udf03 Dn, Dn [Operation] When the 32-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate register MCRL is equal to or greater than the maximum positive value for a 9-bit signed numeric value (0x000000ff), the maximum positive value (0xff) is stored in Dn.
Page 82 MCST48 (Multiply-and-accumulate operation results 48-bit saturation operation instruction) [Instruction Format (Macro Name)] MCST48 Dn [Assembler Mnemonic] udf06 Dn, Dn [Operation] When the 64-bit result of the multiply-and-accumulate operation that is stored in the multiply-and-accumulate registers MCRH and MCRL is equal to or greater than the maximum positive value for a 48-bit signed numeric value (0x00007fffffffffff), the maximum positive value (0x00007fffffffffff) is output and bits 47 through bits 16 of that output are stored in Dn.
Page 83 BSCH (Bit search instruction) [Instruction Format (Macro Name)] BSCH Dm, Dn [Assembler Mnemonic] udf07 Dm, Dn [Operation] Bit search is performed within the bit string of the 32 bits contained in Dm from the bit position of the bit number indicated by the contents of Dn - 1 in the direction that the bit number becomes smaller.
Page 84 SWAP (Data swapping instruction that swaps bytes [high-order to low-order and vice versa] in four-byte data) [Instruction Format (Macro Name)] SWAP Dm, Dn [Assembler Mnemonic] udf08 Dm, Dn [Operation] This instruction swaps the positions of the high-order and low-order 8-bit bytes within the respective high- and low-order 16-bit half-words within the 32-bit data stored in Dm, and then swaps the positions of the high-order and low-order 16-bit half-words, and then stores the result in Dn.
Page 85 [Flag Changes] Flag Change Undefined Undefined Undefined Undefined [Programming Cautions] PSW updating by flag changes is delayed by one instruction. However, Bcc and Lcc instructions can evaluate flags without waiting for flag reflection to PSW. The operations of "udf08 imm8, Dn", "udf08 imm16, Dn" and "udf08 imm32, Dn" are not assured. In addition, a system error interrupt does not occur in these cases.
Page 86 SWAPH (Data swapping instruction [high-order to low-order and vice versa] in two-byte data) [Instruction Format (Macro Name)] SWAPH Dm, Dn [Assembler Mnemonic] udf09 Dm, Dn [Operation] This instruction swaps bits 15 through 8 of Dm with bits 7 through 0, and bits 31 through 24 with bits 23 through 16, and then stores the result in Dn.
Page 87: Programming Notes
3.2.4 Programming Notes Notes on instruction description These programming notes address instruction descriptions as well as instruction placement and combinations. Failure to heed these notes will result in misoperation. A list of these notes is shown below. Table 3-2-1 Notes on Instruction Description Preceding instruction Word/half-word data Multiply-and-accumulate...
Page 88 (a) Note on the description of word/half-word data multiply-and-accumulate instructions and multiply-and- accumulate instructions When executing a word/half-word data multiply-and-accumulate instruction followed by a multiply-and-accumulate instruction, the result produced by the word/half-word data multiply-and-accumulate instruction is used in the execution of the subsequent multiply-and-accumulate instruction. Therefore, it is essential to not initiate the subsequent multiply-and-accumulate instruction until after the result that is required from the word/half-word data multiply-and-accumulate instruction has been output.
Page 89 (b) Note on the description of word/half-word data multiply-and-accumulate instructions and MCRH, MCRL access instructions When executing a word/half-word data multiply-and-accumulate instruction followed by an MCRH, MCRL access instruction, the result produced by the word/half-word data multiply-and-accumulate instruction is used in the execution of the subsequent MCRH, MCRL access instruction.
Page 90 (c) Note on the description of byte data multiply-and-accumulate instructions and MCRH, MCRL access instructions When executing a byte data multiply-and-accumulate instruction followed by an MCRH, MCRL access instruction, the result produced by the byte data multiply-and-accumulate instruction is used in the execution of the subsequent MCRH, MCRL access instruction.
Page 91 (d) Note on the description of multiply-and-accumulate instructions and multiply-and-accumulate instructions or multiply-and-accumulate instructions and quick multiplication instructions When executing a multiply-and-accumulate instruction followed by another multiply-and-accumulate instruction or a quick multiplication instruction, at least three cycles must be inserted between the instructions. However, no problems are encountered in the case of the instruction combinations listed in the table, or when the value of the multiply-and-accumulate operation overflow detect register MCVF is not used.
Page 92 (e) Note on the description of memory access and multiply-and-accumulate instruction or high-speed multiplication instruction There is an error occasion - CPU hung-up - as written below, if High-speed multiplication instruction or Multiply- and-accumulate instruction is executed within 2 instructions after a memory access instruction that accesses to internal ROM, internal peripheral I/O space or external memory space (this space is referred to as "the space other than internal RAM"...
Page 93 Case 3: Instruction flow Memory access instruction accesses to the space other than internal RAM Lcc instruction If a stack area is in the internal RAM, any error making potential condition shown on the following cases 4 to 12 is not generated.
Page 94 Case 9: Instruction flow CALLS or JSR instruction with stack area outside internal RAM area The case where the High-speed multiplication instruction uses 32-bit immediate value is excluded. Case 10: Instruction flow TRAP instruction with stack area outside internal RAM area The case where the High-speed multiplication instruction uses 32-bit immediate value is excluded.
Page 95 In addition, please obey the following recommended conditions of 3 points when a program is developed by the assembler so that this error would not occur. As for the program developed by the PanaXSeries C compiler, the following recommended conditions are guaranteed. 1.
Page 96 Extension Instruction Specifications 3-40...
Page 97: Memory Modes
Memory Modes...
Page 98: Memory Mode Types And Selection
Memory Modes 4.1 Memory Mode Types and Selection This microcontroller has a 32-bit linear address space of up to 4 Gbytes. The address space is comprised of internal memory space built into the chip and external memory space located outside the chip. The internal memory space can be further divided into internal data space which allows high- speed data access, internal I/O space which contains the I/O ports and control registers built into the chip, and internal instruction space which mainly contains instructions.
Page 99: Memory Mode Pin Processing
4.2 Memory Mode Pin Processing Fix the input levels for the memory mode pins (MMOD0,1) as shown in Table 4-2-1 and Fig. 4-2-1 with pull-up/ pull-down resistors. For details on the pull-up/pull-down resistance, refer to “High-speed Serial Control Card Operation Manual”. Table 4-2-1 Memory Mode Setting MMOD1 MMOD0...
Page 100: Description Of Memory Mode
4.3 Description of Memory Mode 4.3.1 Memory Extension Mode The memory mode which comprises a system from both internal and external memory is called memory extension mode. This mode enables configuration of a system where the program and data make the best use of the high- speed performance of internal memory and the large capacity of external memory.
Page 101: Processor Mode
4.3.2 Processor Mode The memory mode which executes externally located instructions while using the internal data RAM and I/O ports is called processor mode. The internal instruction ROM and the internal flash memory are not used for this mode. Processor mode has memory space of up to 3 GB from addresses x'00000000 to x'BFFFFFFF. Addresses x'00000000 to x'1FFFFFFF are the internal data space (up to 512 MB) which contains data, addresses x'20000000 to x'3FFFFFFF are the internal I/O space (up to 512 MB) which is assigned to the I/O ports and control registers, and addresses x'40000000 to x'BFFFFFFF are the external memory space (up to 2 GB).
Page 102 Memory Modes...
Page 103: Operating Mode
Operating Mode...
Page 104: Overview
5.1 Overview The 32-bit microcontroller has the following three operating modes. Oscillator start/stop and CPU and peripheral circuit start/stop switching control functions are provided to support low power consumption. Operating modes 1. Reset mode (RESET) 2. Normal operation mode (NORMAL) 3.
Page 105: Reset Mode
5.2 Reset Mode • The mode in which the reset (RST) pin is active (“L” level) is called “Reset Mode”. • When the reset pin is low, the chip is reset (initialized) internally. When the reset pin makes the transition to high, the oscillation stabilization wait time is started by an internal 18-bit (when CKSEL pin = “H”) or 19-bit (when CKSEL pin = “L”) binary counter based on the oscillation clock.
Page 106: Low Power Mode
5.3 Low Power Mode Low power consumption is achieved by stopping the oscillation of the oscillators and the clock generator (CG) and stopping the clocks supplied to the CPU and peripheral circuits. Low power mode contains the following three modes and transitions to the three modes are made through software. Stop mode (STOP) In this mode, the oscillation of oscillators as well as the CG oscillation are stopped.
Page 107: Clock Generator
Clock Generator...
Page 108: Overview
6.1 Overview The CG has an internal PLL circuit; in addition to supplying clock pulses to this microcontroller at a frequency that is a multiple of the oscillating frequency of the oscillator, the CG also supplies clock pulses with the same frequency as the oscillating frequency of the oscillator, or that frequency divided by 2, to external devices.
Page 109: Description Of Operation
6.4 Description of Operation 6.4.1 Input Frequency Setting The CG input frequency range is set by the external input pin CKSEL. When CKSEL is set “H”, use an oscillator or resonator with an input frequency fosci such that 8 MHz oscillator or resonator with an input frequency fosci such that 8 MHz fosci Use of an oscillator or resonator that generates a frequency lower than 8 MHz, or higher than 20 MHz is prohibited.
Page 110: Table 6-4-3 Relationship Between The Input Frequency And The Sysclk, Mclk
The relationship between the input frequency (fosci) and the SYSCLK, MCLK, and IOCLK multiples and frequencies is shown in Table 6-4-2, and the relationship between the input frequency (fosci) and the SYSCLK, MCLK, and IOCLK multiples and frequencies when reset is released is shown in Table 6-4-3. Table 6-4-2 Relationship between the Oscillation Mode and the SYSCLK, MCLK, Input frequency...
Page 111: Internal Memory
Internal Memory...
Page 112: Overview
7.1 Overview The MN103001G has 128 Kbytes of instruction ROM and 8 Kbytes of internal data RAM. The MN1030F01K has 256 Kbytes of flash memory and 8 Kbytes of internal data RAM. The instruction ROM/flash memory and data RAM are connected to the CPU core via a 64-bit bus and a 32-bit bus, respectively. 7.2 Features The features of the internal memory are listed below.
Page 113: Internal Memory Configuration
7.3 Internal Memory Configuration The internal instruction ROM is located in the internal memory space at address x'40000000 to x'4001FFFF, while the internal flash memory is located at address x'40000000 to x'4003FFFF and the internal data RAM is located at address x'00000000 to x'00001FFF.
Page 114 Internal Memory...
Page 115: Bus Controller (Bc)
Bus Controller (BC)
Page 116: Overview
Bus Controller (BC) 8.1 Overview The bus controller (BC) controls interfacing between the CPU core, internal I/O (peripherals), and devices external to the chip. The bus controller also handles arbitration between the internal and external buses. In addition, in an interface with devices external to the chip, it is possible to select whether address pins and data pins are separate or multiplex.
Page 117: Bus Configuration
8.3 Bus Configuration Fig. 8-3-1 shows the bus configuration. The chip’s internal buses are the ROM bus between the CPU core and internal instruction ROM/internal flash memory, the RAM bus between the CPU core and internal data RAM, the BC bus between the CPU core and the bus controller, and the I/O bus between the bus controller and internal I/O. The EX bus is an external bus.
Page 118: Fig. 8-4-1 Block Diagram For The Bus Controller
Bus Controller (BC) Fig. 8-4-1 Block Diagram for the Bus Controller...
Page 119: Pin Functions
8.5 Pin Functions The external pin functions relating to the bus controller are shown in Table 8-5-1. Table 8-5-1 External Pin Functions Relating to the Bus Controller Pin name Input/output Number of pins OSCI Input OSCO Output CKSEL Input MMOD1 to 0 Input EXMOD1 to 0 Input...
Page 120: Table 8-5-2 Operating Status Of Pins Concerning Bc
Bus Controller (BC) Table 8-5-2 shows the operating status of the external pins concerning BC. Table 8-5-2 Operating Status of Pins Concerning BC Operating status SLEEP mode SYSCLK Operate A23 to 0 Operate ADM15 to 0 Operate D15 to 0 Operate RAS2 to 1 Operate...
Page 121: Description Of Registers
8.6 Description of Registers Table 8-6-1 lists the bus controller registers. The settings of these registers are used in timing control, DRAM interface control, etc. Table 8-6-1 List of Bus Control Registers Address Name x'32000020 Memory control register 0B x'32000022 Memory control register 1B x'32000024 Memory control register 2B x'32000026 Memory control register 3B x'32000030 Memory control register 0A...
Page 122: Memory Block 0 Control Register
Bus Controller (BC) 8.6.1 Memory Block 0 Control Register Memory control register 0A/B is used to set the memory block 0 read/write timing and synchronous/asynchronous mode through software. Memory control register 0A Register symbol: MEMCTR0A Address: x’32000030 Purpose: Sets the access timing, etc., for external memory space block 0. Bit No.
Page 123 Memory control register 0B Register symbol: MEMCTR0B Address: x’32000020 Purpose: Sets the bus mode, access timing, etc., for external memory space block 0. Bit No. name WEN4WEN3WEN2WEN1WEN0 ASN2 ASN1 ASN0 ASA1 ASA0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit No.
Page 124: Memory Block 1 Control Register
Bus Controller (BC) 8.6.2 Memory Block 1 Control Register Memory control register 1A/B is used to set the memory block 1 read/write timing, synchronous/asynchronous mode, DRAM mode, page mode, and bus width through software. Memory control register 1A Register symbol: MEMCTR1A Address: x’32000032 Purpose:...
Page 125 When using DRAM (Memory control register 1B B1DRAM = 1) Bit No. Bit name 1 to 0 BCS1 to 0 Row address setup timing (use as ASR parameter) 3 to 2 EA1 to 0 Column address setup timing (use as ASC parameter) 5 to 4 ADE1 to 0 Column address output timing...
Page 126 Memory control register 1B Register symbol: MEMCTR1B Address: x’32000022 Purpose: Sets the bus mode, access timing, etc., for external memory space block 1. Bit No. name WEN4WEN3WEN2WEN1WEN0 ASN2 ASN1 ASN0 ASA1 ASA0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When not using DRAM (Memory control register 1B B1DRAM = 0) Bit No.
Page 127 When using DRAM (Memory control register 1B B1DRAM = 1) Bit No. Bit name DRAM Block 1 DRAM space setting Block 1 bus mode Block 1 software page mode enable Block 1 bus width 7 to 6 ASA1 to 0 Always set to "01".
Page 128: Memory Block 2 Control Register
8.6.3 Memory Block 2 Control Register Memory control register 2A/B is used to set the memory block 2 read/write timing, synchronous/asynchronous mode, fixed wait/handshaking mode, DRAM mode, page mode, and bus width through software. Memory control register 2A Register symbol: MEMCTR2A Address: x’32000034 Purpose:...
Page 129 When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1) Bit No. Bit name 1 to 0 BCS1 to 0 DK detection wait cycle (use as DW parameter) 3 to 2 EA1 to 0 RE/WE assert timing 5 to 4 ADE1 to 0 Address output end timing...
Page 130 Memory control register 2B Register symbol: MEMCTR2B Address: x’32000024 Purpose: Sets the bus mode, access timing, etc., for external memory space block 2. Bit No. name WEN4WEN3WEN2WEN1WEN0 ASN2 ASN1 ASN0 ASA1 ASA0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W When using fixed wait mode and not using DRAM (Memory control register 2B B2DRAM = 0, B2WM = 0) Bit No.
Page 131 When using handshaking mode (Memory control register 2B B2DRAM = 0, B2WM = 1) Bit No. Bit name Description DRAM Block 2 DRAM space setting Block 2 wait mode Block 2 bus mode Block 2 software page mode enable Block 2 bus width 7 to 6 ASA1 to 0 AS assert timing...
Page 132 After the reset is released, block 2 is set as follows: Address output end timing RE negate timing WE negate timing RE/WE assert timing Bus cycle start timing Bus cycle end timing AS assert timing AS negate timing The bus width is 16 bits, and synchronous fixed wait mode is set. 8-18 3MCLK 29MCLK...
Page 133: Memory Block 3 Control Register
8.6.4 Memory Block 3 Control Register Memory control register 3A/B is used to set the memory block 3 read/write timing, synchronous/asynchronous mode, fixed wait/handshaking mode, and bus width through software. However, the handshaking mode can only be set when (MCLK frequency/SYSCLK frequency) = 4. Memory control register 3A Register symbol: MEMCTR3A Address:...
Page 134 When using handshaking mode (Memory control register 3B B3WM = 1) Bit No. Bit name 1 to 0 BCS1 to 0 DK detection wait cycle (used as parameter DW) 3 to 2 EA1 to 0 RE/WE assert timing 5 to 4 ADE1 to 0 Address output end timing 10 to 6...
Page 135 When using handshaking mode (Memory control register 3B B3WM = 1) Bit No. Bit name Block 3 wait mode Block 3 bus mode Block 3 bus width 7 to 6 ASA1 to 0 AS assert timing 10 to 8 ASN2 to 0 AS negate timing Set so that: 15 to 11...
Page 136: Dram Control Register
8.6.5 DRAM control register DRAM control register Register symbol: DRAMCTR Address: x'32000040 Purpose: Stores various DRAM mode settings when DRAM is connected. Bit No. – – – – name Reset Access Bit No. Bit name DRAME DRAM control circuit enable PAGE Page mode enable REFE...
Page 137: Refresh Count Register
8.6.6 Refresh count register Register symbol: REFCNT Address: x'32000042 Purpose: Sets the DRAM refresh interval when DRAM is connected. Bit No. REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC REFC name Reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit No.
Page 138: Page Row Address Register
8.6.7 Page Row Address Register Page Row Address Register Register symbol: PRAR Address: x'32000044 Purpose: Sets the row address for DRAM software page mode. Bit No. PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR PRAR name Reset Access...
Page 139 Notes when switching the internal clock multiplier Be aware of the following points when setting the clock control register CKCTR and changing the internal clock multiplier. • If external memory is accessed immediately after setting the clock control register CKCTR, the multiplier for the internal clock MCLK may change in the middle of the access, resulting in a change in the external bus timing.
Page 140: Space Partitioning
8.7 Space Partitioning In extension memory mode (MMOD 1 to 0 = "LH"), the 1 GB memory space from x'80000000 to x'BFFFFFFF becomes external memory space; in processor mode (MMOD 1 to 0 = "HL"), the 2 GB memory space from x'40000000 to x'BFFFFFFF becomes external memory space.
Page 141: Fig. 8-7-2 Space Partitioning
Extension memory mode x'00000000 2 GB x'80000000 x'90000000 x'A0000000 1 GB x'B0000000 x'C0000000 System reserved 1 GB x'FFFFFFFF Processor mode x'00000000 1 GB x'40000000 x'50000000 x'60000000 x'70000000 x'80000000 x'90000000 2 GB x'A0000000 x'B0000000 x'C0000000 System reserved 1 GB x'FFFFFFFF x'90000000 x'90800000 x'91000000 x'91800000...
Page 142: Operation Clocks
8.8 Operation Clocks MCLK, IOCLK, and SYSCLK are used as BC operation clocks. Table 8-8-1 shows the ratio of each clock versus the oscillation input clock (OSCI). Table 8-8-1 Frequency Ratios of BC Operation Clocks Oscillation mode Clock control register setting CKSEL Using Not using...
Page 143: Bus Cycle
8.10 Bus Cycle Depending on the value of the external input pin CKSEL and the internal registers, the MCLK frequency can be either 1/2, 1, 2, or 4 times the input frequency, and the IOCLK frequency can be either 1/8, 1/4, 1/2, or 1 times the input frequency.
Page 144: Store Buffer
Bus Controller (BC) 8.11 Store Buffer The bus controller has one store buffer (with a 32-bit data width) built in, and is used to avoid a time penalty when conducting a store operation in internal I/O or external memory. The CPU store operation is completed storing the address, data, and access size in the store buffer, and is executed with no wait states.
Page 145: Accessing The Internal I/O Space
8.12 Accessing the Internal I/O Space Accesses to the internal I/O space (I/O register) are performed through the I/O bus, with the bus controller controlling the interface for read/write requests from the CPU. Accesses between the bus controller and the internal I/O space are executed in synchronization with IOCLK.
Page 146: External Memory Space Access
Bus Controller (BC) 8.13 External Memory Space Access (Non-DRAM Spaces) During an access to external memory, the BC controls the interface for the read/write request from the CPU. Table 8-13-1 lists the transactions that are supported for the external bus. Table 8-13-1 External Bus Transaction Address Bus width...
Page 147: 16-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Separate Mode
Bus Controller (BC) 8.13.1 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode Setting of the various parameters for external memory access is performed in memory control registers 0 to 3, corresponding to each block. In synchronous mode, the bus access is initiated in synchronization with SYSCLK. When fixed wait insertion is specified, the bus access ends to the timing set in the memory control register.
Page 148: Fig. 8-13-2 Access Timing On A 16-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Separate Mode (Mclk = Sysclk Multiplied By 2)
Bus Controller (BC) MCLK SYSCLK :Undefined Fig. 8-13-2 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 149: 16-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Separate Mode
8.13.2 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode When using handshaking, bus access starts once synchronization with SYSCLK is achieved, and after the data acknowledge signal (DK) is asserted, 2 MCLK cycles are consumed by the BC internally and then the access is completed according to the specified parameters.
Page 150: Fig. 8-13-5 Access Timing On A 16-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Separate Mode (Mclk = Sysclk Multiplied By 2)
MCLK SYSCLK : Undefined Fig. 8-13-5 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 151: 16-Bit Bus In Asynchronous Mode And In Address/Data
8.13.3 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode Asynchronous mode is used for accessing external memory at high speed; the address signals, CSn signals, etc., are output asynchronously with the SYSCLK but in synchronization with the internal MCLK. In asynchronous mode, accesses are all by fixed wait insertion.
Page 152: Fig. 8-13-8 Access Timing On A 16-Bit Bus In Asynchronous Mode And In Address/Data Separate Mode (Mclk = Sysclk Multiplied By 2)
MCLK SYSCLK : Undefined Fig. 8-13-8 Access Timing on a 16-bit Bus in Asynchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 153: 8-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Separate Mode
Bus Controller (BC) 8.13.4 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode 8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to "0"...
Page 154 MCLK SYSCLK A[0]=0 D7-0 Read low- order side : Undefined Fig. 8-13-11 Access Timing on a 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 155: 8-Bit Bus With Handshaking, In Synchronous Mode And In
8.13.5 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode 8-bit bus mode is set for blocks 2 and 3 by setting the BnBW bit to “0” in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0"...
Page 156: Fig. 8-13-13 Access Timing On A 8-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Separate Mode (Mclk = Sysclk Multiplied By 4)
MCLK SYSCLK “H” D7-0 Read low-order side : Undefined MCLK SYSCLK “H” D7-0 Write low-order side : Undefined Fig. 8-13-13 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 4) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 157: Fig. 8-13-14 Access Timing On A 8-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Separate Mode (Mclk = Sysclk Multiplied By 2)
MCLK SYSCLK “H” D7-0 Read low-order side : Undefined MCLK SYSCLK “H” D7-0 Write low-order side : Undefined Fig. 8-13-14 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 158: Fig. 8-13-15 Access Timing On A 8-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Separate Mode (Mclk = Sysclk)
MCLK SYSCLK “H” D7-0 Read low-order side : Undefined MCLK SYSCLK “H” D7-0 Write low-order side : Undefined Fig. 8-13-15 Access Timing on a 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Separate Mode (MCLK = SYSCLK) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 159: Address/Data Separate Mode
8.13.6 8-bit Bus in Asynchronous Mode and in Address/Data Separate Mode 8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to “0” in the corresponding memory control register. In 8-bit bus mode, half-word access (16 bits) is performed by means of two external accesses, with A[0] = "0"...
Page 160: 16-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Multiplex Mode
8.13.7 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use common pins for the memory address and memory data signals (pins ADM15 to 0). In synchronous mode, the bus access starts in synchronization with SYSCLK, and when fixed wait states are inserted, the access ends according to the timing that was set in the memory control register.
Page 161: Fig. 8-13-18 Access Timing On A 16-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk Multiplied By 2)
MCLK SYSCLK A23* to 16 addr addr ADM15 to 0 RWSEL : Undefined : Undefined or Hi-Z : A23 also serves as CS3 Fig. 8-13-18 Access Timing on a 16-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 2) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 162: 16-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Multiplex Mode
8.13.8 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 2 and 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0). When using handshaking, bus access starts once synchronization with SYSCLK is achieved, and after the data acknowledge signal (DK) is asserted, 2 MCLK cycles are consumed by the BC internally and then the access is completed according to the specified parameters.
Page 163: Fig. 8-13-20 Access Timing On A 16-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk Multiplied By 4)
MCLK SYSCLK A23* to 16 addr ADM15 to 0 addr RWSEL : Undefined : Undefined or Hi-Z : A23 also serves as CS3 Fig. 8-13-20 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK multiplied by 4) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 164: Fig. 8-13-22 Access Timing On A 16-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk)
MCLK SYSCLK A23* to 16 addr ADM15 to 0 addr RWSEL : Undefined : Undefined or Hi-Z : A23 also serves as CS3 Fig. 8-13-22 Access Timing on a 16-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode (MCLK = SYSCLK) For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.”...
Page 165: 16-Bit Bus In Asynchronous Mode And In Address/Data
8.13.9 16-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0). Asynchronous mode is used for accessing external memory at high speed;...
Page 166: 8-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Multiplex Mode
Bus Controller (BC) 8.13.10 8-bit Bus with Fixed Wait States, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0).
Page 167: Fig. 8-13-24 Access Timing On A 8-Bit Bus With Fixed Wait States, In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk Multiplied By 4)
MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 RWSEL “H” : Undefined : Undefined or Hi-Z : A23 also serves as CS3 MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 RWSEL “H” : Undefined : Undefined or Hi-Z : A23 also serves as CS3 Fig.
Page 168 MCLK SYSCLK A23* to 16 ADM15 to 0 RWSEL “H” : Undefined : Undefined or Hi-Z : A23 also serves as CS3 MCLK SYSCLK A23* to 16 ADM15 to 0 RWSEL “H” : Undefined : Undefined or Hi-Z : A23 also serves as CS3 Fig.
Page 169 MCLK SYSCLK BCS=0 A23* to 16 ADM15 to 0 RWSEL “H” : Undefined : Undefined or Hi-Z : A23 also serves as CS3 MCLK SYSCLK BCS=0 A23* to 16 ADM15 to 0 RWSEL “H” : Undefined : Undefined or Hi-Z : A23 also serves as CS3 Fig.
Page 170: 8-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Multiplex Mode
8.13.11 8-bit Bus with Handshaking, in Synchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 2 and 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0). 8-bit bus mode is set for blocks 2 and 3 by setting the BnBW bit to “0”...
Page 171: Fig. 8-13-27 Access Timing On A 8-Bit Bus With Handshaking, In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk Multiplied By 4)
MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 RWSEL “H” : Undefined Read low-order side : Undefined or Hi-Z : A23 also serves as CS3 MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 RWSEL “H” : Undefined Write low-order side : Undefined or Hi-Z : A23 also serves as CS3...
Page 172: Fig. 8-13-28 Access Timing On A 8-Bit Bus With Handshaking In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk Multiplied By 2)
MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 RWSEL “H” : Undefined Read low-order side : Undefined or Hi-Z : A23 also serves as CS3 MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 RWSEL “H” : Undefined Write low-order side : Undefined or Hi-Z : A23 also serves as CS3...
Page 173: Fig. 8-13-29 Access Timing On A 8-Bit Bus With Handshaking In Synchronous Mode And In Address/Data Multiplex Mode (Mclk = Sysclk)
MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 RWSEL “H” : Undefined Read low-order side : Undefined or Hi-Z : A23 also serves as CS3 MCLK SYSCLK A23* to 16 A[0]=0 ADM15 to 0 A[0]=0 RWSEL “H” : Undefined Write low-order side : Undefined or Hi-Z : A23 also serves as CS3...
Page 174: 8-Bit Bus In Asynchronous Mode And In Address/Data
Bus Controller (BC) 8.13.12 8-bit Bus in Asynchronous Mode and in Address/Data Multiplex Mode By setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, blocks 0 to 3 use multiplex pins for the memory address and memory data signals (pins ADM15 to 0). 8-bit bus mode is set for block 0 by setting the mode through the MMOD1 and 0 pins and the EXMOD1 and 0 pins, and for blocks 1 to 3 by setting the BnBW bit to “0”...
Page 175: Fig. 8-13-30 Access Timing On A 8-Bit Bus In Asynchronous Mode And
MCLK SYSCLK A23* to 16 ADM15 to 0 RWSEL “H” : Undefined : Undefined or Hi-Z : A23 also serves as CS3 MCLK SYSCLK A23* to 16 ADM15 to 0 RWSEL “H” : Undefined : Undefined or Hi-Z : A23 also serves as CS3 Fig.
Page 176: External Memory Space Access (Dram Space)
Bus Controller (BC) 8.14 External Memory Space Access (DRAM Space) 8.14.1 DRAM Space Blocks 1 and 2 can be used as DRAM space by setting the BnDRAM bits in memory control registers 1B/2B and setting the DRAME bit in DRAM control register. The DRAM bus cycle is always not synchronized the external clock (but is synchronized with MCLK), and performs address multiplexed output, RAS/CAS signal output, etc.
Page 177: Fig. 8-14-2 Case Where The Ras Precharge Interval Is At Its Minimum
Minimum value for the RAS Precharge interval When consecutive DRAM accesses are performed, the RAS precharge interval is shortest when performing an access of type (1) or (2) below while the PAGE bit is set to “0” in the DRAM control register: (1) Word/half-word access while the bus width is set to 8 bits (2) Word access while the bus width is set to 16 bits Because the minimum value for the RAS precharge interval is:...
Page 178: Fig. 8-14-3 Example Of An 8-Bit Data Write Using 2 We Control (16-Bit Bus Width)
Bus Controller (BC) 2 WE control/2 CAS control DRAM that permits byte/word control can be supported by selecting either one of the following two methods: • 2 WE control: The two pins WE1 and WE0 are used for byte/word control. •...
Page 179: Dram
8.14.2 DRAM page mode If the PAGE bit in the DRAM control register is set to “1”, page mode access is enabled, making high-speed access in page mode possible for following accesses to DRAM. (1) Word/half-word access when the bus width is set to 8 bits (2) Word access when the bus width is set to 16 bits Fig.
Page 180: Software
Bus Controller (BC) 8.14.3 Software Page Mode Software page mode is a mode that forcibly initiates page mode by setting the control register. Operation within software page mode is as described below. Refer to Fig. 8-14-6. • When the mode is initiated, the contents of PRAR are output as the row address. •...
Page 181: Fig. 8-14-6 Software Page Mode Read/Write Timing
MCLK CAO+1 RASn MCLK CAO+1 RASn Fig. 8-14-6 Software Page Mode Read/Write Timing For details on the various timing settings, refer to the description of the memory control register in section 8.6, “Description of Registers.” Column Column (a) Read Timing Column Column Column...
Page 182: Dram Refresh
Bus Controller (BC) [Restrictions on Use] (1) While software page mode is in effect, external access outside of the block in question is prohibited. Cancel software page mode before accessing an external memory space other than the block for which software page mode is set.
Page 183: Fig. 8-14-7 Dram Refresh Operation
Refresh count value REFC Count interval Refresh is executed during idle cycle REFE bit is set Fig. 8-14-7 DRAM Refresh Operation MCLK SYSCLK RAS1 RAS2 “H” “H” “Hi-Z” Refresh For details on the ASR and RP settings, refer to the explanations in section 8.6.2, “Memory Block 1 Control Register,”...
Page 184: Bus Arbitration
Bus Controller (BC) 8.15 Bus Arbitration In this microcontroller, bus arbitration is implemented through the bus authority request signal (BR) and the bus authority release signal (BG). If an external device asserts the BR signal, then once the current bus access that is being executed is completed, the BG signal is asserted and the bus authority is released to the external device.
Page 185: Fig. 8-15-1 Bus Arbitration Timing 1
MCLK SYSCLK “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” RASn “Hi-Z” “Hi-Z” Fig. 8-15-1 Bus Arbitration Timing 1 (Bus Authority Release/Bus Authority Acquisition, nfr = 4) MCLK SYSCLK “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” RASn “Hi-Z” “Hi-Z” Fig. 8-15-2 Bus Arbitration Timing 2 (Bus Authority Release/Bus Authority Acquisition, External device Standby...
Page 186: Fig. 8-15-3 Bus Arbitration Timing 3
Bus Controller (BC) MCLK SYSCLK RASn Fig. 8-15-3 Bus Arbitration Timing 3 (Bus Authority Release/Bus Authority Acquisition, MCLK SYSCLK “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” “Hi-Z” RASn “Hi-Z” “Hi-Z” External device Fig. 8-15-4 Bus Arbitration Timing 4 (Refresh Request Generated While Bus Authority Has Been Released) 8-72 “Hi-Z”...
Page 187: Cautions
8.16 Cautions These cautions concern the BC. These cautions must be heeded, since failure to do so may result in misoperation. 1. Do not change the contents of the relevant memory control register and the DRAM control register while accessing external memory space, except when software page mode is not in effect. 2.
Page 188 Bus Controller (BC) _____ Designate the bus authority request pin (BR) as a general-purpose input port, and the bus authority release _____ pin (BG) as a general-purpose output port, for instance, so that bus requests cannot be accepted during execution of a BSET or BCLR instruction. 8-74...
Page 189: Interrupt Controller
Interrupt Controller...
Page 190: Overview
Interrupt Controller 9.1 Overview The interrupt controller processes non-maskable interrupts and level interrupts (internal interrupts and external interrupts). For external pins, the microcontroller has eight external interrupt pins and one non-maskable interrupt pin. 9.2 Features • Up to four interrupt requests can be accepted by each group. •...
Page 191: Block Diagram
9.4 Block Diagram Non-maskable CPU core Level: 0 to 6 The interrupt level can be set separately for each group. (However, GROUP 0 and GROUP 1 are non-maskable.) NMIRQ pin interrupts GROUP Watchdog timer overflow System error — GROUP Reserved for system Timer 0 underflow Timer 1 underflow GROUP...
Page 192: Fig. 9-4-2 Block Diagram 2
Serial 0 reception Serial 0 transmission GROUP — — Serial 1 reception Serial 1 transmission GROUP — — Serial 2 reception Serial 2 transmission GROUP — — Serial 3 reception Serial 3 transmission GROUP — — External interrupt 0 — GROUP —...
Page 193 External interrupt 3 — GROUP — — External interrupt 4 — GROUP — — External interrupt 5 — GROUP — — External interrupt 6 — GROUP — — External interrupt 7 — GROUP — — A/D conversion end — GROUP —...
Page 194: Description Of Registers
9.5 Description of Registers This interrupt controller includes an interrupt control registers, an interrupt accepted group register, and an external interrupt condition specification register. Table 9-5-1 lists the interrupt controller registers. Address Name x'34000100 Non-maskable interrupt control register x'34000108 Group 2 interrupt control register x'3400010C Group 3 interrupt control register x'34000110 Group 4 interrupt control register x'34000114 Group 5 interrupt control register...
Page 195 Non-maskable interrupt control register Register symbol: G0ICR (NMICR) Address: x'34000100 Purpose: This register determines whether a non-maskable interrupt has been generated. Bit No. name Reset Access Bit No. Bit name Description NMIF External non-maskable interrupt request flag WDIF Watchdog timer overflow interrupt request flag SYSEF System error interrupt request flag The method of clearing flag differs according to the interrupt request flags.
Page 196 Group n interrupt control register GnICR (n = 2 to 19) Registers G2ICR to G19ICR control level interrupts for groups 2 to 19, respectively. Each register confirms the group interrupt level as well as the enabling, request, and detection of interrupts within the respective group.
Page 197 Bit No. Bit name Description 11 to 8 IE3 to 0 Group n interrupt enable register • This register is used to specify whether an interrupt is enabled or not. • When an IEn(n=3 to 0) bit is set to "1", the corresponding interrupt is enabled. •...
Page 198 Interrupt Controller Group 2 interrupt control register Register symbol: G2ICR Address: x'34000108 Purpose: This register is used to enable group 2 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit No.
Page 199 Group 3 interrupt control register Register symbol: G3ICR Address: x'3400010C Purpose: This register is used to enable group 3 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit No.
Page 200 Interrupt Controller Group 4 interrupt control register Register symbol: G4ICR Address: x'34000110 Purpose: This register is used to enable group 4 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit No.
Page 201 Group 5 interrupt control register Register symbol: G5ICR Address: x'34000114 Purpose: This register is used to enable group 5 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No. Bit name Description T10UID...
Page 202 Interrupt Controller Group 6 interrupt control register Register symbol: G6ICR Address: x'34000118 Purpose: This register is used to enable group 6 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No.
Page 203 Group 7 interrupt control register Register symbol: G7ICR Address: x'3400011C Purpose: This register is used to enable group 7 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No. Bit name Description SC0RID...
Page 204 Interrupt Controller Group 8 interrupt control register Register symbol: G8ICR Address: x'34000120 Purpose: This register is used to enable group 8 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No.
Page 205 Group 9 interrupt control register Register symbol: G9ICR Address: x'34000124 Purpose: This register is used to enable group 9 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No. Bit name Description SC2RID...
Page 206 Interrupt Controller Group 10 interrupt control register Register symbol: G10ICR Address: x'34000128 Purpose: This register is used to enable group 10 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No.
Page 207 Group 11 interrupt control register Register symbol: G11ICR Address: x'3400012C Purpose: This register is used to enable group 11 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No. Bit name Description IQ0ID...
Page 208 Interrupt Controller Group 12 interrupt control register Register symbol: G12ICR Address: x'34000130 Purpose: This register is used to enable group 12 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No.
Page 209 Group 13 interrupt control register Register symbol: G13ICR Address: x'34000134 Purpose: This register is used to enable group 13 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No. Bit name Description IQ2ID...
Page 210 Interrupt Controller Group 14 interrupt control register Register symbol: G14ICR Address: x'34000138 Purpose: This register is used to enable group 14 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No.
Page 211 Group 15 interrupt control register Register symbol: G15ICR Address: x'3400013C Purpose: This register is used to enable group 15 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No. Bit name Description IQ4ID...
Page 212 Interrupt Controller Group 16 interrupt control register Register symbol: G16ICR Address: x'34000140 Purpose: This register is used to enable group 16 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No.
Page 213 Group 17 interrupt control register Register symbol: G17ICR Address: x'34000144 Purpose: This register is used to enable group 17 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No. Bit name Description IQ6ID...
Page 214 Interrupt Controller Group 18 interrupt control register Register symbol: G18ICR Address: x'34000148 Purpose: This register is used to enable group 18 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No.
Page 215 Group 19 interrupt control register Register symbol: G19ICR Address: x'3400014C Purpose: This register is used to enable group 19 interrupts, and to confirm interrupt requests and detection. Bit No. name LV2 LV1 LV0 Reset Access R/W R/W R/W Bit No. Bit name Description ADID...
Page 216 Interrupt Controller Interrupt accepted group register Register symbol: IAGR Address: x'34000200 Purpose: This register is used to read the group number that generated the interrupt request. Bit No. name Reset Access Bit No. Bit name Description 6 to 2 GN4 to 0 Group number register The group number that was accepted is stored in GN 4 to 0.
Page 217 External interrupt condition specification register Register symbol: EXTMD Address: x'34000280 Purpose: This register specifies the external interrupt generation conditions. Set the desired level or edge for each pin. Bit No. name TG1 TG0 TG1 TG0 TG1 TG0 TG1 TG0 TG1 TG0 TG1 TG0 TG1 TG0 TG1 TG0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
Page 218: Description Of Operation
9.6 Description of Operation The following interrupt processing is performed. • Non-maskable interrupts • Level interrupts • Internal interrupts • External interrupts In the event of a level interrupt, an interrupt group determination is made, and an interrupt request is sent to the CPU.
Page 219 [Cautions] 1. Maintain external pin interrupt signals for at least 10, 5, or 2.5 SYSCLK cycles when SYSCLK frequency) = 1, 2, or 4, respectively. The interrupt cannot be detected if the signal is not maintained for at least that long. However, when recovering from HALT mode in response to an external pin interrupt signal, maintain the signal for at least 22, 11, or 5.5 SYSCLK cycles when recovering from STOP mode in response to an external pin interrupt signal, maintain the signal for at least 10,...
Page 220 Interrupt Controller 9-32...
Page 221: Bit Timers
8-bit Timers...
Page 222: Overview
10.1 Overview This device has 12 reload timers built in. All are down counters that can be used as interval timers and event counters. Eight of the timers are also capable of PWM output. 10.2 Features The features of the 8-bit timers are described below. •...
Page 223: Block Diagram
10.3 Block Diagram Fig. 10-3-1 shows a block diagram for timers 0 to 3. Fig. 10-3-2 shows a block diagram for timers 4 to B. Figures 10-3-3 to 10-3-6 show connection diagrams for the 8-bit timers. Timer n (n = 0, 1, 2, 3) TMnIN0 TMnIN1 TMnIN2...
Page 224: Fig. 10-3-2 8-Bit Timer Block Diagram (Timers 4 To B)
8-bit Timers Timer n (n = 4, 5, 6, 7, 8, 9, A, B) TMnIN0 TMnIN1 TMnIN2 TMnIN3 TMnIN4 TMnIN5 TMnIN6 TMnIN7 Count operation enabled TMnMD mode register Output waveform control Fig. 10-3-2 8-bit Timer Block Diagram (Timers 4 to B) 10-4 TMnBR base register...
Page 225: Fig. 10-3-3 8-Bit Timer Connection Diagram (Overall)
Reset Prescaler TMPSCNT IOCLK 1/32 Prescaler control register TMnIN0 TM0IRQ TMnIN1 Timer 0 TMnIN2 TM1IRQ TM2IRQ TMnIN4 Timer 1 TMnIN5 TM3IRQ TMnIN6 TM0IN7 Timer 2 TM1IN7 TM2IN7 TM3IN7 Timer 3 TM0OUT TM1OUT TM2OUT Block Timer 0 to 3 TM3OUT Timer output selection register TMOSL TMnIN0...
Page 226: Fig. 10-3-4 8-Bit Timer Connection Diagram (Timer 0 To 3 Block)
8-bit Timers TM0IO pin input TM1IO pin input TM2IO pin input TM3IO pin input Fig. 10-3-4 8-bit Timer Connection Diagram (Timer 0 to 3 block) 10-6 TM0IN0 TM0CI TM0IN1 TM0IRQ TM0IN2 TM0IN3 Timer 0 TM0IN4 TM0OUT TM0IN5 TM0IN6 TM0CLK TM0IN7 TM0CO TM1IN0 TM1CI...
Page 227: Fig. 10-3-5 8-Bit Timer Connection Diagram (Timer 4 To 7 Block)
TM4IO pin input TM5IO pin input TM6IO pin input TM7IO pin input Fig. 10-3-5 8-bit Timer Connection Diagram (Timer 4 to 7 block) TM4IN0 TM4CI TM4IN1 TM4IRQ TM4IN2 TM4IN3 Timer 4 TM4IN4 TM4OUT TM4IN5 TM4IN6 TM4CLK TM4IN7 TM4CO TM5IN0 TM5CI TM5IN1 TM5IRQ TM5IN2...
Page 228: Fig. 10-3-6 8-Bit Timer Connection Diagram (Timer 8 To B Block)
8-bit Timers TM0IO pin input TM1IO pin input TM2IO pin input TM3IO pin input Fig. 10-3-6 8-bit Timer Connection Diagram (Timer 8 to B block) 10-8 TM8IN0 TM8CI TM8IN1 TM8IRQ TM8IN2 TM8IN3 Timer 8 TM8IN4 TM8OUT TM8IN5 TM8IN6 TM8CLK TM8IN7 TM8CO TM9IN0 TM9CI...
Page 229: Functions
10.4 Functions Table 10-4-1 lists the functions of each 8-bit timer. Table 10-4-1 List of 8-bit Timer Functions Timer Interval timer Event counter Timer output — PWM output Interrupt — SIF0, 2 clock source — SIF1, 3 clock source A/D conversion —...
Page 230: Description Of Registers
8-bit Timers 10.5 Description of Registers Table 10-5-1 lists the 8-bit timer registers. Table 10-5-1 List of 8-bit Timer Registers (1/2) Address Name x'34001000 Timer 0 mode register x'34001001 Timer 1 mode register x'34001002 Timer 2 mode register x'34001003 Timer 3 mode register x'34001004 Timer 4 mode register x'34001005 Timer 5 mode register x'34001006 Timer 6 mode register...
Page 231: Table 10-5-1 List Of 8-Bit Timer Registers (2/2)
Table 10-5-1 List of 8-bit Timer Registers (2/2) Address Name x'34001034 Timer 4 compare register x'34001035 Timer 5 compare register x'34001036 Timer 6 compare register x'34001037 Timer 7 compare register x'34001038 Timer 8 compare register x'34001039 Timer 9 compare register x'3400103A Timer A compare register x'3400103B Timer B compare register x'34001070 Timer ouput selection...
Page 232 8-bit Timers Timer n mode register (n = 0, 1, 2, 3) Register symbol: TMnMD Address: x'34001000 (n=0), x'34001001 (n=1), x'34001002 (n=2), x'34001003 (n=3) Purpose: This register controls the operation of timer n. Bit No. TMn TMn name CNE LDE Reset Access R/W R/W...
Page 233 Timer n mode register (n = 4, 5, 6, 7, 8, 9, A, B) Register symbol: TMnMD Address: x'34001004 (n=4), x'34001005 (n=5), x'34001006 (n=6), x'34001007 (n=7), x'34001008 (n=8), x'34001009 (n=9), x'3400100A (n=A), x'3400100B (n=B) Purpose: This register controls the operation of timer n. Bit No.
Page 234: Table 10-5-2 Pwm Output Waves
8-bit Timers [Note] When setting TMnCNE to "1", do so while TMnLDE is set to "0". When setting TMnLDE to "1", do so while TMnCNE is set to "0". Operation is not guaranteed if TMnCNE and TMnLDE are both set to "1" at the same time. TMnOM0 setting Upon initialization "L"...
Page 235: Table 10-5-3 8-Bit Timer Clock Sources
Table 10-5-3 8-bit Timer Clock Sources TMnCK[2:0] Timer 0 Setting IOCLK IOCLK/8 IOCLK/32 Setting prohibited Setting prohibited Timer 1 underflow Timer 2 underflow TM0IO pin input TMnCK[2:0] Timer 4 Setting IOCLK IOCLK/8 IOCLK/32 Setting prohibited Timer 0 underflow Timer 1 underflow Timer 2 underflow TM4IO pin input TMnCK[2:0]...
Page 236 8-bit Timers Timer n base register (n = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B) Register symbol: TMnBR Address: x'34001010 (n = 0), x'34001011 (n = 1), x'34001012 (n = 2), x'34001013 (n = 3), x'34001014 (n = 4), x'34001015 (n = 5), x'34001016 (n = 6), x'34001017 (n = 7), x'34001018 (n = 8), x'34001019 (n = 9), x'3400101A (n =A), x'3400101B (n = B) Purpose:...
Page 237 Timer n compare register (n = 4, 5, 6, 7, 8, 9, A, B) Register symbol: TMnCMP Address: x'34001034 (n = 4), x'34001035 (n = 5), x'34001036 (n = 6), x'34001037 (n = 7), x'34001038 (n = 8), x'34001039 (n = 9), x'3400103A (n = A), x'3400103B (n = B) Purpose: This is the timer n compare register.
Page 238 8-bit Timers Timer output selection register Register symbol: TMOSL Address: x'34001070 Purpose: This register selects the 8-bit timer output signal. Bit No. name Reset Access Bit No. Bit name Description TMOSL0 Timer output selection flag 0 Selects the output signal for the TM0IO pin. TMOSL1 Timer output selection flag 1 Selects the output signal for the TM1IO pin.
Page 239 Prescaler control register Register symbol: TMPSCNT Address: x'34001071 Purpose: This register controls the prescaler operation. Bit No. TMPS name Reset Access Bit No. Bit name Description 6 to 0 – "0" is returned when these bits are read. TMPSCNE Prescaler operation enable flag. Enables/disables operation of the 1/8 IOCLK and 1/32 IOCLK prescaler.
Page 240: Description Of Operation
8-bit Timers 10.6 Description of Operation This section describes the operation of the 8-bit timers. 10.6.1 Interval Timers and Timer Output When using an 8-bit timer as an interval timer, make the appropriate settings according to the procedure described below. The timer in question then operates as an interval timer that generates interrupts on the set cycle.
Page 241 (6) Enable the timer counting operation. Once TMnCNE is set to "1" in the TMnMD register, the counting operation starts. Once the counting operation is enabled, an underflow interrupt request is generated at fixed intervals. In addition, the pin output is inverted each time that this interrupt is generated, and the value that is set in TMnBR is loaded into TMnBC.
Page 242 8-bit Timers TMnBC value TMnBR setting value TMnCNE Interrupt request Timer output IOCLK TMnBC value x'01 x'00 Interrupt request signal (TMnIRQ) Timer output (TMnOUT) Fig 10-6-2 Interval Timer Operation (When Clock Source = IOCLK) 10-22 Fig 10-6-1 Interval Timer Operation TMnBR value TMnBR value-1 (value in TMnBR + 1) x IOCLK TMnBR value...
Page 243: Fig. 10-6-3 Interval Timer Operation (Using Prescaler)
8-bit Timers IOCLK Counter clock TMnBC value x'01 x'00 TMnBR value TMnBR value-1 TMnBR value-2 Interrupt request signal (TMnIRQ) Timer output (TMnOUT) Fig. 10-6-3 Interval Timer Operation (Using Prescaler) 10-23...
Page 244: Event Counting
8-bit Timers 10.6.2 Event Counting When using an 8-bit timer for event counting, make the settings according to the procedure described below. When using the timers as a 16-, 24- or 32-bit timer by means of a cascaded connection, refer to section 10.6.3, "Cascaded Connection."...
Page 245: Fig. 10-6-4 Event Counting Operation
8-bit Timers [Note] Pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively. Event counting is not possible when IOCLK is stopped (in HALT or STOP mode). IOCLK Pin input (TMnIO)
Page 246: Cascaded Connection
8-bit Timers 10.6.3 Cascaded Connection The 8-bit timers can be cascaded together in the combinations shown in Fig. 10-6-5. When using cascaded 8-bit timers as a 16-bit timer: (Higher) (Lower) Timer 3 Timer 2 Timer 7 Timer 6 Timer B Timer A When using cascaded 8-bit timers as a 24-bit timer: (Highest)
Page 247 Make the settings described below when cascading 8-bit timers. (1) Set the timer division ratio. Set the timer division ratio in TMnBR. (Example 1) When using timers 0 and 1 as 16-bit timers and setting the interrupt cycle to x'1234: In order to set the interrupt cycle to x'1234, x'1234 - 1 = x'1233 must be set in TMnBR.
Page 248 8-bit Timers (4) Enable counting operation Enable the counting operation by either one of the following two methods: 1) Enable the counting operation for each of the cascaded timers one at a time, in order, starting from the highest timer. 2) Enable the counting operation for all of the cascaded timers simultaneously.
Page 249 Differences between using a timer as a prescaler and when cascaded The following explanation of these differences uses the cases where the clock source for timer 1 is set to "timer 0 underflow" and to "cascaded with timer 0" as examples. When "timer 0 underflow"...
Page 250 8-bit Timers When "cascaded with timer 0" is set, operation is as shown in Fig. 10-6-7. (IOCLK is selected as the clock source for timer 0.) If TM1BC does not equal x'00, then when TM0BC underflows, the value in TM0BC is x'FF and the value in TM1BC is decremented by one.
Page 251: Pwm Output
10.6.4 PWM Output Make the settings as described below when using an 8-bit timer to output a PWM waveform. (Timers 4 to B) The timers cannot be cascaded when outputting a PWM waveform. Procedure for initiating operation (1) Set the PWM output cycle. Set the cycle in TMnBR.
Page 252 8-bit Timers Once the counting operation is enabled, the PWM waveform is output and an underflow interrupt request is generated. (Refer to Fig. 10-6-8 and 10-6-9.) If the value in the TMnBR register is changed while the counting operation is in progress, that value is loaded as the initial value when the next underflow is generated, and the cycle of the PWM waveform changes.
Page 253: Fig. 10-6-8 Pwm Output
8-bit Timers IOCLK x'00 TMnBR value TMnCMP value x'00 TMnBR value TMnBC value Interrupt request signal (TMnIRQ) Timer output (TMnOUT) TMnCMP value x IOCLK (TMnBR value +1) x IOCLK Fig. 10-6-8 PWM Output (When Clock Source = IOCLK, and "L" Level Is Output Upon Initialization) IOCLK Counter clock x'00...
Page 254 8-bit Timers 10-34...
Page 255 16-bit Timers...
Page 256: Overview
16-bit Timers 11.1 Overview This microcontroller has four 16-bit timers built in. Three are reload timers (down-counters) that can be used as interval timers or event counters. The other is an up-counter that has two compare/capture registers built in. 11.2 Features The features of the 16-bit timers are described below.
Page 257: Block Diagram
11.3 Block Diagram Fig. 11-3-1 shows the block diagram for timer 10, and Fig. 11-3-2 shows the block diagram for timers 11 to 13. Timer 10 TM10IN0 TM10IN1 TM10IN2 TM10IN4 TM10IN5 TM10IN6 TM10IN7 TM10INA TM10INB Fig. 11-3-1 16-bit Timer Block Diagram (Timer 10) TM10BC Binary counter Capture...
Page 258: Fig. 11-3-2 16-Bit Timer Block Diagram (Timers 11, 12 And 13)
16-bit Timers Timer n (n = 11, 12, 13) TMnIN0 TMnIN1 TMnIN2 TMnIN4 TMnIN5 TMnIN6 TMnIN7 Counting operation enable TMnMD Mode register Fig. 11-3-2 16-bit Timer Block Diagram (Timers 11, 12, and 13) 11-4 TMnBR Base register Load Reload TMnBC Underflow Binary counter Reset...
Page 259: Fig. 11-3-3 16-Bit Timer Connection Diagram
Prescaler control register TMPSCNT Reset IOCLK prescaler IOCLK 1/32 TM10IN0 TM10IRQ TM10IN1 TM10IN2 TM10AIRQ TM10IN4 Timer 10 TM10IN5 TM10BIRQ TM10IN6 TM10IN7 TM10OA TM10OB TM10IA TM10IB TM11IN0 TM11IN1 TM11IRQ TM11IN2 Timer 11 TM11IN4 TM11IN5 TM11OUT TM11IN6 TM11IN7 TM12IN0 TM12IN1 TM12IRQ TM12IN2 Timer 12 TM12IN4 TM12IN5...
Page 260: Fig. 11-3-4 Timer 10 Compare/Capture Register Block Diagram
Fig. 11-3-4 shows the block diagram for the timer 10 compare/capture registers. Timer 10 compare/capture registers ( TM10CA, TM10CB ) Capture timing Capture enable Capture register mode Double-buffer mode Load timing Single-buffer mode Initialization flag (TM10LDE) Compare register mode Fig. 11-3-4 Timer 10 Compare/Capture Register Block Diagram Fig.
Page 261: Functions
11.4 Functions Table 11-4-1 lists the functions of each 16-bit timer. Table 11-4-1 List of 16-bit Timer Functions Timer Timer 10 Up-/down-counting Up-counting Interval timer Event counting (Edge can be selected) Toggled output (2 outputs) Variable cycle and PWM output duty ratio: Fixed cycle: 2 outputs Overflow...
Page 262: Description Of Registers
16-bit Timers 11.5 Description of Registers Table 11-5-1 lists the 16-bit timer registers. Table 11-5-1 List of 16-bit Timer Registers Address Name x'34001080 Timer 10 mode register x'34001082 Timer 11 mode register x'34001084 Timer 12 mode register x'34001086 Timer 13 mode register x'34001092 Timer 11 base register x'34001094...
Page 263 Timer 10 mode register Register symbol: TM10MD Address: x'34001080 Purpose: This register controls the operation of timer 10. Bit No. TM10 TM10 TM10 TM10 TM10 name CNE LDE PME PM1 PM0 Reset Access R/W R/W R/W R/W R/W Bit No. Bit name Description TM10CK0...
Page 264 16-bit Timers Bit No. Bit name Description TM10TGE External trigger start enable flag Enables/disables timer start by an external trigger. 0: Disables timer start by an external trigger. (The trigger input is ignored.) 1: Enables timer start by an external trigger. 10 to 8 —...
Page 265 Timer n mode register (n = 11, 12, 13) Register symbol: TMnMD Address: x'34001082 (n=11), x'34001084 (n=12), x'34001086 (n=13) Purpose: This register controls the operation of timer n. Bit No. TMn TMn – – name CNE LDE Reset Access R/W R/W Bit No.
Page 266 16-bit Timers Timer n base register (n = 11, 12, 13) Register symbol: TMnBR Address: x'34001092 (n=11), x'34001094 (n=12), x'34001096 (n=13) Purpose: This register sets the initial value and the underflow cycle for the timer n binary counter. Bit No. TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn TMn name BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0...
Page 267 Timer 10 compare/capture A mode register Register symbol: TM10MDA Address: x'340010B0 Purpose: This register controls the operation of the timer 10 compare/capture A register. This register also sets the waveform that is output to the TM10IOA pin. Bit No. TM10 TM10 TM10 TM10 name AM1 AM0 AEG ACE Reset...
Page 268 16-bit Timers Timer 10 compare/capture B mode register Register symbol: TM10MDB Address: x'340010B1 Purpose: This register controls the operation of the timer 10 compare/capture B register. This register also sets the waveform that is output to TM10IOB pin. Bit No. TM10 TM10 TM10 TM10 name BM1 BM0 BEG BCE...
Page 269 Timer 10 compare/capture A register Register symbol: TM10CA Address: x'340010C0 Purpose: This is the timer 10 compare/capture A register. Bit No. TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 name CA15 CA14 CA13 CA12 CA11 CA10 CA9 CA8 CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W...
Page 270 16-bit Timers Timer 10 compare/capture B register Register symbol: TM10CB Address: x'340010D0 Purpose: This is the timer 10 compare/capture B register. Bit No. TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 TM10 name CB15 CB14 CB13 CB12 CB11 CB10 CB9 CB8 CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0 Reset Access...
Page 271 Prescaler control register Register symbol: TMPSCNT Address: x'34001071 Purpose: This register controls prescaler operations. Bit No. TMPS – – – name Reset Access Bit No. Bit name Description 6 to 0 — "0" is returned when these bits are read. TMPSCNE Prescaler operation enable flag Enables/disables 1/8 IOCLK and 1/32 IOCLK prescaler operation.
Page 272: Description Of Operation Of Timer 10
16-bit Timers 11.6 Description of Operation of Timer 10 This section describes the operation of timer 10. Timer 10 includes an up-counter and two compare/capture registers. The compare/capture registers are independent of each other, and can each be used as either a compare register or a capture register. 11.6.1 Compare Register Settings In order to use either the timer 10 compare/capture A register or B register as a compare register, the following settings must be made according to the procedure described below before timer 10 is initialized.
Page 273: Capture Register Settings
IOCLK TM10BC value (when TM10CAE = 1) TM10BC value (when TM10CAE = 0) Compare/capture A interrupt request Fig. 11-6-1 Compare Register Operation (When Clock Source = IOCLK) 11.6.2 Capture Register Settings In order to use either the timer 10 compare/capture A register or B register as a capture register, the following settings must be made according to the procedure described below before timer 10 is initialized.
Page 274: Fig. 11-6-2 Input Capture Operation (When "Rising Edge" Is Selected)
16-bit Timers If dual-edge was selected, the capture operation is performed when either a rising or falling edge is input. It is not possible to determine which edge was input. (The pin input level cannot be read.) The capture operation can be disabled even while counting is in progress by setting TM10ACE to "0". When TM10CAE is set to "1"...
Page 275: Pin Output Settings
11.6.3 Pin Output Settings Timer 10 can be used to output a variety of waveforms to the TM10IOA and TM10IOB pins. (1) Setting the output level upon initialization If the TM10LDE flag in the TM10MD register is set to "1", thus initializing timer 10, the output level on the TM10IOA pin is the value that is set for the TM10AEG flag in the TM10MDA register.
Page 276: Fig. 11-6-3 Pin Output Waveform (1)
16-bit Timers Examples of TM10IOA pin output waveforms are shown below. Output for the TM10IOB pin is similar. Fig. 11-6-3 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA, and reset when TM10BC matches TM10CB" is set. If the set and reset conditions occur simultaneously, the reset takes precedence.
Page 277: Fig. 11-6-5 Pin Output Waveform (3)
Fig. 11-6-5 shows the output waveform for the TM10IOA pin when "Set when TM10BC matches TM10CA" is set. Match between TM10BC and TM10CA TM10IOA pin output (when TM10AEG = 0) TM10IOA pin output (when TM10AEG = 1) Fig. 11-6-6 shows the output waveform for the TM10IOA pin when "Reset when TM10BC matches TM10CA" is set.
Page 278: Starting By An External Trigger
16-bit Timers 11.6.4 Starting by an External Trigger Timer 10 can be started up by input on the TM10IOB pin. Fig. 11-6-8 illustrates the startup operation. The compare/capture A and B registers can be used as compare registers or as capture registers. Procedure for initiating operation (1) Select the input edge on which timer 10 is to start.
Page 279: Fig. 11-6-8 Timer 10 Startup By An External Trigger (When "Rising Edge" Is Selected)
Procedure for ending operation (1) Disable timer startup by an external trigger. Set TM10TGE in the TM10MD register to "0". (2) Stop the counting operation. Set TM10CNE in the TM10MD register to "0". If TM10TGE and TM10CNE are both set to "0" simultaneously, there is a possibility that TM10CNE will be set again, depending on the pin input timing.
Page 280: One-Shot Operation
16-bit Timers 11.6.5 One-shot Operation It is possible to stop timer 10 when TM10BC and TM10CA match. Figs. 11-6-9 and 11-6-10 illustrate the operation that stops timer 10. The compare/capture B register can be used as a compare register or as a capture register. Procedure for initiating operation (1) Set the compare/capture A register mode.
Page 281: Fig. 11-6-9 One-Shot Operation (When Clock Source = Ioclk)
Procedure for ending operation • When the timer was started by a program (TM10TGE = 0) Stop the counting operation. Set TM10CNE in the TM10MD register to "0". • When the timer was started by an external trigger (TM10TGE = 1) Disable timer startup by an external trigger.
Page 282: Interval Timer
16-bit Timers 11.6.6 Interval Timer When using timer 10 as an interval timer, make the settings according to the procedure described below. This interval timer generates a compare/capture A interrupt request on the cycle that is set. (Refer to Figs. 11-6-11 to 11-6-14.) The compare/capture B register can be used as a compare register or as a capture register.
Page 283: Fig. 11-6-11 Timer 10 Interval Timer Operation (1)
If the value in the TM10CA register is changed while the counting operation is in progress, the value in the buffer is loaded into the compare register the next time that TM10BC is cleared, and the interrupt cycle is then changed. If the interrupt cycle will be changed while the counting operation is in progress, set TM10CA as a double-buffer compare register.
Page 284: Fig. 11-6-13 Timer 10 Interval Timer Operation (When Clock Source = Ioclk)
16-bit Timers IOCLK TM10BC value x'0000 Compare/capture A interrupt request Compare/capture A Set value 1 register (TM10CA) Compare register Set value 1 A buffer Fig. 11-6-13 Timer 10 Interval Timer Operation (When Clock Source = IOCLK) IOCLK Count clock TM10BC value Compare/capture A interrupt request Compare/capture A...
Page 285: Event Counting
11.6.7 Event Counting When using timer 10 as an event counter, make the settings according to the procedure described below. This event counter generates a compare/capture A interrupt when it has counted the specified number of edges. (Refer to Fig. 11-6-15.) The compare/capture B register can be used as a compare register or as a capture register.
Page 286: Fig. 11-6-15 Event Count Operation (When "Rising Edge" Is Selected)
16-bit Timers Once the counting operation is enabled, TM10BC is incremented each time that the specified edge is input to the TM10IOB pin. Once (value in compare/capture A register + 1) edges are counted, TM10BC is cleared and a compare/capture A register interrupt request is generated. If the value in the TM10CA register is changed while the counting operation is in progress, the value in the buffer is loaded into the compare register the next time that TM10BC is cleared, and the interrupt cycle is then changed.
Page 287: Description Of Operation Of Timers 11, 12 And 13
11.7 Description of Operation of Timers 11, 12, and 13 This section describes the operation of timers 11, 12, and 13. Timers 11, 12, and 13 have built-in registers for setting the initial values, and down-counters. These timers can be used as interval timers and as event counters.
Page 288: Fig. 11-7-1 Interval Timer Operation
16-bit Timers Once the counting operation is enabled, an underflow interrupt request is generated on a regular cycle. In addition, with each interrupt the pin output is inverted and the value in TMnBR is loaded into TMnBC. If the value in the TMnBR register is changed while the counting operation is in progress, this changed value is loaded as the initial value the next time that an underflow is generated, and the interrupt cycle is then changed.
Page 289: Fig. 11-7-2 Interval Timer Operation (When Clock Source = Ioclk)
IOCLK TMnBC value TMnBR value x'0001 x'0000 Interrupt request signal (TMnIRQ) Timer output (TMnOUT) Fig. 11-7-2 Interval Timer Operation (When Clock Source = IOCLK) IOCLK Count clock TMnBC value x'0001 x'0000 Interrupt request signal (TMnIRQ) Timer output (TMnOUT) Fig. 11-7-3 Interval Timer Operation (When Using the Prescaler) TMnBR value TMnBR value -1 x'0000...
Page 290: Event Counting
16-bit Timers 11.7.2 Event Counting When using timer 11, 12, or 13 as an event counter, make the settings according to the procedure described below. Procedure for initiating operation (1) Set the timer division ratio. Set the division ratio in TMnBR. An interrupt request is then generated when the rising edge is counted (value set in TMnBR + 1) times in the pin input.
Page 291: Fig. 11-7-4 Event Count Operation
[Note] The pin input is sampled according to IOCLK. Input a signal with a pulse width of at least 6, 3, or 1.5 SYSCLK cycles when (MCLK frequency/SYSCLK frequency) = 1, 2, or 4, respectively. Also note that event counting is not possible when IOCLK is stopped (in HALT or STOP mode). IOCLK Pin input (TMnIO)
Page 292 16-bit Timers 11-38...
Page 293: Watchdog Timer
Watchdog Timer...
Page 294: Overview
12.1 Overview This microcontroller has a 25-bit binary counter built in that can be used as a 16- to 25-bit watchdog timer. A watchdog timer overflow generates a nonmaskable interrupt, enabling the watchdog timer overflow to be identified. The watchdog timer is also used as an oscillation stabilization wait timer. 12.2 Features •...
Page 295: Block Diagram
12.3 Block Diagram Level output/Pulse output selection Internal reset Internal reset signal generation SYSCLK STOP mode Oscillation stabilization wait release, interrupt request 8-bit binary counter Reset wdovf SYSCLK 8-bit binary counter Reset WDBC Clock source 16-bit binary counter selection CKSEL input WDCTR “H”...
Page 296: Description Of Registers
12.4 Description of Registers Table 12-4-1 lists the watchdog timer registers. Table 12-4-1 List of Watchdog Timer Registers Address Name x'34004000 Watchdog binary counter x'34004008 Watchdog timer control register x'34004004 Reset control register Watchdog binary counter Register symbol: WDBC Address: x'34004000 Purpose: Reading this counter returns the counter value of the high-order eight bits of the watchdog...
Page 297 Watchdog timer control register Register symbol: WDCTR Address: x'34004008 Purpose: This register sets the watchdog timer operation control conditions. Bit No. name CNE RST OVT OVF Reset Access R/W R/W R/W Bit No. Bit name Description WDCK0 Clock source selection (LSB) WDCK1 Clock source selection WDCK2...
Page 298 — When this bit is read, a "0" is returned. WDOVF The value of the watchdog timer overflow output. WDOVT Watchdog timer overflow output selection WDRST Binary counter reset, watchdog timer overflow output (WDOVF flag) reset WDCNE Watchdog timer count operation control flag [Notes] When resetting the value of watchdog overflow by writing the WDRST flag, do not simultaneously overwrite the WDOVT flag.
Page 299: Description Of Operation
12.5 Description of Operation Oscillation stabilization wait operation The watchdog timer operates as an oscillation stabilization wait timer after the reset state is released or when the microcontroller recovers from STOP mode (Fig. 12-5-1). The watchdog timer operates in this capacity even if the WDCNE flag is "0". When recovering from STOP mode, the watchdog timer operates as a counter of the number of bits specified by WDCK2 to 0 (Fig.
Page 300: Fig. 12-5-2 Operation Diagram 2: When Recovering From Stop Mode
Stop mode release request (external pin interrupt) OSCI input SYSCLK Internal clock, SYSCLK supply enabled Watchdog timer count value (when CKSEL = “H” and the oscillating input frequency is 15 MHz) Fig. 12-5-2 Operation Diagram 2: When Recovering from STOP Mode 12-8 Interrupt Oscillation stabilization...
Page 301: Fig. 12-5-3 Operation Diagram 3: Watchdog Operation
Watchdog operation If the WDCNE flag is set to "1" and the watchdog operation is enabled, a non-maskable interrupt is generated if a watchdog timer overflow occurs. When an overflow occurs, the watchdog timer overflow output is output to the WDOVF flag. Pulse output or level output can be selected through the WDOVT flag.
Page 302 Watchdog Timer 12-10...
Page 303: Serial Interface
Serial Interface...
Page 304: Overview
Serial Interface 13.1 Overview This microcontroller has three types of internal serial interfaces. One is a general-purpose serial interface for which clock synchronous mode, UART mode, or I2C mode can be specified; this interface supports one channel. The second interface is a clock synchronous serial interface that supports two channels. The third interface is UART serial interface that supports one channel.
Page 305: General-Purpose Serial Interface
13.2 General-purpose serial interface 13.2.1 Features Serial interface 0 is a general-purpose serial interface for which clock sync mode, UART mode, or I2C mode can be specified. The features of each mode are described below. <Clock synchronous mode> • Parity None, 0 fixed, 1 fixed, even, odd •...
Page 306 <UART mode> • Parity None, 0 fixed, 1 fixed, even, odd • Character length 7 bits, 8 bits • Transmission and reception bit sequence LSB or MSB selectable • Clock source 1/8 or 1/32 of IOCLK 1/8 of timer 3 or timer 9 underflow 1/8 of external clock •...
Page 307: Block Diagram Of General-Purpose Serial Interface
13.2.2 Block Diagram of General-Purpose Serial Interface Fig 13-2-1 shows the block diagram for the general-purpose serial interface section. Serial interface 0 Parity bit addition Stop bit addition SC0ICR Interrupt mode register Transmission interrupt request Interrupt request generation Reception interrupt request SC0STR Status register SC0CTR...
Page 308: Description Of Registers For The General-Purpose Serial Interface
Serial Interface 13.2.3 Description of Registers for the General-Purpose Serial Interface The general-purpose serial interface includes the registers listed in Table 13-2-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection. Table 13-2-1 List of General-Purpose Serial Interface Registers Address Name x'34000800 Serial 0 control register...
Page 309 SC0PB2 Parity bit selection (MSB) 000: None 001, 010, 011: Setting prohibited 100: 0 fixed 101: 1 fixed 110: Even (even number of ones) 111: Odd (odd number of ones) SC0CLN Character length selection 0: 7 bits 1: 8 bits SC0TOE SBT0 pin output control 0: When the internal clock is selected, the SBT0 pin is an output only while...
Page 310 Serial Interface Serial 0 interrupt mode register Register symbol: SC0ICR Address: x'34000804 Purpose: This register selects the sources for transmission interrupts and reception interrupts for serial interface 0. Bit No. name Reset Access R/W R/W Bit No. Bit name Description SC0RI Reception interrupt factor selection —...
Page 311 Serial 0 reception buffer Register symbol: SC0RXB Address: x'34000809 Purpose: This register reads in the reception data of serial interface 0. Bit No. name RXB7 RXB6 RXB5 RXB4 RXB3 RXB2 RXB1 RXB0 Reset Access Reception data is gotten by reading this buffer at the end of reception. In the case of a 7-bit transfer, the MSB (bit 7) is "0".
Page 312: Description Of Operation
Serial Interface 13.2.4 Description of Operation <Clock synchronous mode> Clock synchronous mode connection Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer. When SBT pin is an output only during transmission (SC0TOE = "0"), it is necessary to pull up SBT pin. In addition, when using SBO pin as a data input/output (SC0MD1 and 0 = "11"), it is necessary to pull up SBO pin.
Page 313: Fig. 13-2-3 Timing Chart (1)
Clock synchronous mode timing <Transmission> • One-byte transfer with 8-bit data length and parity on SBO pin SBT pin Data write SC0TXF flag SC0TBF flag Interrupt request (when set to “transmission end”) Interrupt request (when set to “transmission buffer empty”) •...
Page 314: Fig. 13-2-5 Timing Chart (3)
Serial Interface <Reception> • One-byte transfer with 8-bit data length and parity on SBI pin SBT pin SC0RXF flag SC0RBF flag Interrupt request Data read • Two-byte transfer with 8-bit data length and parity off SBI pin bp1 bp2 bp3 bp4 bp5 bp6 SBT pin SC0RXF flag SC0RBF flag...
Page 315: Fig. 13-2-7 Timing Chart (5)
When a reception error is generated • Transfer in clock synchronous mode with 8-bit data length, parity on. SBI pin SBT pin SC0RXF flag SC0RBF flag “H” SC0OEF flag SC0PEF flag Interrupt request When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Page 316: Fig. 13-2-8 Connections
<UART mode> UART mode connection Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer. The SBO pin is always an output, and the SBI pin is always an input. Transmission External clock Undirectional transfer UART mode bit rates In UART mode, it is necessary to select an appropriate bit rate and serial interface input clock.
Page 317: Table 13-2-2 Bit Rates (1) (When Ioclk = 15 Mhz)
Table 13-2-2 Bit rates (1) (When IOCLK = 15 MHz) When cascaded Bit rate (bit/s) Timer division ratio 19 200 9 600 4 800 2 400 1 200 1 563 Table 13-2-3 Bit Rates (2) (When IOCLK = 12 MHz) When cascaded Bit rate (bit/s) Timer division ratio...
Page 318: Fig. 13-2-9 Timing Chart (6)
UART mode timing <Transmission> • Transfer with 8-bit data length, parity on, and 1 stop bit SBO pin Data write SC0TXF flag SC0TBF flag Interrupt request (when set to “transmission end”) Interrupt request (when set to “transmission buffer empty”) • Two-byte transfer with 7-bit data length, parity on, and 1 stop bit SBO pin Data write SC0TXF flag...
Page 319: Fig. 13-2-11 Timing Chart (8)
<Reception> • Transfer with 8-bit data length, parity on, and 1 stop bit SBI pin SC0RXF flag SC0RBF flag Interrupt request Data read • Two-byte transfer with 7-bit data length, parity on, and 1 stop bit SBI pin bp1 bp2 bp3 bp4 bp5 bp6 SC0RXF flag SC0RBF flag Interrupt request...
Page 320: Fig. 13-2-13 Timing Chart (10)
Serial Interface When a reception error is generated • Transfer in UART mode with 8-bit data length, parity on, and 1 stop bit SBI pin SC0RXF flag SC0RBF flag “H” SC0OEF flag SC0PEF flag SC0FEF flag Interrupt request When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Page 321: Fig.13-2-14 Connections
<I2C mode> I2C mode connection It is possible to connect a device that is capable of slave transmission and slave reception. SDA and SCL require pull-up resistors. Connect pull-up resistors externally. The SBO pin is an open-drain input/output, and the SBT pin is an open drain output. Master transmission/ reception...
Page 322 Serial Interface I2C mode transmission/reception The transmission/reception procedure in I2C mode is described below. (Refer to Fig. 13-2-15.) • Make the initial settings as described below. (1) I/O port setting Set the SBT and SBO pins as general-purpose input ports. For details on the settings, refer to the chapter on I/O ports.
Page 323 • Perform data transmission/reception (B) according to the procedure described below: (1) Ack setting "Ack" is represented by the parity bits. Set the parity bit selection flags (SC0PB2 to 0) to "1 fixed" or "0 fixed" in accordance with the communications protocol for the device that is connected.
Page 324: Fig. 13-2-15 Timing Chart (11)
Serial Interface If the above procedures do not satisfy the AC timing of the device that is connected, send the stop sequence according to the procedure described below. (1)' SBT pin setting Set the SBT pin as a general-purpose input port. When the pin switches to a general-purpose input port, SCL goes high.
Page 325: Fig. 13-2-16 Timing Chart (12)
• Resend the start sequence (D) according to the procedure described below. (Refer to Fig. 13-2-16.) (1) SBO pin setting Set the SBO pin as a general-purpose input port. When the pin switches to a general-purpose input port, SDA goes high. (2) SBT pin setting Set the SBT pin as a general-purpose input port.
Page 326: Clock Synchronous Serial Interface
13.3 Clock Synchronous Serial Interface 13.3.1 Features Serial interfaces 1 and 2 are clock synchronous serial interfaces. Their features are described below. • Parity None, 0 fixed, 1 fixed, even, odd • Character length 7 bits, 8 bits • Transmission and reception bit sequence LSB or MSB selectable •...
Page 327: Block Diagram Of Clock Synchronous Serial Interface
13.3.2 Block Diagram of Clock Synchronous Serial Interface Fig 13-3-1 shows the block diagram for the clock synchronous serial interface sections. Serial interface n (n = 1, 2) Parity bit addition SCnICR Interrupt mode register Transmission interrupt request Interrupt request Reception generation interrupt request...
Page 328: Description Of Registers For The Clock Synchronous Serial Interface
Serial Interface 13.3.3 Description of Registers for the Clock Synchronous Serial Interface The clock synchronous serial interfaces include the registers listed in Table 13-3-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection. Table 13-3-1 List of Clock Synchronous Serial Interface Registers Address Name...
Page 329 Serial n control register (n = 1, 2) Register symbol: SCnCTR Address: x'34000810 (n =1), x'34000820 (n =2) Purpose: This register sets the serial interface n operation control conditions. Bit No. – – name TXE RXE Reset Access R/W R/W Bit No.
Page 330 Serial Interface Bit No. Bit name Description SCnTOE SBTn pin output control SCnOD Transmission and reception bit sequence selection SCnMD0 Protocol selection 13 to 11 — "0" is returned when these bits are read. SCnRXE Reception operation enable SCnTXE Transmission operation enable 13-28 0: When the internal clock is selected, the SBTn pin is an output only while transmission is in progress (the SBTn pin is an input when in standby...
Page 331 Serial n interrupt mode register (n = 1, 2) Register symbol: SCnICR Address: x'34000814 (n = 1), x'34000824 (n = 2) Purpose: This register selects the sources for transmission interrupts and reception interrupts for serial interface n. Bit No. – –...
Page 332 Serial Interface Serial n transmission buffer (n = 1, 2) Register symbol SCnTXB Address: x'34000818 (n=1), x'34000828 (n=2) Purpose: This register writes the transmission data to serial interface n. Bit No. name TXB7 TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W...
Page 333 Serial n status register (n=1,2) Register symbol: SCnSTR Address: x'3400081C (n=1), x'3400082C (n=2) Purpose: This register indicates the status of serial interface n. Bit No. name TXF RXF TBF RBF Reset Access Bit No. Bit name Description SCnOEF Overrun error indication SCnPEF Parity error indication 3 to 2...
Page 334: Description Of Operation
Serial Interface 13.3.4 Description of Operation Clock synchronous serial interface n connection (n=1,2) Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer. When SBT pin is an output only during transmission (SCnTOE = "0"), it is necessary to pull up SBT pin. In addition, when using SBO pin as a data input/output (SCnMD0 = "1"), it is necessary to pull up SBO pin.
Page 335: Fig. 13-3-3 Timing Chart (13)
Clock synchronous serial interface timing <Transmission> • One-byte transfer with 8-bit data length and parity off SBO pin SBT pin Data write SCnTXF flag SCnTBF flag Interrupt request (when set to “transmission end”) Interrupt request (when set to “transmission buffer empty”) •...
Page 336: Fig. 13-3-5 Timing Chart (15)
<Reception> • One-byte transfer with 7-bit data length and parity on SBI pin SBT pin SCnRXF flag SCnRBF flag Interrupt request Data read • Two-byte transfer with 8-bit data length and parity on SBI pin bp1 bp2 bp3 bp4 bp5 bp6 SBT pin SCnRXF flag SCnRBF flag...
Page 337: Fig. 13-3-7 Timing Chart (17)
When a reception error is generated • Transfer with 7-bit data length, parity on SBI pin SBT pin SCnRXF flag “H” SCnRBF flag SCnOEF flag SCnPEF flag Interrupt request When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Page 338: Universal Asynchronous Receiver-Transceiver Serial Interface
13.4 Universal Asynchronous Receiver-Transceiver Serial Interface 13.4.1 Features Serial interface 3 is a UART serial interface. Its features are described below. • Parity None, 0 fixed, 1 fixed, even, odd • Character length 7 bits, 8 bits • Transmission and reception bit sequence LSB or MSB selectable •...
Page 339: Block Diagram Of Uart Serial Interface
13.4.2 Block Diagram of UART Serial Interface Fig 13-4-1 shows the block diagram for the UART serial interface sections. Serial interface 3 Parity bit addition Stop bit addition SC3ICR Interrupt mode register Transmission interrupt request Interrupt request generation Reception interrupt request SC3STR Status register SC3CTR...
Page 340: Description Of Registers For The Uart Serial Interface
Serial Interface 13.4.3 Description of Registers for the UART Serial Interface The UART serial interface includes the registers listed in Table 13-4-1. These registers are used for settings such as clock source selection, parity bit selection, and protocol selection. Table 13-4-1 List of UART Serial Interface Registers Address Name x'34000830 Serial 3 control register...
Page 341 Serial 3 control register Register symbol: SC3CTR Address: x'34000830 Purpose: This register sets the serial interface 3 operation control conditions. Bit No. name TXE RXE BKE TWS Reset Access R/W R/W R/W R/W Bit No. Bit name Description SC3CK0 Clock source selection (LSB) SC3CK1 Clock source selection (MSB) —...
Page 342 Serial Interface Bit No. Bit name Description SC3TWE Transmission interrupt enable SC3OD Transmission and reception bit sequence selection 11 to 10 — "0" is returned when this bit is read SC3TWS Transmission interrupt code selection SC3BKE Break transmission (SBO3 pin is fixed at "0") SC3RXE Reception operation enable SC3TXE...
Page 343 Serial 3 interrupt mode register Register symbol: SC3ICR Address: x'34000834 Purpose: This register selects the sources for transmission interrupts and reception interrupts for serial interface 3. Bit No. – – – name Reset Access R/W R/W Bit No. Bit name Description SC3RI Reception interrupt factor selection...
Page 344 Serial Interface Serial 3 transmission buffer Register symbol: SC3TXB Address: x'34000838 Purpose: This register writes the transmission data of serial interface 3. Bit No. name TXB7 TXB6 TXB5 TXB4 TXB3 TXB2 TXB1 TXB0 Reset Access R/W R/W R/W R/W R/W R/W R/W R/W Data is transmitted by writing it to this buffer.
Page 345 Serial 3 status register Register symbol: SC3STR Address: x'3400083C Purpose: This register indicates the status of serial interface 3. Bit No. name TXF RXF TBF RBF CTS Reset Access Bit No. Bit name Description SC3OEF Overrun error indication SC3PEF Parity error indication SC3FEF Framing error indication SC3CTS...
Page 346 Serial 3 timer register Register symbol: SC3TIM Address: x'3400083D Purpose: This register sets the timer that is used for internal division for serial interface 3. Bit No. – name TIM6 TIM5 TIM4 TIM3 TIM2 TIM1 TIM0 Reset Access R/W R/W R/W R/W R/W R/W R/W Set the value that corresponds to the required division ratio - 1.
Page 347: Description Of Operation
13.4.4 Description of Operation UART Serial Interface connection Two different connection methods are possible, one for unidirectional transfer, and the other for bi-directional transfer. The SBO pin is always an output, and the SBI pin is always an input. Transmission External clock Unidirectional transfer...
Page 348: Table 13-4-2 Bit Rates (1) (When Ioclk = 15 Mhz)
Division ratio 1 = INT (IOCLK frequency / bit rate/127) + 1 Division ratio 2 = INT (IOCLK frequency / bit rate/division ratio 1 + 0.5) Subtract 1 from the value for division ratio 2 that was derived through the above equations, and write the result in SC3TIM.
Page 349: Table 13-4-3 Bit Rates (2) (When Ioclk = 12 Mhz)
Table 13-4-3 Bit Rates (2) (When IOCLK = 12 MHz) Bit rate (bit/s) Division ratio 1 230 400 115 200 56 000 38 400 19 200 9 600 4 800 2 400 1 200 Table 13-4-4 Bit Rates (3) (When IOCLK = 8 MHz) Bit rate (bit/s) Division ratio 1 230 400...
Page 350 [Notes on Usage] Set SC3CTR before setting the other registers, and do not change the setting while transmitting or receiving, or while there is data in the transmission buffer. Operation is not guaranteed if the setting of the SC3CTR register is changed.
Page 351: Fig. 13-4-3 Timing Chart (18)
UART Serial Interface timing <Transmission> • Transfer with 7-bit data length, parity off, and 2 stop bit SBO pin Data write SC3TXF flag SC3TBF flag Interrupt request (when set to “transmission end”) Interrupt request (when set to “transmission buffer empty”) •...
Page 352: Fig. 13-4-5 Timing Chart (20)
Serial Interface <Reception> • Transfer with 7-bit data length, parity on, and 2 stop bit SBI pin SC3RXF flag SC3RBF flag Interrupt request Data read • Two-byte transfer with 8-bit data length, parity off, and 1 stop bit SBI pin bp1 bp2 bp3 bp4 bp5 bp6 SC3RXF flag SC3RBF flag...
Page 353: Fig. 13-4-7 Timing Chart (22)
When a reception error is generated • Transfer with 7-bit data length, parity on, and 2 stop bit SBI pin SC3RXF flag SC3RBF flag “H” SC3OEF flag SC3PEF flag SC3FEF flag Interrupt request When "reception end" is set as the reception interrupt source, an interrupt request is generated when reception ends, regardless of whether or not an error occurred.
Page 354 Serial Interface 13-52...
Page 355: A/D Converter
A/D Converter...
Page 356: Overview
14.1 Overview The A/D converter is a 10-bit charge redistribution-type A/D converter that can process analog signals on a maximum of four channels. The A/D conversion reference clock can be selected from 1/2, 1/4, 1/8, or 1/16 of IOCLK. When IOCLK = 10 MHz, A/D conversion is performed with a maximum conversion speed of 2.8 s/ch.
Page 357: Features
14.2 Features • S/H Built in • Conversion accuracy 10 bits The value of VREFH divided into 1024 steps is stored in AD0BUF to AD3BUF. • Conversion reference clock Selectable from 1/2, 1/4, 1/8, or 1/16 of IOCLK Set this parameter so that one cycle is at least 200 ns. (Example: When IOCLK is 15 MHz, set this parameter 1/4 or 1/8 or 1/16.) •...
Page 358: Block Diagram
14.3 Block Diagram ADTRG Timer 2 underflow Divider IOCLK Fig. 14-3-1 The Block Diagram of A/D Converter 14-4 Shift registers for states A/D conversion trigger Data buffer selection For multiple- channel Comparator conversion VREFH ADnBUF Conversion Data buffer results 10 bit x 4 ch Results writing ADCTR Interrupt...
Page 359: Description Of Registers
14.4 Description of Registers Table 14-4-1 lists the registers for this A/D converter. Address Name x'34000400 A/D conversion control register x'34000410 A/D0 conversion data buffer x'34000414 A/D1 conversion data buffer x'34000418 A/D2 conversion data buffer x'3400041C A/D3 conversion data buffer A/D conversion control register Register symbol: ADCTR Address:...
Page 360 ADEN Conversion start/execution flag (conversion can be started by writing a "1" to this flag) ADSC0 Selection of conversion channel when converting any one channel/ indicator of current conversion channel when converting multiple channels (LSB) ADSC1 Selection of conversion channel when converting any one channel/ indicator of current conversion channel when converting multiple channels (MSB) —...
Page 361: Description Of Operation
14.5 Description of Operation Operating mode selection (1) Any one channel/one-time conversion If "any one channel/one-time conversion" is selected as the operating mode (ADMD1 to 0), one AN input is converted one time only. Set the conversion channel in the conversion channel selection bits (ADSC1 to 0). (ADMC1 to 0 are ignored.) An A/D interrupt request is generated simultaneously with the completion of conversion.
Page 362: Fig. 14-5-2 External Trigger Input Conversion Example
(2) Multiple channels/one-time conversion for each channel If "multiple channels/one-time conversion for each channel" is selected as the operating mode (ADMD1 to 0), a number of AN inputs, starting from AN0, are converted one time only. Set channel 0 in the conversion channel selection bits used for converting any one channel (ADSC1 to 0), and set the number of channels to be converted in the conversion channel selection bits (ADMC1 to 0).
Page 363: Fig. 14-5-3 External Trigger Input Conversion Example
(3) Any one channel/continuous conversion If "any one channel/continuous conversion" is selected as the operating mode (ADMD1 to 0), one AN input is converted continuously. Set the conversion channel in the conversion channel selection bits (ADSC1 to 0). (ADMC1 to 0 are ignored.) An A/D interrupt request is generated each time conversion is completed. When starting up conversion through software, set the conversion start trigger selection bits (ADST1 to 0) to "00", and set the conversion start/execution flag (ADEN) to "1".
Page 364: Fig. 14-5-4 External Trigger Input Conversion Example
(4) Multiple channels/continuous conversion If "multiple channels/continuous conversion" is selected as the operating mode (ADMD1 to 0), a number of AN inputs, starting from AN0, are converted continuously. Set channel 0 in the conversion channel selection bits used for converting any one channel (ADSC1 to 0), and set the number of channels to be converted in the conversion channel selection bits (ADMC1 to 0).
Page 365: Fig. 14-5-5 Conversion Timing When Using Two Sampling Cycles
Conversion reference clock selection, sampling cycle number selection The A/D conversion time is [(12 + number of sampling cycles) x IOCLK/clock selection]/channel. For example, if the conversion reference clock is set as 1/8 of IOCLK and the number of sampling cycles is set as two cycles, the A/D conversion time is IOCLK x 112 cycles/channel.
Page 366: Fig. 14-5-7 Example Of Conversion By Switching To
A/D Converter [Notes] If a falling edge is input to the ADTRG pin before the conversion start trigger selection (ADST1 to 0) is switched to "external trigger" ("01"), the ADEN flag is set at the same time that the switch is made, and A/D conversion starts.
Page 367: I/O Ports
I/O Ports...
Page 368: Overview
I/O Ports 15.1 Overview The MN103001G and MN1030F01K have a total of 13 internal I/O ports: 0 to 9, A, B and C. These ports can all be accessed by programs as internal I/O memory space. Port 0 is a 3-bit general-purpose output port; ports 1, 2, A, and B are 8-bit general-purpose input/output ports;...
Page 369 Port 7 (P7) This port is also used for address bus signal A23; DRAM RAS signals RAS2 and RAS1; and chip select signals CS3 to CS0. Port 8 (P8) This port is also used for analog signal inputs AN3 to AN0 and external interrupt inputs IRQ7 to I RQ4.
Page 370: Table 15-1-1 List Of Registers (1/2)
I/O Ports The I/O ports are provided with the registers listed in Table 15-1-1. Address x'36008000 Port 0 output register x'36008001 Port 1 output register x'36008004 Port 2 output register x'36008005 Port 3 output register x'36008008 Port 4 output register x'36008009 Port 5 output register x'3600800C...
Page 371: Table 15-1-1 List Of Registers (2/2)
Address Name x'36008081 Port 1 pin register x'36008084 Port 2 pin register x'36008085 Port 3 pin register x'36008088 Port 4 pin register x'36008089 Port 5 pin register x'3600808C Port 6 pin register x'36008090 Port 8 pin register x'36008091 Port 9 pin register x'36008094 Port A pin register x'36008095...
Page 372: Fig. 15-2-1 Port 0 Block Diagram (P02)
I/O Ports 15.2 Port 0 15.2.1 Block Diagram Fig. 15-2-1 and Fig 15-2-2 show block diagrams for port 0. Internal data bus P0OUT Control signal from BC A23 to A16 Output enable signals P0SS P0MD P02MD Fig. 15-2-1 Port 0 Block Diagram (P02) 15-6 P02O Output...
Page 373: Fig. 15-2-2 Port 0 Block Diagram (P01, P00)
Internal data bus P0OUT A21(n=1), A20(n=0) A23 to A16 Output enable signals P0MD P0nMD Fig. 15-2-2 Port 0 Block Diagram (P01, P00) 15.2.2 Register Descriptions Port 0 is a general-purpose output port that is also used for address bus A [22:20], DRAM CAS signal CAS. Each register for port 0 is described below.
Page 374 I/O Ports Port 0 output mode register Register symbol: P0MD Address: x'36008020 Purpose: This register selects the content output on the port 0 pins with P0SS. Bit No. Bit name Reset Access Port 0 dedicated output control register Register symbol: P0SS Address: x'36008040 Purpose:...
Page 375: Port 0 100
15.2.3 Pin Configurations Table 15-2-1 shows the pin configurations for port 0. Port P0nMD = "1" Port 0 100 General-purpose output port General-purpose output port General-purpose output port [Note 1] : When reset (whether in address/data separate mode or address/data multiplex mode) [Note 2] When the bus authority is granted, CAS, and A22 to A20 go to high impedance.
Page 376: Block Diagram
15.3 Port 1 15.3.1 Block Diagram Figs. 15-3-1 and 15-3-2 show block diagrams for port 1. Internal data bus P1OUT P1nO P1DIR P1nD D7 to D0 Output enable P1MD signal P1PU D7(n=7) to D2(n=2) Fig. 15-3-1 Port 1 Block Diagram (P17 to P12) 15-10 P1IN P1nI...
Page 377: Fig. 15-3-2 Port 1 Block Diagram (P11, And P10)
Internal data bus RWSEL(n=1), AS(n=0) P1OUT P1nO Control Signal from BC P1DIR P1nD D7 to D0 Output enable P1MD signal P1PU Address/data multiplex mode D1(n=1), D0(n=0) Fig. 15-3-2 Port 1 Block Diagram (P11, and P10) P1IN P1nI (n=1,0) P... Represents one bit of each register. 15-11...
Page 378: Register Descriptions
15.3.2 Register Descriptions Port 1 is a general-purpose input/output port that is also used for data bus signals D[7:0], address strobe signal AS, and read/write select RWSEL. Each register for port 1 is described below. Port 1 output register Register symbol: P1OUT Address: x'36008001 Purpose:...
Page 379 Port 1 input/output control register Register symbol: P1DIR Address: x'36008061 Purpose: This register sets the port 1 pins for input or output. (0:input; 1: output) Bit No. Bit name P17D P16D P15D P14D P13D P12D P11D P10D Reset Access R/W R/W R/W R/W R/W R/W R/W R/W Port 1 output mode register Register symbol: P1MD Address:...
Page 380: Pin Configuration
15.3.3 Pin Configurations Table 15-3-1 shows the pin configurations for port 1. Port P1nD = "1" Port 1 96 P10 General-purpose output port <<Address strobe output *Setting invalid>> <<AS>> P11 General-purpose output port <<Read/write select output *Setting invalid>> <<RWSEL>> P12 General-purpose output port P13 General-purpose output port P14 General-purpose output port P15 General-purpose output port...
Page 381: Block Diagram
15.4 Port 2 15.4.1 Block Diagram Figs. 15-4-1 shows a block diagrams for port 2. Internal data bus P2OUT P2nO P2DIR P2nD D15 to D8 output enable P2MD signal P2PU D15(n=7) to D8(n=0) Fig. 15-4-1 Port 2 Block Diagram (P27 to P20) P2IN P2nI (n=7,6,5,4,3,2,1,0)
Page 382: Register Descriptions
15.4.2 Register Descriptions Port 2 is a general-purpose input/output port that is also used for data bus signals D[15:8]. Each register for port 2 is described below. Port 2 output register Register symbol: P2OUT Address: x'36008004 Purpose: This register sets the data to be output on port 2. Bit No.
Page 383 Port 2 input/output control register Register symbol: P2DIR Address: x'36008064 Purpose: This register sets the port 2 pins for input or output. (0: input; 1: output) Bit No. Bit name P27D P26D P25D P24D P23D P22D P21D P20D Reset Access R/W R/W R/W R/W R/W R/W R/W R/W Port 2 output mode register Register symbol: P2MD...
Page 384: Pin Configuration
15.4.3 Pin Configurations Table 15-4-1 shows the pin configurations for port 2. Port P2nD = "1" Port 2 87 P20 General-purpose output port P21 General-purpose output port P22 General-purpose output port P23 General-purpose output port P24 General-purpose output port P25 General-purpose output port P26 General-purpose output port P27 General-purpose output port [Note 1]...
Page 385: Block Diagram
15.5 Port 3 15.5.1 Block Diagram Fig. 15-5-1 shows a block diagram for port 3. Internal data bus P3OUT P30O P3DIR P30D P3MD Fig. 15-5-1 Port 3 Block Diagram (P30) P3IN P30I P... Represents one bit of each register. 15-19...
Page 386: Register Descriptions
15.5.2 Register Descriptions Port 3 is a general-purpose input/output port that is also used for the bus grant signal BG. Each register for port 3 is described below. Port 3 output register Register symbol: P3OUT Address: x'36008005 Purpose: This register sets the data to be output on port 3. Bit No.
Page 387: Pin Configuration
Port 3 output mode register Register symbol: P3MD Address: x'36008025 Purpose: This register selects the content output on the port 3 pin. Bit No. Bit name Reset Access 0: Bus grant signal output (BG) 1: General-purpose input/output port (P30) Note: When BG is selected in the P3MD register, this control signal is output regardless of the value in the P3DIR register.
Page 388: Block Diagram
15.6 Port 4 15.6.1 Block Diagram Figs. 15-6-1 to 15-6-4 show block diagrams for port 4. Internal data bus P4OUT DWE(n=5), DCAS0(n=3) SBO1(n=5), SBT1(n=3) P4DIR Control signal from SBO1 output enable (n=5), SBT1 output enable (n=3) P4SS P4MD SBO1(n=5), SBT1(n=3) Fig.
Page 389: Fig. 15-6-2 Port 4 Block Diagram (P44)
Internal data bus P4OUT P44O DCAS1 P4DIR P44D Control signal from P4SS P44S P4MD P44M SBI1 P4IN P44I Fig. 15-6-2 Port 4 Block Diagram (P44) P... Represents one bit of each register. 15-23...
Page 390: Fig. 15-6-3 Port 4 Block Diagram (P42, P40)
Internal data bus P4OUT SBO0(n=2), SBT0(n=0) P4DIR SBO0 output enable(n=2), SBT0 output enable (n=0) P4MD SBO0(n=2), SBT0(n=0) Fig. 15-6-3 Port 4 Block Diagram (P42, P40) Internal data bus P4OUT P4DIR P4MD SBI0 Fig. 15-6-4 Port 4 Block Diagram (P41) 15-24 P4nO P4nD P4nM...
Page 391: Register Descriptions
15.6.2 Register Descriptions Port 4 is a general-purpose input/output port that is also used for serial interface input/output signals SBI1, SBO1, SBT1, SBI0, SBO0, and SBT0; the DRAM CAS signals (for 2CAS) DCAS1 and DCAS0; and the DRAM write signal (for 2CAS) DWE. Each register for port 4 is described below.
Page 392 Port 4 input/output control register Register symbol: P4DIR Address: x'36008068 Purpose: This register sets the port 4 pins for input or output. (0: input; 1: output) Bit No. Bit name P45D P44D P43D P42D P41D P40D Reset Access R/W R/W R/W R/W R/W R/W Port 4 output mode register Register symbol: P4MD Address:...
Page 393 Port 4 dedicated output control register Register symbol: P4SS Address: x'36008048 Purpose: Along with P4MD, this register selects the content output on the port 4 pins. Bit No. Bit name P45S P44S P43S Reset Access R/W R/W R/W P45M; P45S 00: Serial 1 data input/output (SBO1) * The input/output setting is made through the serial interface 1 settings.
Page 394: Pin Configurations
15.6.3 Pin Configurations Table 15-6-1 shows the pin configurations for port 4. Port Pin P4n P4nM = "1" P4nD = "1" Port 4 75 P40 General-purpose General-purpose output port input port P41 General-purpose General-purpose output port input port P42 General-purpose General-purpose output port input port...
Page 395: Block Diagram
15.7 Port 5 15.7.1 Block Diagram Figs. 15-7-1 to 15-7-5 show block diagrams for port 5. Internal data bus P5OUT TM13IO TM5IO SBO3 P5DIR P5SS P5MD TM13IO/TM5IO Fig. 15-7-1 Port 5 Block Diagram (P55) P55O P55D P55S P55M P5IN P55I I/O Ports P...
Page 396: Fig. 15-7-2 Port 5 Block Diagram (P54)
I/O Ports Internal data bus P5OUT TM12IO TM4IO P5DIR P5SS P5MD TM12IO/TM4IO/SBI3 Fig. 15-7-2 Port 5 Block Diagram (P54) 15-30 P54O P54D P54S P54M P5IN P54I P... Represents one bit of each register.
Page 397: Fig. 15-7-3 Port 5 Block Diagram (P53)
Internal data bus P5OUT P53O TM11IO TM3IO P5DIR P53D P5SS P53S P5MD P53M TM11IO/TM3IO/SBT3 Fig. 15-7-3 Port 5 Block Diagram (P53) P5IN P53I P... I/O Ports Represents one bit of each register. 15-31...
Page 398: Fig. 15-7-4 Port 5 Block Diagram (P52, P50)
I/O Ports Internal data bus P5OUT TM2IO(n=2), TM0IO(n=0) SBO2(n=2), SBT2(n=0) P5DIR SBO2 output enable (n=2), SBT2 output enable (n=0) P5SS P5MD TM2IO/SBO2(n=2), TM0IO/SBT2(n=0) Fig. 15-7-4 Port 5 Block Diagram (P52, P50) 15-32 P5nO P5nD P5nS P5nM P5IN P5nI (n=2,0) P... Represents one bit of each register.
Page 399: Fig. 15-7-5 Port 5 Block Diagram (P51)
Internal data bus P5OUT P51O TM1IO P5DIR P51D P5SS P51S P5MD P51M TM1IO/SBI2 P5IN P51I Fig. 15-7-5 Port 5 Block Diagram (P51) P... Represents one bit of each register. I/O Ports 15-33...
Page 400: Register Descriptions
I/O Ports 15.7.2 Register Descriptions Port 5 is a general-purpose input/output port that is also used for the serial interface input/output signals SBI3, SBO3, SBT3, SBI2, SBO2, SBT2; and the timer input/output signals TM13IO, TM12IO, TM11IO, TM5IO, TM4IO, TM3IO, TM2IO, TM1IO, and TM0IO. Each register for port 5 is described below.
Page 401 Port 5 input/output control register Register symbol: P5DIR Address: x'36008069 Purpose: This register sets the port 5 pins for input or output. (0: input; 1: output) Bit No. Bit name P55D P54D P53D P52D P51D P50D Reset Access R/W R/W R/W R/W R/W R/W Port 5 output mode register Register symbol: P5MD Address:...
Page 402 Port 5 dedicated output control register Register symbol: P5SS Address: x'36008049 Purpose: Along with P5MD, this register selects the content output on the port 5 pins. Bit No. Bit name P55S P54S P53S P52S P51S P50S Reset Access R/W R/W R/W R/W R/W R/W P55M;...
Page 403: Pin Configurations
15.7.3 Pin Configurations Table 15-7-1 shows the pin configurations for port 5. Port P5nS = "1" P5nD = "1" P5nD = "0" Port 5 P50 General- General- purpose purpose output port input port P51 General- General- purpose purpose output port input port P52 General- General- purpose...
Page 404: Port 5
15.8 Port 6 15.8.1 Block Diagram Figs. 15-8-1 shows the block diagrams for port 6. Internal data bus TM10IOB(n=3), TM10IOA(n=2), TM7IO(n=1), TM6IO(n=0) ADTRG/IRQ3/TM10IOB(n=3), IRQ2/TM10IOA(n=2), IRQ1/TM7IO(n=1), IRQ0/TM6IO(n=0) Fig. 15-8-1 Port 6 Block Diagram (P63 to P60) 15-38 P6OUT P6nO P6DIR P6nD P6MD P6nM P6IN...
Page 405: Register Descriptions
15.8.2 Register Descriptions Port 6 is a general-purpose input/output port that is also used for external interrupt inputs IRQ3 to IRQ0; the timer input/output signals TM6IO, TM7IO, TM10IOA, TM10IOB; and the A/D conversion trigger input ADTRG. Each register for port 6 is described below. Port 6 output register Register symbol: P6OUT Address:...
Page 406: Pin Configurations
Port 6 output mode register Register symbol: P6MD Address: x'3600802C Purpose: This register selects the content output on the port 6 pins. Bit No. Bit name Reset Access When P6nM is "0", the timer input/output signal is selected. The input/output setting for the timer input/output signal is also changed by P6nD.
Page 407: Port 6
15.9 Port 7 15.9.1 Block Diagram Fig. 15-9-1 and Fig. 15-9-2 show block diagrams for port 7. Internal data bus P7OUT P73O P7SS P73S Control signal from P7MD P73M Fig. 15-9-1 Port 7 Block Diagram (P73) Internal data bus P7OUT P7nO CS2/RAS2(n=2), CS1/RAS1(n=1),...
Page 408: Register Descriptions
15.9.2 Register Descriptions Port 7 is a general-purpose output port that is also used for address bus signal A23, DRAM RAS signals RAS2 and RAS1, chip select signals CS3 to CS0. Each register for port 7 is described below. Port 7 output register Register symbol: P7OUT Address: x'3600800D...
Page 409 Port 7 dedicated output control register Register symbol: P7SS Address: x'3600804D Purpose: This register selects the content output on the port 7 pins. Valid when the P7nM is “0”. Bit No. Bit name Reset Access P73M; P73S 00: Chip select signal 3 output (CS3) 01: Address output (A23) 1x: General-purpose output port (P73) P72M...
Page 410: Pin Configurations
15.9.3 Pin Configurations Table 15-9-1 shows the pin configurations for port 7. Port Pin P7n P7nM = "1" Port 7 55 P70 General-purpose output port 53 P71 General-purpose output port 52 P72 General-purpose output port 51 P73 General-purpose output port [Note 1] : When reset (whether in address/data separate mode or address/data multiplex mode) : If block 1 in the external memory space is not used as a DRAM space, CS1 is selected;...
Page 411: Port 7
15.10 Port 8 15.10.1 Block Diagram Figs. 15-10-1 shows the block diagrams for port 8. Internal data bus AN3(n=3) to AN0(n=0) P8AD P8nA IRQ7(n=3) to IRQ4(n=0) Fig. 15-10-1 Port 8 Block Diagram (P83 to P80) P8IN P8nI P... (n=3,2,1,0) Represents one bit of each register. 15-45...
Page 412: Register Descriptions
15.10.2 Register Descriptions Port 8 is a general-purpose input port that is also used for analog signal inputs AN3 to AN0 and external interrupt inputs IRQ7 to IRQ4. Each register for port 8 is described below. Port 8 analog/digital input control register Register symbol: P8AD Address: x'36008030...
Page 413: Pin Configurations
15.10.3 Pin Configurations Table 15-10-1 shows the pin configurations for port 8. Port Pin No. Port 8 General-purpose input port General-purpose input port General-purpose input port General-purpose input port [Note 1] : When reset (whether in address/data separate mode or address/data multiplex mode) [Note 2] When pin Nos.
Page 414: Block Diagram
15.11 Port 9 15.11.1 Block Diagram Fig. 15-11-1 to Fig. 15-11-4 show block diagrams for port 9. Internal data bus P9OUT P97O SYSCLK P9MD P97M Fig. 15-11-1 Port 9 Block Diagram (P97) Internal data bus P9OUT P9DIR P9MD Fig. 15-11-2 Port 9 Block Diagram (P96) 15-48 P96O P96D...
Page 415: Fig. 15-11-3 Port 9 Block Diagram (P95, P91, P90)
Internal data bus P9OUT P9nO P9DIR P9nD P9MD P9nM DK (n=5), EXMOD1 (n=1), EXMOD0 (n=0) Fig. 15-11-3 Port 9 Block Diagram (P95, P91, P90) Internal data bus P9OUT P9nO WE1(n=4), WE0(n=3), P9MD RE(n=2) P9nM Control signal from BC Fig. 15-11-4 Port 9 Block Diagram (P94, P93, P92) P9IN P9nI P...
Page 416: Register Descriptions
15.11.2 Register Descriptions Port 9 is also used for extension mode setting signals EXMOD1 and EXMOD0; memory write signals WE1 and WE0; memory read signal RE; bus authority request signal BR; data acknowledge signal DK; and system clock SYSCLK. P96, P95, P91, and P90 are general-purpose input/output ports, and P97 and P94 to P92 are general- purpose output ports.
Page 417 Port 9 output mode register Register symbol: P9MD Address: x'36008031 Purpose: This register selects the content output on the port 9 pins. Bit No. Bit name P97M P96M P95M P94M P93M P92M P91M P90M Reset Access R/W R/W R/W R/W R/W R/W R/W R/W P97M 0: System clock output (SYSCLK) 1: General-purpose output port (P97)
Page 418: Port 9
15.11.3 Pin Configurations Table 15-11-1 shows the pin configurations for port 9. Port P9nD = "1" Port 9 P90 General-purpose output port General-purpose input port EXMOD0 Extension mode setting input 0 P91 General-purpose output port General-purpose input port EXMOD1 Extension mode setting input 1 P92 General-purpose output port P93 General-purpose output port P94 General-purpose output port...
Page 419: Block Diagram
15.12 Port A 15.12.1 Block Diagram Fig. 15-12-1 shows a block diagram for port A. Internal data bus PAOUT PAnO PADIR PAnD A7 to A0 Output enable PAMD signal PAPU A7(n=7) to A0(n=0) ADM7(n=7) to ADM0(n=0) Fig. 15-12-1 Port A Block Diagram (PA7 to PA0) PAIN PAnI (n=7,6,5,4,3,2,1,0)
Page 420: Register Descriptions
15.12.2 Register Descriptions Port A is a general-purpose input/output port that is also used for address bus signals A[7:0], and address/ data signals ADM[7:0]. Each register for port A is described below. Port A output register Register symbol: PAOUT Address: x'36008014 Purpose: This register sets the data to be output on port A.
Page 421 Port A input/output control register Register symbol: PADIR Address: x'36008074 Purpose: This register sets the port A pins for input or output. Valid when the PAM is "1". (0: input; 1: output) Bit No. Bit name PA7D PA6D PA5D PA4D PA3D PA2D PA1D PA0D Reset Access R/W R/W R/W R/W R/W R/W R/W R/W...
Page 422: Pin Configurations
15.12.3 Pin Configurations Table 15-12-1 shows the pin configurations for port A. Port PAnD = "1" Port A 24 PA0 General-purpose output port PA1 General-purpose output port PA2 General-purpose output port PA3 General-purpose output port PA4 General-purpose output port PA5 General-purpose output port PA6 General-purpose output port...
Page 423: Block Diagram
15.13 Port B 15.13.1 Block Diagram Fig. 15-13-1 shows a block diagram for port B. Internal data bus PBOUT PBnO PBDIR PBnD A15 to A8 output enable PBMD signal PBPU A15 (n=7) to A8 (n=0) ADM15 (n=7) to ADM8 (n=0) Fig.
Page 424 15.13.2 Register Descriptions Port B is a general-purpose input/output port that is also used for address bus signals A[15:8], and address/ data signals ADM[15:8]. Each register for port B is described below. Port B output register Register symbol: PBOUT Address: x'36008015 Purpose: This register sets the data to be output on port B.
Page 425 Port B input/output control register Register symbol: PBDIR Address: x'36008075 Purpose: This register sets the port B pins for input or output. Valid when PBM is "1". (0: input; 1: output) Bit No. Bit name PB7D PB6D PB5D PB4D PB3D PB2D PB1D PB0D Reset Access R/W R/W R/W R/W R/W R/W R/W R/W...
Page 426: Port B 14
15.13.3 Pin Configurations Table 15-13-1 shows the pin configurations for port B. Port PBnD = "1" Port B 14 PB0 General-purpose output port PB1 General-purpose output port PB2 General-purpose output port PB3 General-purpose output port PB4 General-purpose output port PB5 General-purpose output port PB6 General-purpose output port...
Page 427: Port C
15.14 Port C 15.14.1 Block Diagram Fig. 15-14-1 shows a block diagram for port C. Internal data bus PCOUT PCnO A19 (n=3) to A16(n=0) A23 to A16 Output enable signal PCMD PCnM Fig. 15-14-1 Port C Block Diagram (PC3 to PC0) P...
Page 428: Register Descriptions
15.14.2 Register Descriptions Port C is a general-purpose output port that is also used for address bus signals A[19:16]. Each register for port C is described below. Port C output register Register symbol: PCOUT Address: x'36008018 Purpose: This register sets the data to be output on port C. Bit No.
Page 429: Table 15-14-1Port C Configuration
15.14.3 Pin Configurations Table 15-14-1 shows the pin configurations for port C. Port Pin No. PCn Port C General-purpose output port General-purpose output port General-purpose output port General-purpose output port [Note 1] : When reset (whether in address/data separate mode or address/data multiplex mode) [Note 2] When the bus authority is granted, A19 to A16 go to high impedance.
Page 430: Treatment Of Unused Pins
I/O Ports 15.15 Treatment of Unused Pins Unused pins should be treated as shown in Table 15-15-1 below. Table 15-15-1 Treatment of Unused Pins Pin name PC3/A19, PC2/A18, PC1/A17, PC0/A16 PB7/ADM15/A15, PB6/ADM14/A14, PB5/ADM13/A13, PB4/ADM12/A12, PB3/ADM11/A11, PB2/ADM10/A10, PB1/ADM9/A9, PB0/ADM8/A8, PA7/ADM7/A7, PA6/ADM6/A6, PA5/ADM5/A5, PA4/ADM4/A4, PA3/ADM3/A3, PA2/ADM2/A2, PA1/ADM1/A1, PA0/ADM0/A0 OSCO...
Page 431: Internal Flash Memory
Internal Flash Memory...
Page 432: Overview
16.1 Overview The MN1030F01K has 256 KB of internal flash memory for use as instruction memory in place of instruction ROM. Using flash memory makes it easy to make changes to a stored program, which makes it possible to reduce program development time and permits the creation of a highly flexible system.
Page 433: Flash Memory Overwrite Mode And Settings
16.4 Flash Memory Overwrite Mode and Settings There are two flash memory overwrite modes: flash memory mode and on-board write mode. Table 16-4-1 lists the mode settings through the external pins. Flash memory mode is used to overwrite the internal flash memory with a ROM writer. In this mode, the flash memory inputs and outputs are connected to external pins.
Page 434: Description Of External Pins
16.5 Flash Memory Mode 16.5.1 Description of External Pins Fig. 16-5-1 and Table 16-5-1 show the pin assignments for the MN1030F01K in flash memory mode. NROMRST PD15 PD14 PD13 PD12 PD11 PD10 TEST3 TEST2 Fig. 16-5-1 MN1030F01K Pin Assignments in Flash Memory Mode 16-4 TOP VIEW 100 Pin QFP...
Page 435: Table 16-5-1 Mn1030F01K Pin Assignments
Table 16-5-1 MN1030F01K Pin Assignments Pin Name 1 TEST1 26 PVSS 2 TEST0 27 PVDD 3 VDD 28 MMOD1 4 PA17 29 MMOD0 5 PA16 30 RST 6 PA15 31 — 7 PA14 32 — 8 PA13 33 VDD 9 VSS 34 —...
Page 436: Table 16-5-2 Pin Functions
Table 16-5-2 lists the functions of the external pins in flash memory mode. Table 16-5-2 Pin Functions Pin Name Input/Output PA[17:1] Input PD[15:0] Input/Output Input Input MODE Input Input Input Input FROM Input TEST[3:0] Input NROMRST When first applying power, it is necessary to input a signal that is low for at least 1 ms to the reset pin NROMRST. 16-6 Description Address...
Page 437: Erasure Blocks
16.5.2 Erasure Blocks The flash memory is partitioned into 32 8 KB erasure blocks. Fig. 16-5-2 shows the configuration of the flash memory erasure blocks and their correspondence with each of the bits in the erasure block registers that are used to specify which blocks to erase.
Page 438: On-Board Write Mode
16.6 On-board Write Mode In on-board write mode, flash memory is overwritten by manipulating the control registers through software. Table 16-6-1 lists the control registers to be used in on-board write mode. Table 16-6-1 Flash Memory Register List Address Registername Flash on-board rewrite control register x'34010000 Flash data register...
Page 439: Ordering Mask Rom
Ordering Mask ROM...
Page 440: Overview
17.1 Overview This chapter describes the procedure for ordering mask ROM. This chapter also describes the difference in programming when using a product that has on-chip flash memory versus a mask product, and explains how to order ROM, etc. 17.2 Procedure for Ordering ROM When program development with a product that has on-chip flash memory has been conducted using a flash overwrite program (loader program), process the flash memory program by either of the following methods when ordering the mask ROM product.
Page 441 Program in flash memory x'40000000 Loader program 8 KB x'40002000 User program x'40000000 x'40000008 x'40002000 (When the user program starts in x'40002000 and the non-maskable interrupt processing routine starts in x'40002008) Fig. 17-2-2 ROM Ordering Method 2 Program in mask ROM JMP x'40002000 JMP x'40002008 8 KB...
Page 442 Ordering Mask ROM 17-4...
Page 443: Appendix
Appendix...
Page 444: Register Map List
Appendix Appendix A. Register Map List Appendix-2...
Page 445 Appendix Appendix-3...
Page 446 Appendix Appendix-4...
Page 447: Instruction Set
Appendix B. Instruction Set List of Instructions ( Code Length, Execution Cycle*) Instruction Source (Am) (d8,Am) (d16,Am) (d32,Am) (d8,SP) (d16,SP) (d32,SP) (Di,Am) (abs16) (abs32) (Am) (d8,Am) (d16,Am) (d32,Am) (d8,SP) (d16,SP) (d32,SP) (Di,Am) (abs16) (abs32) (d8,Am) (An) (d8,An) (d16,An) (d32,An) (d8,SP) (d16,SP) (d32,SP) (Di,An)
Page 448 Appendix Instruction Source MOVBU MOVBU (Am) MOVBU (d8,Am) MOVBU (d16,Am) MOVBU (d32,Am) MOVBU (d8,SP) MOVBU (d16,SP) MOVBU (d32,SP) MOVBU (Di,Am) MOVBU (abs16) MOVBU (abs32) MOVBU (An) MOVBU (d8,An) MOVBU (d16,An) MOVBU (d32,An) MOVBU (d8,SP) MOVBU (d16,SP) MOVBU (d32,SP) MOVBU (Di,An) MOVBU (abs16) MOVBU...
Page 449 Instruction Source Destination MOVM imm8 imm16 imm32 imm8 imm16 imm32 imm8 imm16 imm32 ADDC ADDC imm32 imm32 SUBC SUBC MULU MULU DIVU DIVU INC4 INC4 imm8 imm16 imm32 imm8 imm16 imm32 Code length Execution Cycle Format Registers specified by regs = 4 Registers specified by regs = 7 Registers specified by regs = 8 Registers specified by regs = 9...
Page 450 Instruction Source imm8 imm16 imm32 imm16 imm8 imm16 imm32 imm16 imm16 imm32 BTST BTST imm8 BTST imm16 BTST imm32 BTST imm8 (d8,An) BTST imm8 (abs32) BSET BSET (An) BSET imm8 (d8,An) BSET imm8 (abs32) BCLR BCLR (An) BCLR imm8 (d8,An) BCLR imm8 (abs32)
Page 451 Instruction Source Destination SETLB SETLB (An) (d16,PC) (d32,PC) CALL CALL (d16,PC) regs,imm8 CALL CALL (d32,PC) regs,imm8 CALLS CALLS (An) CALLS (d16,PC) CALLS (d32,PC) regs,imm8 RETF RETF regs,imm8 RETS RETS TRAP TRAP UDF20~35 UDF00~15 UDF00~15 imm8 UDF00~15 imm16 UDF00~15 imm32 UDFU00~15 imm8 UDFU00~15 imm16...
Page 452 List of Extension Instructions ( Code Length, Execution Cycle) Instruction Source Destination Format Code length Execution cycle PUTX PUTX PUTCX GETX GETX GETCHX GETCLX CLRMAC CLRMAC MULQ MULQ MULQI imm8 MULQI imm16 MULQI imm32 MULQU MULQU MULQIU imm8 MULQIU imm16 MULQIU imm32 MACH...
Page 453: Memory Connection Example
Appendix C. Memory Connection Example Fig. C-1 shows a connection example for the memory configuration described below. Block 0: 16-bit bus, 4-Mbit ROM (262 144 words x 16 bits) Block 1: 16-bit bus, 4-Mbit DRAM (262 144 words x 16 bits, 2 CAS control) Block 2: 8-bit bus, 1-Mbit SRAM (131 072 words x 8 bits) Fig.
Page 454: Pins And Their Operating Statuses Upon Reset
Appendix Appendix D. Pins and Their Operating Statuses upon Reset In the address/data separate mode Pin name Pin name Operating status 1 A19 26 PVSS 2 A18 27 PVDD 3 VDD — 28 MMOD1 4 A17 29 MMOD0 5 A16 30 RST 6 A15 31 OSCO...
Page 455 In the address/data multiplex mode Operating Pin name Pin name status 1 A19 26 PVSS 2 A18 27 PVDD 3 VDD — 28 MMOD1 4 A17 29 MMOD0 5 A16 30 RST 6 ADM15 Pull-Up 31 OSCO 7 ADM14 Pull-Up 32 OSCI 8 ADM13 Pull-Up...
Page 456: Package Outline
Appendix Appendix E. Package Outline The package outline and dimensions of this microcontroller are shown below. Package code : LQFP100-P-1414 Unit: mm ± 16.00 0.20 ± 14.00 0.10 Fig. E-1 Package Outline Appendix-14...
Page 457 The correction table in The Revised Edition of MN103001G/F01K LSI User's Manual (From 2nd Edition (or 2nd Edition 1st printing) to 5th Edition) Errors Page - External interrupts: 9 sources (8 individual IRQs, and 1 external NMI) P.1-3 P.1-8 (The column of "Pin Function" such as "Pin name" is "NMIRQ" in the table.) External NMI input P.2-9...
Page 458 Errors Page P.3-8 P.3-9 P.3-10 P.3-21 P.3-22 [Instruction Format (Macro Name)] P.3-23 MCST32, MCST16, MCST8 P.3-23 (From 2nd line of [Operation]) In addition, depending on the value of Dm, ... (1) When the value of Dm is 32 (0x00000020) (2) When the value of Dm is 16 (0x00000010) (3) When the value of Dm is 8 (0x00000008) (4) When the value of Dm is any other value P.3-24...
Page 459 Errors Page P.3-30 P.3-31 (Omit) P.4-4 Note that operation is not assured when attempting to access unmounted space. P.4-5 Note that operation is not assured when attempting to access unmounted space. P.5-4 (The 2nd line of " Operation of various peripheral functions in the low power consumption modes".) In SLEEP mode, all peripheral functions operate except for the bus controller.
Page 460 Errors Page P.6-3 Input frequency range 8 fosci 15 MHz 8 fosci 30 MHz P.6-3 When the reset state is released, SYSCLK, MCLK, and IOCLK are supplied starting after a certain oscillation stabilization wait time. Note: • When a clock is supplied from external, input the clock to the OSCI pin, and leave the OSCO pin open.
Page 461 Errors Page P.8-42 P.8-43 P.8-44 P.8-48 P.8-49 P.8-49 P.8-50 P.8-56 P.8-57 P.8-58 P.8-59 Corrections Page ____ P.8-42 (In figure 8-13-13 (a) and (b), the DK signal asserted by the low- order side access was changed so as to be negated before the high- order side access.) P.8-43 (In figure 8-13-14 (a), (b) and figure 8-13-15 (a), (b), the DK signal...
Page 462 Errors Page P.9-3 (In fig. 9-4-1.) P.9-7 (Register's purpose) This register determines whether an NMI interrupt has been generated. P.9-7 Bit name Description NMIF External NMI request flag P.9-7 (From 1st line of main sentence) Each flag is set if the corresponding NMI interrupt request is generated.
Page 463 Errors Page P.12-5 (In the table of Example.) Overflow cycle When CKSEL is "H" and oscillation frequency is 15 MHz (or when CKSEL is "L" and oscillating frequency is 30 MHz) P.12-7 (The 2nd line from the bottom.) An oscillation stabilization wait time of at least 17ms is recommended.
Page 464 Errors Page Warning The MN1030F01K is manufactured and marketed under a licensing agreement with Bull CP8 Corporation. Note that the MN1030F01K cannot be used on IC cards. Warning If you have any inquiries or questions about this book or our semiconductors, please contact one of our sales offices listed at the back of this book or Matsushita Electronics Corporation's Sales Department.
Page 465 MN103001G/F01K LSI User's Manual February, 2002 5th Edition Issued by Matsushita Electric Industrial Co., Ltd. © Matsushita Electric Industrial Co., Ltd.
Page 466 Semiconductor Company, Matsushita Electric Industrial Co., Ltd. NORTH AMERICA U.S.A. Sales Office: Panasonic Industrial Company New Jersey Office: Two Panasonic Way Secaucus, New Jersey 07094 U.S.A. Tel: 1-201-348-5257 Fax:1-201-392-4652 Chicago Office: 1707 N. Randall Road Elgin, Illinois 60123-7847 U.S.A. Tel: 1-847-468-5720...

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