9. PT6324
• FUNCTIONAL BLOCK DIAGRAM
OTW
Internal Pullup
Resistors to VREG
SD
M1
M2
M3
RESET_AB
RESET_CD
PWM
PWM_D
Rcv.
PWM
PWM_C
Rcv.
PWM
PWM_B
Rcv.
PWM
PWM_A
Rcv.
Copyright © 2008 LG Electronics. Inc. All right reserved.
Only for training and service purposes
Under-
voltage
Protection
Power
On
Reset
Protection
and
I/O Logic
Temp.
Sense
Overload
Protection
Gate
Ctrl.
Timing
Drive
Gate
Ctrl.
Timing
Drive
Gate
Ctrl.
Timing
Drive
Gate
Ctrl.
Timing
Drive
3-19
4
4
VREG
I
sense
BTL/PBTLConfiguration
Pulldown Resistor
BTL/PBTLConfiguration
Pulldown Resistor
BTL/PBTLConfiguration
Pulldown Resistor
BTL/PBTLConfiguration
Pulldown Resistor
VDD
VREG
AGND
GND
OC_ADJ
GVDD_D
BST_D
PVDD_D
OUT_D
GND_D
GVDD_C
BST_C
PVDD_C
OUT_C
GND_C
GVDD_B
BST_B
PVDD_B
OUT_B
GND_B
GVDD_A
BST_A
PVDD_A
OUT_A
GND_A
B0034-03
LGE Internal Use Only