Yamaha MCX-1000 Service Manual page 52

MCX-1000
IC501 : LAN91C111 (MAIN P.C.B.)
Ethernet
Pin No.
Name
TQFP
104-107, Data Bus
99-102,
73-76,
68-71,
63-66,
58-61,
53-56,
48-51
30 Reset
37 nAddress Strobe nADS
35 nCycle
36 Write/nREAD
40 NVLBus Access
42 Local Bus Clock
38 Asynchronous
Ready
43 nSynchronous
Ready
46 nReady Return
52
Buffer
Symbol
Type
D0-D31 I/O24** Bidirectional signal. 32-bit data bus that is used to access the
internal register of LAN91C111. The data bus has a weak internal
pullup register. It is usable for direct connection with the system bus
without external buffering. For the 16-bit system, only D0 to D15 are
used.
RESET IS** Input signal. When this pin is in the high state, the controller
executes resetting of the internal system (MAC and PHY). When this
pin is in the high state, all registers are set to the default value and
the controller reads the contents of the EEPROM device through the
EEPROM interface (1). This input is not considered effective unless
it is active for at least 100ns for filtering of glitches.
IS** Input signal. With the system that requires address latching, the
rising edge of nADS indicates the time of A1, A15 and AEN latching.
The internal functions of all LAN91C111 of A1, A15 and AEN are
latched if there is no n LDEV decoding.
nCYCLE I** Input signal. This active low signal is used to control the LAN91C111
EISA burst mode synchronous bus cycle.
W/nR IS** Input signal. Used to determine the direction of the synchronous
cycle. When it is in the high state, the writing cycle is selected and
when it is low, the reading cycle is selected.
nVLBUS I with Input signal. When it is in the low state, LAN91C111 synchronous
pullup** bus interface is set for VL bus accessing. If not, LAN91C111is set for
EISA DMA burst accessing. It does not affect the asynchronous bus
interface.
LCLK I** Input signal. Used to interface the synchronous bus. The maximum
frequency is 50MHz. For the EISA DMA burst mode, the maximum
value is 8.33MHz.
ARDY OD16 Open drain output signal. ARDY is usable for interfacing the
asynchronous bus to expand accessing. Its rising (completion of
accessing) edge is controlled by XTA 1 clock and so asynchronous
with the host CPU, that is, bus clock.
nSRDY O16 Output signal. This output is used for interfacing the synchronous
bus at n VLBUS=0 to expand accessing. This signal is usually
inactive and its falling edge indicates completion. This signal is
synchronous with the bus clock LCLK.
nRDYRTN I** Input signal. This input is used to complete the synchronous reading
cycle. In the EISA burst mode, it is picked up at the falling edge and
the synchronous cycle continues until the EISA burst mode is
adopted in the high state.
Function