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-9-
a.
F/F reset pulse width: 1msec
NOTE: At power on, the flipflop will be
reset
with a
pulse from the C-R
network.
A low state of the
flipflop output performs all clear
operation.
A
power on reset output is sent out at the
begin-
ning of the all
clear
operation to reset the
flipflop.
Pulse added to the RST pin thereafter
will not be assumed as the
all
clear
signal.
(5)
Al
I
clear operation ( F ig.1)
1.
Pulse is added to
Q)
in order to perform the same
action as at
power
on.
2. Pulse is added to
(8)
for
a wake up by releasing the
halt condition.
3.
Hardware is reset by adding a pulse
to
the RST
terminal (G).
With the
above operation,
it insured all clear
opera-
tion even if there was an error in the program due to
noise.
1!9
POWER ON TEST
IQ
POWER ON RESET
~
Jf-------------
L_Power on
_jt_®
---
Q)
Reset
Power on reset timing (Fig.1)
(4)
-
PC-2500
NOTE-1:
Once it goes into the halt
state,
arrival of a
wake up pulse will be disregard in this period.
NOTE-2:
"IOms. TYP" is dependent on the factor of the
C-R
network.
Condition required for the LSI to
operate normally is
4msec,
minimum.
NOTE-3:
A wait time until it goes into the halt state after
completion of data processing, with no more
data to
receive.
@
Wake up disregard period
(NOTE-1) 20msec
@
Halt reset
-»
start of operation
(NOTE-2) 10msec
©
Halt wait period
(NOTE-3) 120msec
Th is wake up is
disregarded.
NOTE: The on/off state of
the
PF switch is checked once
in a
busy
period
(3msec).
(3)
Halt control signal timing (Fig.1)
Busy period
3msec
3msec
Ready period
®
Read timing
----i__s-
'-----1----1~
Paper feed
period
©PAPER
FEED
@BUSY
(2)
PF switch sense timing (Fig.1)
®
One data
length
8.33msec
@
One bit length
833 µsec
©
Start bit
rising edqe
-»
11 Oµsec
busy
signal
rising edge
®
OJ
''°':''''td
@BUSY~
I__
©
"O" level
®
•m.c
""'
~
1
°
1
•
l
•
l
•
l
•
[
•
[
• i
I
@
"1"
level
Start
bi t
8-bit serial
print data
are
received
from
the CPU to be
printed.
(1)
Serial interface timing (Fig.1.)
-
5.
DESCRIPTION OF THE PRINTER
CONTROL CIRCUIT
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