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MPEG4-2 CIRCUIT DIAGRAM
1.8V
IC301
MT8520
H21
VCC18I0
ADQ0
H23
VCC18I0
ADQ1
J22
ADQ2
VCC18I0
J24
VCC18I0
ADQ3
P21
VCC18I0
ADQ4
P23
VCC18I0
ADQ5
R22
VCC18I0
ADQ6
R24
VCC18I0
ADQ7
Y21
ADQ8
VCC18I0
Y23
VCC18I0
ADQ9
AA8
VCC18I0
ADQ10
AA14
VCC18I0
ADQ11
AA20
VCC18I0
ADQ12
AA22
VCC18I0
ADQ13
AA24
ADQ14
VCC18I0
AB9
VCC18I0
ADQ15
AB15
VCC18I0
ADQ16
AB21
VCC18I0
ADQ17
AB23
VCC18I0
ADQ18
AC8
VCC18I0
ADQ19
AC14
VCC18I0
ADQ20
AC20
VCC18I0
ADQ21
AC22
VCC18I0
ADQ22
AC24
VCC18I0
ADQ23
AD9
VCC18I0
ADQ24
AD15
VCC18I0
ADQ25
AD21
VCC18I0
ADQ26
AD23
VCC18I0
ADQ27
AD25
VCC18I0
ADQ28
AE24
VCC18I0
ADQ29
AE25
VCC18I0
ADQ30
AE26
VCC18I0
ADQ31
AF25
VCC18I0
ADQM0
ADQM1
ADQM2
ADQM3
ADQS0
ADQSB0
ADQS1
ADQSB1
ADQS2
ADQSB2
ADQS3
ADQSB3
ABA0
ABA1
ABA2
ARAS#
ACAS#
ACKE
ARCS#
ARWE#
ARA0
ARA1
ARA2
ARA3
ARA4
ARA5
ARA6
ARA7
ARA8
ARA9
ARA10
ARA11
ARA12
DDR2_VREF
ARA13
AA16
VDD_ARVREF
AB16
VDD_ARVREF
ARCLK
1.8V
R601
75(1%)
AF24
REXTUP
ARCLKB
AD26
GND
REXTDN
R602
75(1%)
ARCLK1
GND
ARCLKB1
A0DT
;3:B4
DDR2_A_DQ[0-31]
1.8V
AC7
DDR2_A_DQ[0]
AB8
DDR2_A_DQ[1]
AD7
DDR2_A_DQ[2]
AB7
DDR2_A_DQ[3]
AA7
DDR2_A_DQ[4]
AA9
DDR2_A_DQ[5]
Y8
DDR2_A_DQ[6]
GND
AE6
DDR2_A_DQ[7]
AF10
DDR2_A_DQ[8]
AB11
DDR2_A_DQ[9]
AA10
DDR2_A_DQ[10]
AE9
DDR2_A_DQ[11]
AD8
DDR2_A_DQ[12]
AE10
DDR2_A_DQ[13]
AC10
DDR2_A_DQ[14]
AD10
DDR2_A_DQ[15]
AE17
DDR2_A_DQ[16]
AE18
DDR2_A_DQ[17]
AC18
DDR2_A_DQ[18]
AF17
DDR2_A_DQ[19]
DDR2_0V9
AB17
DDR2_A_DQ[20]
AA18
DDR2_A_DQ[21]
DDR2_VREF
AD17
DDR2_A_DQ[22]
AD19
DDR2_A_DQ[23]
AD22
DDR2_A_DQ[24]
AB20
DDR2_A_DQ[25]
AF22
DDR2_A_DQ[26]
AD20
DDR2_A_DQ[27]
AB19
DDR2_A_DQ[28]
AE22
DDR2_A_DQ[29]
AC21
DDR2_A_DQ[30]
GND
AE21
DDR2_A_DQ[31]
AC9
DDR2_A_DQM[0]
AB10
DDR2_A_DQM[1]
AC19
DDR2 SDRAM LAYOUT GUIDE
DDR2_A_DQM[2]
AA19
DDR2_A_DQM[3]
1) a. DQS pairs will eventually have length matching rule to their respective byte lane data
b. CK pairs will eventually have length matching rule to address lines
2) The decaps and VREF resistors and caps should be laid out near the associated balls.For 7440 they should be
backside in the depopulated ring. VREF is the most senstive net ( in terms of isolation ) to route.
AE7
3) use top and bottom layers only.
DDR2_A_DQS0
AF7
4) Lay out escape plan per attached sketch
DDR2_A_DQS0#
5) Complete the layout of the wires in the following order. Keeping signals on their layer as much as possible:
CK pairs
AF8
DQS diff pairs
DDR2_A_DQS1
DQ and DM
AE8
remaining signals
DDR2_A_DQS1#
6) Signals can be freely substituted within the follwing groups: [RS] if this is done, the schematic should be updated to mach
DQ[7:0]
DQ[15:8]
DQ[23:16]
AE19
7) Diff pairs should be routed together 4 mil etch 4 mil spacing
DDR2_A_DQS2
AF19
8) Signals should be routed 4 mil etch 4 mil space min, 8 mil spacing mostly.
DDR2_A_DQS2#
9) Keep data lines separate from address lines, to avoid x-talk between the two
10) Prepare wire length report and schedule a review
AF20
11) LENGTH RULE: Data bits DDA2_n_DATA[31:0] <=1.5
DDR2_A_DQS3
12) Keep decoupling caps on back side out from beneath backing plate.
AE20
13) Route clocks as differential pairs - Match differential impedance
DDR2_A_DQS3#
60 ohm to plane.
120 ohm on pair
AE16
DDR2_A_BA[0]
AD16
DDR2_A_BA[1]
AC15
DDR2_A_BA[2]
AC12
DDR2_A_RAS#
AE12
DDR2_A_CAS#
AC16
DDR2_A_CKE
Y11
DDR2_A_CS#
AA15
DDR2_A_WE#
DDR2_A_RA[0-13]
AC13
DDR2_A_RA[0]
AA13
DDR2_A_RA[1]
AB13
DDR2_A_RA[2]
AF16
DDR2_A_RA[3]
AA12
DDR2_A_RA[4]
AE15
DDR2_A_RA[5]
AF13
DDR2_A_RA[6]
AE14
DDR2_A_RA[7]
AD13
DDR2_A_RA[8]
AD14
DDR2_A_RA[9]
AB14
DDR2_A_RA[10]
AF14
DDR2_A_RA[11]
Y14
DDR2_A_RA[12]
AE13
DDR2_A_RA[13]
AE11
DDR2_A_CLK0
R605
0
DDR2_D_CLK0
R604
100_1%
AF11
DDR2_A_CLK0#
R603
0
DDR2_D_CLK0#
AE23
DDR2_A_CLK1
R608
0
DDR2_D_CLK1
R607
100_1%
AF23
DDR2_A_CLK1#
R606
0
DDR2_D_CLK1#
AD11
DDR2_A_0DT
IC601
G2995P1X
1
8
1.8V
NC
VTT
2
7
GND
PVIN
3
6
R615
AVIN
0
VSENSE
4
5
VDDQ
VREF
3.3V
GND
D4
DVSS
E5
E23
DVSS
F21
F22
DVSS
F24
K10
DVSS
K13
DVSS
K14
K17
DVSS
L12
DVSS
L15
DVSS
L21
DQ[31:24]
L23
DVSS
M11
M12
M13
M14
DVSS
M15
M16
M22
DVSS
M24
DVSS
N10
DVSS
N12
N13
DVSS
N14
N15
N17
P10
DVSS
P12
P13
P14
P15
P17
R11
R12
R13
R14
R15
R16
T12
T15
U10
U13
U14
U17
U23
DVSS
V22
DVSS
V24
DVSS
AA11
AA17
AA21
AB6
AB12
DVSS
AB18
AB22
AC6
DVSS
AC11
AC17
AC23
AD12
AD18
AD24
DVSS
GND
IC301
MT8520
V21
DDR2_B_DQ[0]
BDQ0
W23
DDR2_B_DQ[1]
BDQ1
AA25
DDR2_B_DQ[2]
BDQ2
W22
DDR2_B_DQ[3]
BDQ3
Y22
DDR2_B_DQ[4]
BDQ4
Y24
DDR2_B_DQ[5]
BDQ5
W21
DDR2_B_DQ[6]
BDQ6
U20
DDR2_B_DQ[7]
BDQ7
T23
DDR2_B_DQ[8]
BDQ8
U25
DDR2_B_DQ[9]
BDQ9
T22
DDR2_B_DQ[10]
BDQ10
U22
DDR2_B_DQ[11]
B DQ11
V25
DDR2_B_DQ[12]
B DQ12
U26
DDR2_B_DQ[13]
B DQ13
T21
DDR2_B_DQ[14]
B DQ14
U24
DDR2_B_DQ[15]
B DQ15
K21
DDR2_B_DQ[16]
B DQ16
K23
DDR2_B_DQ[17]
B DQ17
K22
DDR2_B_DQ[18]
B DQ18
K24
DDR2_B_DQ[19]
B DQ19
J25
DDR2_B_DQ[20]
B DQ20
J21
DDR2_B_DQ[21]
B DQ21
H24
DDR2_B_DQ[22]
B DQ22
J23
DDR2_B_DQ[23]
B DQ23
G22
DDR2_B_DQ[24]
B DQ24
H22
DDR2_B_DQ[25]
B DQ25
G21
DDR2_B_DQ[26]
B DQ26
E26
DDR2_BDQ[27]
BDQ27
F25
DDR2_B_DQ[28]
BDQ28
F23
DDR2_B_DQ[29]
BDQ29
E25
DDR2_B_DQ[30]
BDQ30
E24
DDR2_B_DQ[31]
B DQ31
W24
BDQM0
DDR2_B_DQM[0]
V23
BDQM1
DDR2_B_DQM[1]
G26
DVSS
BDQM2
DDR2_B_DQM[2]
G23
BDQM3
DDR2_B_DQM[3]
DVSS
Y25
DVSS
BDQS0
DDR2_B_DQS0
Y26
BDQSB0
DDR2_B_DQS0#
DVSS
W26
BDQS1
DDR2_B_DQS1
W25
BDQSB1
DDR2_B_DQS1#
H25
DVSS
BDQS2
DDR2_B_DQS2
H26
BDQSB2
DDR2_B_DQS2#
DVSS
DVSS
G25
DVSS
BDQS3
DDR2_B_DQS3
G24
BDQSB3
DDR2_B_DQS3#
DVSS
DVSS
L24
B BA0
DDR2_
B
_BA[0]
M23
B BA1
DDR2_B_BA[1]
L25
BBA2
DDR2_B_BA[2]
DVSS
DVSS
P20
DVSS
BCAS#
DDR2_B_CAS#
K25
DVSS
BCKE
DDR2_B_CKE
T24
BRAS#
DDR2_B_RAS#
R23
DVSS
BRCS#
DDR2_B_CS#
K26
DVSS
BRWE#
DDR2_B_WE#
DVSS
DVSS
DVSS
P26
DDR2_B_RA[0]
DVSS
BRA0
N26
DDR2_B_RA[1]
DVSS
BRA1
P22
DDR2_B_RA[2]
DVSS
BRA2
L26
DDR2_B_RA[3]
DVSS
BRA3
R25
DDR2_B_RA[4]
DVSS
BRA4
M25
DDR2_B_RA[5]
DVSS
BRA5
M24
DDR2_B_RA[6]
DVSS
BRA6
M21
DDR2_B_RA[7]
DVSS
BRA7
P25
DDR2_B_RA[8]
DVSS
BRA8
N23
DDR2_B_RA[9]
DVSS
BRA9
N25
DDR2_B_RA[10]
DVSS
BRA10
N21
DDR2_B_RA[11]
DVSS
BRA11
N22
DDR2_B_RA[12]
DVSS
BRA12
P24
DDR2_B_RA[13]
BRA13
T25
DDR2_
B
_CLK0
DVSS
B RCLK
T26
DDR2_
B
_CLK0#
B RCLKB
DVSS
DVSS
DVSS
DVSS
D25
DDR2_
B
_CLK1
DVSS
B RCLK1
D26
DDR2_
B
_CLK1#
B RCLKB1
DVSS
DVSS
R21
DVSS
B 0DT
DDR2_
B
_0DT
DVSS
DDR2_
VREF
DVSS
L22
VDD_BRVREF
GND
;3:B4
DDR2_A_DQ[0-31]
DDR2_B_RA[0-13]
R611
0
DDR2_
D
_CLK2
R610
100_1%
R609
0
DDR2_
D
_CLK2#
R614
0
DDR2_D_CLK3
R613
100_1%
R612
0
DDR2_D_CLK3#
2-5
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