Arc Burst Pattern Analysis Algorithm; Arcing Suspected Algorithm; Overcurrent Disturbance Monitoring; Hi-Z Even Harmonic Restraint Algorithm - GE F60 Instruction Manual

FAULT LOCATOR

CHAPTER 9: THEORY OF OPERATION

9.1.9 Arc Burst Pattern Analysis algorithm

The Arc Burst Pattern Analysis algorithm attempts to provide faulted phase identification information based on a
correlation between the fault component of the measured neutral current and the phase voltages. The phase identified is
the one whose phase voltage peak lines up with the neutral current burst. The fault component is received from the Load
Extraction algorithm. The result of the analysis is checked by the Load Analysis algorithm if its other phase identification
methods prove unsuccessful.

9.1.10 Arcing Suspected algorithm

The purpose of the Arcing Suspected algorithm is to detect multiple, sporadic arcing events. If taken individually, such
events are not sufficient to warrant an arcing alarm. When taken cumulatively, however, these events do warrant an alarm
to system operators so that the cause of the recurrent arcing can be investigated.

9.1.11 Overcurrent disturbance monitoring

This function is part of High Impedance Fault Detection and is not be confused with conventional overcurrent protection.
The Hi-Z element monitors for an overcurrent condition on the feeder by establishing overcurrent thresholds for the
phases and for the neutral and then checking for a single two-cycle RMS current that exceeds those thresholds.
Oscillography and fault data are captured if it is determined that an overcurrent condition exists.

9.1.12 Hi-Z Even Harmonic Restraint algorithm

Every two-cycle interval, the algorithm evaluates the even harmonic content of each phase current. The even harmonic
content is evaluated as a percentage of the phase RMS current. If for any phase the percentage is greater than the
HI-Z
setting, the algorithm inhibits setting of the overcurrent flags. This is to prevent a cold-load
EVEN HARMONIC RESTRAINT
pickup event from starting the Hi-Z logic sequence (which requires the overcurrent flag or the loss-of-load flag to be set at
the beginning of an arcing event). The duration over which the algorithm inhibits the setting of the overcurrent flag(s) is
from the time the even-harmonic level (as a percentage of RMS) increases above the threshold until one second after it
falls back below the threshold.

9.1.13 Hi-Z Voltage Supervision algorithm

This algorithm was implemented to minimize the probability of a false Hi-Z indication due to bus voltage dips, for example
from parallel feeder faults. A fault on a parallel line can cause voltage dips that produce a decrease in the line load that
can be mistaken by the Hi-Z element as Loss of Load.
Every two cycles, the voltage on each phase is checked against the . If the voltage on any phase has
HI-Z V SUPV THRESHOLD
dropped by a percentage greater than or equal to this setting, the Loss of Load flag is blocked. The blocking is not done on
a per-phase basis. If one phase voltage shows a dip, the block is applied for all phases. Also the High Impedance
Oscillography records that a voltage dip was experienced. The Oscillography record is phase-specific.
9.2 Fault locator

9.2.1 Fault type determination

9
Fault type determination is required for calculation of fault location. The algorithm uses the angle between the negative
and positive sequence components of the relay currents. To improve accuracy and speed of operation, the fault
components of the currents are used; that is, the pre-fault phasors are subtracted from the measured current phasors. In
addition to the angle relationships, certain extra checks are performed on magnitudes of the negative and zero-sequence
currents.
The single-ended fault location method assumes that the fault components of the currents supplied from the local (A) and
remote (B) systems are in phase. The figure shows an equivalent system for fault location.
9-4 F60 FEEDER PROTECTION SYSTEM – INSTRUCTION MANUAL