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Functions
Pin
Requirements
Watchdog
WDOG
monitoring
Power-On-Reset
RESET_N
(POR)
RESET2_N
Voltage Supply
REG1
Logics
(2.9V)
Voltage Supply
REG2
Logics
(1,92V)
V 1.10
A52/A55/C55 IFX
Sequence
As soon as the first
detected during the TE4 timer, the device start
the watchdog monitoring procedure. Standard
switch off of the phone is the watchdog. The
first edge of watchdog is rising. If a falling edge
is detected as the first transient the device will
go to power down mode again and the whole
phone is switched off. Rising and falling edges
must be detected alternated. With any edge on
WDOG
(PinH3) pin a counter will be loaded.
The next - compared to the previous edge -
inverted edge must occur between end of T1,
and end of T2. If the signal occurs before end
of T1 or is not detected until end of T2, the
device
will
immediately after the violation of the watchdog
criteria occurs.
T1 min. 0,327s/ typ. 0,360s/ max. 0,400s
T2 min. 2,600s/ typ. 2,860s/ max. 3,178s
To guarantee a correct start-up of the ASIC, a
power on reset is needed at first power supply
ramping. Therefore a static/dynamic power on
reset circuit is added, which creates a reset
each time the power supply is connected. After
POR the
oscillator, read in the fuse content and goes
back to power down mode. If the power supply
will
drop
synchronous reset is done and the
to power down mode independently of the
previous operating mode.
The linear controller is designed for 2.9V(±2%)
and a maximum load current of 140 mA.
Voltage and current for the external Logic is
supplied from the internal 2.9V logic regulator.
The operating voltage
up to the maximum rated load current. A
reference voltage for the regulator circuit is
generated from a bandgap reference
The
linear
1.82V(±3%) and a maximum load current of
300 mA.
The REG2 supplies the Baseband Processor.
For a high power application, the power has to
be dissipated outside of the chip. This is done
with a series diode at the input of REG2, which
will force the regulator to a lower input voltage
and therefore lower power dissipation.
Page 27of 45
Company Confidential © Copyright Siemens AG
WDOG
(PinH3) pin rising is
go
to
power
ASIC
starts up the reference and the
under
the
POR
VREG1
is kept constant
controller
is
down
mode
threshold
a
ASIC
will go
designed
for
ICM MP CCQ GRM
08/03
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