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PWDN
SDI0 = L, R
SDI1 = LS, RS
SDI2 = C, SUB
1
2
SD1
+3.3V
3
LRCK
4
BICK
5
6
7
C17
POWER_ON_RST
8
100NF
Y5V
SDA
10
SCL
11
XTI
C14
+3.3V
2.2UF
6.3VDC
C15
100NF
Y5V
U2
SDI_1/SDATA_OUT
SLEFT_B
SDI_2/SDATA_IN
VDD_4
LRCKI/SYNC
GND_4
BCKI/BIT_CLK
LEFT_A
VDD_1
LEFT_B
GND_1
RIGHT_A
RESET
RIGHT_B
AC97_MODE
VDD_3
9
SDA
GND_3
SCL
SRIGHT_A
SA
SRIGHT_B
DDX4100A
+3.3V
+
C19
22UF
C20
6.3VDC
100NF
Y5V
EAPD2
SLEFTA
SLEFTB
33
32
31
C16
30
100NF
29
Y5V
28
27
26
+3.3V
25
24
23
C18
100NF
Y5V
SRIGHTA
SRIGHTB
L2
100NH
1
2
+3.3V
EIA0805
C21
C22
100NF
100NF
Y5V
Y5V
+3.3V
Title
5.1 CHANNEL SCHEMATIC REAR CHANNEL PROCESSING
Size
Document Number
B
150-0000-001
Date:
Thursday , February 14, 2002
Rev
A
Sheet
4
8
of
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