Hitachi HDR081 Service Manual page 9

Digital set top box
Hide thumbs Also See for HDR081:
Table of Contents

Advertisement

SERVICE MANUAL
IEC958/IEC1937 formatted output
The audio decoder outputs IEC958/IEC1937 formatted CD or PCM audio received from the audio
decoder.
1-channel PCM output interface
The PCM output interface outputs PCM audio received from the audio decoder.
Integrated 24-bit stereo audio DAC system
Programmable tone generation for dish alignment
4.4 Internal peripherals
The STi5100 has many dedicated internal peripherals for digital TV receiver applications, including:
2 smartcard controllers,
4 ASCs (UARTs), two of which are generally used by the smartcard controllers, teletext serializer
and DMA,
3 SSCs for I 2 C master/slave interfaces, with SPI support,
4.5 GPIO ports, with a further 1.5 ports mapped to transport pins,
1 PWM module,
a multichannel, infrared blaster/decoder interface module,
a modem analog front-end interface (MAFE),
DVB common interface support,
CableCard support,
fully integrated digital clock recovery for MPEG (replacement for VCXO),
USB 2.0 host, OHCI/EHCI compliant,
interface to SiLabs line side device (DAA),
an interrupt level controller,
a low-power/RTC/watchdog controller,
DCU toolset support,
a JTAG/TAP interface.
4.5 Clock generation
All system clocks are generated using the clock generator block. This contains two high-frequency PLLs
(600 MHz) that are divided down to produce a series of phase-related programmable clock channels. The
guaranteed phase relationship between these channels simplifies interconnect bridging between different
subsystem modules and gives lower latency compared to a fully asynchronous clocking scheme.
The STi5100 is a clock master. The flash clock output may be phase aligned to optimize the external bus
performance of the FMI.
Digital clock recovery for MPEG (DCO) has been integrated using a special purpose frequency
synthesizer, thus removing the need for an external varactor diode or VCXO module. An external VCXO
can still be used for genlocking applications.
4.6 System clock
External 27 MHz clock
Either a 27 MHz clock can be fed into CLK27IN, or a crystal pi network may be connected between
CLK27IN and CLK27OSC. The crystal option and internal VCO is the option recommended by
.
STMicroelectronics
Page 9

Advertisement

Table of Contents
loading

This manual is also suitable for:

Hdr161

Table of Contents