Hh-Board Block Diagram - Panasonic TY-FB8HM Service Manual

TY-FB8HM
7.2.

HH-Board Block Diagram

IC3303
A=3.3V, B=5V
/OE2
7
3 SDA 5
6 2
SCL
JK3301
1
D2+
2
D2G
3
D2-
4
D1+
5
D1G
6
D1-
7
D0+
8
D0G
9
D0-
10
CLK+
11
CLKG
12
CLK-
13
CEC
14
N.C.
15
SCL
16
DDC DATA
17
DDCG
5V_PLUG
18
+5V
19
HPDT
HDMI
INPUT
Q3301
Hot plug
detect control
IC3304
RESET
VOUT 4
IC3319
INVERTER
2 A
MODE SW
SW3301
IC3302
DDC EEPROM
C_WP
WP 7
C_SCL
SCL 6
C_SDA
5
SDA
TY-FB8HM HH-Board Block Diagram
IC3305
HDMI I/F RECEIVER
71
RESET#
72
CLK-
CSDA
REGISTERS 75
IIC
76
IIC CSCL
---------
SLAVE
74
SLAVE CONFIGURATION
77
LOGIC BLOCK
AUX DATA
MCLK
LOGIC
HDCP HDCP
OUT
BLOCK MLCK
KEYS DECRYPTION
26
EEPROM GEN
ENGINE
AUDIO MCLKIN
27
97
DATA
SCK
DECODE 32
XOR MODE
96
SDO
LOGIC
MASK CONTROL 30
92 BLOCK WS
PANEL LINK
31
TMDS CONTROL
91
SIGNALS
DIGITAL
87
CORE CONTROL
SIGNALS
86
84
83
37
R07
8 39
43
48
R00
VIDEO
G07 50
COLOR
8
52
SPACE
CONVERTER 54
UP/DOWN
G00 58
SAMPLING
B07 60
8
62 61
68
B00 70
HSYNC
33
VSYNC
34
ODCK
46
AnRPr
7
AnGY
12
AnBPb
15
IC3306
MICON
D_FA
D_FA 79
D_SCL
D-SCL 78
D_SDA
60 HDMI_INT
D-SDA 80
5 HDMI_RST
DV_S_MUTE 16
B-SCL 18
40 MODE INPUT
B-SDA 19
38 LVDS PD#
70
E-SCL
E-SDA 71
Y 4
IC3317
INVERTER
2 A Y 4
E_SCL
E_SDA
AUDIO MUTE
D_FA
D_SCL
D_SDA
IC3309
AUDIO AMP L
IC3301
B_SDA
B_SCL AUDIO DAC
2
6 SMUTE/CSN
6
1 MCLK
AOUT L
11
BICK IC3313
2
SDTI
3 D/A
AUDIO AMP R
LRCK
4 AOUT R
10
5 PDN
2
6
36
8
38
42
44
49
8
51
53
55
59
8
63
69
K_R
K_G
K_B
5V_PLUG
Q3302
Hi : MUTE
Audio Mute when cable is not connected
CABLE IN -> Hi : Norm
CABLE OUT -> Low : Mute
AUDIO MUTE CIRCUIT
Q3304,Q3305
Q3306,Q3307
Q3310
DV_S_MUTE IC3318
B_SCL
B_SDA
VIDEO AMP
Q3316
Q3313
+
2
K_R -
+
Q3317
7 -
Q3314
+
K_G
5 -
Q3318
Q3315
IC3308
K_B
EX. I/O
14
SCL
SW0 2
15 SDA
SW1 1
SW2 9
6 DAC1
SW3 10
3 DAC4
FOR
MICON
HQ2
LOADER
2 D-FA
4 D-SCL
5 D-SDA
10
9V
+ Q3311
1
-
9V
Q3308
+
7
-
AUD_L
Q3312
AUD_R
Q3309
IC3310
+
1
-
LVDS TRANSMITTER
+
7
-
DATA(LVDS)
3 56
R07 TX0+
47
55 54 8
TX0-
48
52 51
TX1+
2 50 45
R00
TX1-
46
14 12 G07
TX2+
8 41
11 7
TX2-
6 4 42
TX3+
10 8 G00
37
TX3-
38
24 23 B07
22 20 8
19 15
18 16 B00
J_G
CLOCK
27
HS J_B
(LVDS)
28 VS TXC+
39 J_R
PLL
31 TXC-
CLK IN 40
PWRDWN 32
IC3311
J_R
A=PANEL, B=BOARD
15 CONFIG ROM
for HP mode
J_B H_SDA H_SDA
10 SDA
5
H_SCL H_SCL
SCL 6
J_G
12
WP 7
A=PANEL, B=BOARD
IC3312
EX. I/O
H_SDA
4 P0 SCL 14
5 P1
H_SCL
SDA
6 P2 15
IC3314
CONFIG ROM
for HP mode
7
H_SCL
H_SDA
C_SCL
C_SDA
C_WP
TY-FB8HM HH-Board Block Diagram
TO
HQ1
J-BOARD
A26 L
A28
R
/0E2
B39
B3 TX0+
B2 TX0-
B6 TX1+
TX1-
B5
TX2+
B9
TX2-
B8
TX3+
B15
TX3-
B14
B12 TXC+
TXC-
B11
A38 J_G
J_B
A36
A34 J_R
G_SCL
B25
G-SCL
G_SDA
B24 G-SDA
G_SRQ
B23 G-SRQ
5V_STB 5V_STB
A22
9V A21
9V
B21 9V
5V A19 5V
B19 5V
3.3V
3.3V A17
B17 3.3V
G_SRQ
IC3315
1 /OE1
G_SDA
3 SDA 5
G_SCL
6 SCL 2
IC3316
1 /OE1
3 SDA 5
6 SCL 2
FOR
CONFING ROM,
DDC EEPROM
SDA 5
HQ3
WP SCL
6
9 DSDA
8 SCL
2 G-SRQ
WP
10
6 H_SCL
7 H_SDA
4 C-SCL
5 C-SDA
1 C_WP