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Bus Data Specifications
Data Structure
(1)
Write
Slave address
S
(90H or 92H)
(2)
Read
Slave address
S
(91H or 93H)
Note2: Slave address is switched by the voltage applied to pin 27 (address). Switched to 90H when low (GND);
switched to 92H when high (V
Contents of Data
Mode
Data No.
Data 1
[F0H]
Write
Data 2
[1FH]
Data 3
[07H]
Read
Data 4
Note3: Shown in [ ] are reset data.
Note4: The data contents marked by a slash (/) are an unused bit (data free).
W
A
Data 1
(0)
R
A
Data 4
(1)
) during write mode.
CC
B07
B06
Audio mute
L
TV
L
2
out
out
R
R
TV
R
2
out
out
B17
B16
Sync
Sync
detection
output
Sync (diagnosis) detection switching
sensitivity
switching
switching
B27
B26
DAC output switching
O5
O4
B37
B36
ADC input discrimination
I/O2
I/O3
Hi
A
Data 2
A
P
Contents of Data
B05
B04
B03
Forced TV
Audio
1
L
1
out
out
B15
B14
B13
B25
B24
B23
I/O3
I/O2
I/O1
B35
B34
B33
I/O2
I/O1
I/O1
Low
Hi
Low
TA1218N/F
A
Data 3
A
B02
B01
YC output switching
Y
out
B12
B11
Input select (main)
B22
B21
Input select (sub)
B32
B31
S input discrimination
Power-on
S1
C
S2
C
in
in
2000-09-11 15/40
P
B00
C
out
B10
B20
B30
reset
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