Block Diagram; Main Block Diagram - Panasonic TH-L24XM6Z Service Manual

TH-L24XM6Z

9 Block Diagram

9.1.

Main Block Diagram

2ndLow_IF,IFAGC
1stLow_IF IFAGC
Terrestrial(1)
or
Terestllial/cable(2)
cable
OPT
HDMI1
HPD* < STM
HDMI_5V_DET* > STM
HDMI2
HPD* < STM
HDMI_5V_DET* > STM
Only DTMB models(HK)
TS-IN
HS1BCLKIN
HS1SYNCIN
HS1VALIN
HS1DIN0
S3.3 S3.3 HS1DIN1
S3.3 / TU1.8 HS1DIN2
DCDC
HS1DIN3
1.2V HS1DIN4
HS1DIN5
DMD_IIC1 (IIC2) DMD IIC1 (IIC2) HS1DIN6 HS1DIN6
IF_AGC2
HS1DIN7
Low-IF2 HS1DIN8
DTMB
Demod.
< FE_XRST
Low-IF1
PCOE
IF_AGC1
PCWE
DMD_IIC0
PCIORD
PCIOWR
CXD2840
PCRESET
< FE_XRST
PCCE1
Terrestrial
Cross Stream Switch
DTV Decoder
VIF Decoder
ADC
SIF Decoder
VIO
Y1,Pb1,Pr1/V2
LIN1, RIN1
V-SW
V3
AV3(SIDE) INPUT CVBS)
Lin3,Rin3
AIO
R2, G2, B2, H,V
A-SW
HP_DET
Head Head
Phone
HP1_L/R
SOUND_VCC A-Chip
ALRCKO
ASDOUT0
AMP
ABCKO
ASMCK
Optical OUT
IECOUT
ARCOUT
Rx*
DDC* > STM, Peaks
HDMI
Rx*
Rx
MUX
DDC* > STM, Peaks
x3
XERWE0
XERWE0
STB5/5VS
CPU BUS XECS1
CTRL AAR/DATA
ERXW
S5/ S3.3
ES0
ES0
BOOTSWAP
ES1 Analog
XRST
ES2
ASIC
XRSTSTM
Support
< TV_SOS
ED[7:0]
AMP/HP MUTE
Card
MONITOROUT MUTE
JTAG
DTV_XRST
S3.3
2G - Function
VIErA-CAST Browser
EU MHP
UK BBC iPlayer
NAND
Latin GINGA MHP Latin GINGA MHP
S12 S12
Flash
1G
CI-IF
XNFCE,XNFW
Peaks
DCDC_EN
P Peaks
PCWAIT DCDC
NFCLE,NFALE DCDC
PCCD1 VM
XNFWE,XNFR
DTV_XRST >
PCCD2
JTAG
E
PCREADY SW_OFF_DET >
NANDRYBY
AFB
S1.1 S1.5 S3.3
ED[7:0] NFD[7:0]
CPUBUS
Trans Port Decoder NAND-IF
IIC
DMD
P-IIC2 (For DMD only)
DMD-IIC0
DMD-IIC1
Peaks
Video
Analog Video IPR INS
Format
Processor sLD8
Processor
DSP
I2S
SW
A-D Chip
Internal BUS D-Chip
DMD IIC IIC
DMD_IIC0 P-IIC0
DMD_IIC1 P-IIC1
AMP
PWM
SPDIF
SW
CLK
GEN
25MHz
20
S9
S12/S5
(SD-Data-VCC)
S9-REG S9 REG
3.3/1.8
UHS-1 < (SDVOLC)
REG
AN34043A
OVP
STB3.3V/1.2V_REG
SOS Safety
STB5V Reset IC (STM)
Circuit
S9V_REG
S12V Reset IC (Peaks)
Audio MUTE
< MON_MUTE
OCP/OVP/TV-SOS
< SP_HP_MUTE
HP_MUTE,EXT_MUTE
UHS-I_REG PWM >
TV_SOS
PWM
Back Light
PWM >
BL_ON >
BL_SOS <
INVERTER
or
STB3.3 LED Driver
STB1.2
XRST STB_XRST PWMA
POWER_DET
Panel
LVDS
HD : (DATA 4pairs / CLK 1pair) single8bit
FHD: (DATA 4pairs / CLK 1pair) dual8bit
DDR3
S1.5 S1.5
DDR3+(1333) DDR3+(1333)
DDR3+(1333) DDR3+(1333)
x16 x16
1G 1G
S5
USB
USB*VBUS >
< USB*OC
USB
Power SW S5 USB Memory
S5
USB USB
S5
USB*VBUS >
< USB*OC USB
Power SW S5
S5
LAN
SD CARD
Serial
P-Serial0
P-Serial1
P-UART0
P-UART2
S3.3
For Peaks
EEP
EEPROM_WP
EEP
P-IIC
STM
IIC
STM-IIC
Serial
STM-Serial0
STM-Serial1
STB3.3 < KEY3
POWER KEY
STB1.2
< KEY1
CONTROL PANEL KEY