Timer Enable Register (0X60C); Timer Control Status Register (Tcsr, 0X62C-0X62D,0X630-0X631); Table 3-11 Tcsr1 Bit Mapping; Table 3-12 Timer Control Status Registers - GE OpenVPX VPXcel6 SBC622 Hardware Reference Manual

3.2.20 Timer Enable Register (0x60C)

The timers are enabled via the Timer Enable Register located at offset 0x0C from
base I/O address 0x600. The mapping of the bits in this register are as follows:

Table 3-11 TCSR1 Bit Mapping

Field
Timer 1 Enable
Timer 2 Enable
Timer 3 Enable
Timer 4 Enable
Read Latch Select
Reserved
All of these bits default to "0" after system reset.
Each timer can be independently enabled by writing a ʺ1ʺ to the appropriate
ʺTimer x Enableʺ field.
The ʺRead Latch Selectʺ bit is used to select the latching mode of the
programmable timers. If this bit is set to ʺ0ʺ, then each timer output is latched
upon a read of the timerʹs LSB. For example, a read to the LSB of the TMRCCR2
register (Timer Current Count Register), address 0x0A, latches the count of timer
2. This continues for every read to any one of these registers. By setting this bit to
ʺ1ʺ, all four timer outputs will be latched only on a read to TMRCCR1ʹs LSB,
address 0x08. Therefore, to capture the current count of all four timers at the same
time, perform a read to the TMRCCR1 first, followed by a read to TMRCCR2,
TMRCCR3 and TMRCCR4. The first read causes all four timer values to be
latched at the same time. The subsequent reads to the other timer registers do not
latch new count values and may be read in any order.
3.2.21

Timer Control Status Register (TCSR, 0x62C-0x62D,0x630-0x631)

Each timer is controlled and monitored via the Timer Control Status Register
TCSRx, located at the following addresses:

Table 3-12 Timer Control Status Registers

Timer
TCSR1
TCSR2
TCSR3
TCSR4
The mapping of the bits in the registers is as follows:

Table 3-13 Timer Control Status Register Bit Map

Field Bits
IRQ Enable TCSR[0]
Timer Clock Select TCSR[2. .1]
Read Timer TCSR[3]
Reserved TCSR[6..4]
Interrupt TCSR[7}
All of these bits default to "0" after system reset.
Bits Read or Write
TE[0] R/W
TE[1] R/W
TE[2] R/W
TE[3] R/W
TE[4] R/W
TE [7 ..5] R/W
Address
0x62C (Not implemented on SBC622)
0x62D (Not implemented on SBC622)
0x630
0x631
Read or Write
R/W
R/W
R/W
R/W
R/W
Description
0=disable, 1=enable
0=disable, 1=enable
0=disable, 1=enable
0=disable, 1=enable
0=latch individual timers,
1=latch all timers
Description
0=disable, 1=enable
See Table 3-14 "Timer x Clock Select"
0=current timer value
1=timer load value
0=normal
1=generate interrupt
CPLD Control and Status Registers 57