Loading A 34 Mbit/S Plesiochronous Signal In The Vc-3 - Siemens SRA 4 User Manual

1.4.1.12
SRA 4 - 6/7/8/10/11/13 GHz (WB ODU) - UMN
911-381/02C0000 - Issue 3, July 2004

Loading a 34 Mbit/s plesiochronous signal in the VC-3

From the mapping function recommended by ITU-T for the loading of a plesiochronous
34 Mbit/s signal into the VC-3, as shown in Fig. 1.11, one can deduce that the VC-3, with
reference to its own clock, has a capacity for information bits that varies between a
minimum of:
[9 x (3 x 19)x 8 + 189] x 8 x 10
a b c d
obtained by forcing in each frame a fixed stuffing (S=R) for the "S" bits in Fig. 1.11, and
a maximum of:
[9 x (3 x 19)x 8 + 189 + 6] x 8 x 10
a b c d
obtained by forcing in each frame the loading of information bits (S=I) for the "S" bits in
Fig. 1.11,
a) byte per column
b) columns containing only information bits
c) bits of each byte
d) information bits contained in the last columns of Fig. 1.11
e) frame frequency (STM-1)
f) total number of "S" bits in each frame
From Fig. 1.11 on can also deduce that the following is loaded into the C-3 container:
3
(2 x 2 x 9) x 8 x 10 = 0.288 Mbit/s
(22 x 9 x 8 + 129) x 8 x 10
3
= 34.344 Mbit/s
e
3
= 34.392 Mbit/s
f e
3
= 13.704 Mbit/s
1 - PRELIMINARY INFORMATION
for transmission of the stuffing
message (C1, C2 in Fig. 1.11, that is:
6 bits for S1 and 6 bits for S2)
for fixed stuffing (R in Fig. 1.11)
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