Page 1 Hitachi 16-Bit Single-Chip Microcomputer H8S/2678 Series H8S/2677 HD64F2677, HD6432677 H8S/2676 HD64F2676, HD6432676 H8S/2675 HD6432675 H8S/2673 HD6432673 H8S/2670 HD6412670 Reference Manual ADE-602-192A Rev. 2.0 12/5/00 Hitachi, Ltd.
Page 2 Publication Date: 1st Edition, March 2000 2nd Edition, December 2000 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright © Hitachi, Ltd., 2000. All rights reserved. Printed in Japan.
Page 3 Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the information contained in this document.
Page 4 Main Revisions and Additions in this Edition Page Item Revisions (See Manual for Details) 1.2 Block Diagram Figure 1.1 Internal Block Diagram PLLVCC and PLLVSS pins added 4.5.12 Burst Operation Figure 4.29 Operation Timing in Fast Page Mode (1) Title in parentheses amended CAST = 1 →...
Page 6 ADE-602-192A The H8S/2600 Series, H8S/2000 Series Programming Manual gives a detailed description of the architecture and instruction set of the H8S/2600 CPU incorporated into H8S/2678 Series products. The H8S/2678 Series Hardware Manual describes the operation of on-chip functions common to H8S/2678 Series products, and gives a detailed description of the related registers.
Page 7 The contents of the H8S/2678 Series Hardware Manual and the H8S/2678 Series Reference Manual are summarized in table 2. Table 2 Contents of Hardware Manual and Reference Manual Hardware Reference Item Manual Manual Overview (Including pin arrangement) MCU operating modes (including memory maps) —...
Page 8 Pin functions 1.5 Pin Functions Electrical characteristics Section 7 Electrical Characteristics For detailed For details of operation of H8S/2678 Series modules information on functions I/O port information Section 5 I/O Ports Section 3 Exception Handling and Interrupts and exception handling...
Page 10: Table Of Contents
Contents Section 1 Overview ......................Overview..........................Block Diagram........................Pin Arrangement ........................ Pin Functions in Each Operating Mode................Pin Functions ........................Product Lineup........................Package Dimensions ......................28 Section 2 MCU Operating Modes ................. Overview..........................29 2.1.1 Operating Mode Selection (F-ZTAT Version)............. 2.1.2 Operating Mode Selection (ROMless and Mask ROM Versions) .......
Page 11 Interrupt Controller ......................54 3.2.1 Interrupt Controller Features ................54 3.2.2 Block Diagram...................... 55 3.2.3 Pin Configuration ....................3.2.4 Register Configuration ..................57 Register Descriptions......................58 3.3.1 Interrupt Control Register (INTCR)..............58 3.3.2 Interrupt Priority Registers A to K (IPRA to IPRK) ..........59 3.3.3 IRQ Enable Register (IER)...................
Page 12 4.2.4 Read Strobe Timing Control Register (RDNCR)..........CS Assertion Period Control Registers (CSACRH, CSACRL) ......101 4.2.5 4.2.6 Area 0 Burst ROM I/F Control Register (BROMCRH) Area 1 Burst ROM I/F Control Register (BROMCRL) ........103 4.2.7 Bus Control Register (BCR)................. 105 4.2.8 DRAM Control Register (DRAMCR)..............
Page 13 Idle Cycle........................... 165 4.7.1 Operation ......................165 4.7.2 Pin States in Idle Cycle..................173 Write Data Buffer Function ....................173 Bus Release........................174 4.9.1 Overview....................... 174 4.9.2 Operation ......................175 4.9.3 Pin States in External Bus Released State ............176 4.9.4 Transition Timing....................
Page 14 5.8.1 Overview....................... 233 5.8.2 Register Configuration ..................234 5.8.3 Pin Functions ......................236 Port 8..........................240 5.9.1 Overview....................... 240 5.9.2 Register Configuration ..................241 5.9.3 Pin Functions ......................242 5.10 Port A..........................246 5.10.1 Overview....................... 246 5.10.2 Register Configuration ..................247 5.10.3 Pin Functions ......................
Page 15 5.17.3 Pin Functions ......................290 5.18 Pin Functions ........................292 5.18.1 Port States in Each Processing State..............292 5.19 I/O Port Block Diagrams ....................297 5.19.1 Port 1........................297 5.19.2 Port 2........................301 5.19.3 Port 3........................303 5.19.4 Port 4........................307 5.19.5 Port 5........................
Page 16 6.6.2 Block Diagram...................... 357 6.6.3 Pins ........................358 8-Bit Timer......................... 358 6.7.1 Features......................... 358 6.7.2 Block Diagram...................... 359 6.7.3 Pins ........................360 Watchdog Timer ........................ 360 6.8.1 Features......................... 360 6.8.2 Block Diagram...................... 361 6.8.3 Pins ........................361 Serial Communication Interface ..................362 6.9.1 Features.........................
Page 17 7.1.1 Absolute Maximum Ratings................. 377 7.1.2 DC Characteristics ....................378 7.1.3 AC Characteristics ....................381 7.1.4 Conversion Characteristics................... 415 7.1.5 D/A Conversion Characteristics ................416 Electrical Characteristics of F-ZTAT Version (H8S/2677, H8S/2676)......417 7.2.1 Absolute Maximum Ratings................. 417 7.2.2 DC Characteristics ....................418 7.2.3 AC Characteristics ....................
Page 18: Section 1 Overview
Section 1 Overview Overview The H8S/2678 Series comprises microcomputers (MCUs), built around the H8S/2600 CPU, employing Hitachi’s original architecture, and equipped with on-chip supporting functions necessary for system configuration. The H8S/2600 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
Page 19 Table 1.1 Overview Item Specifications • General-register architecture  Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) • High-speed operation suitable for realtime control  Maximum operating frequency: 33 MHz  High-speed arithmetic operations 8/16/32-bit register-register add/subtract: 30 ns (33 MHz operation) 16 ×...
Page 20 Item Specifications • EXDMA controller Four DMA channels exclusively for external bus use (EXDMAC) • Selection of dual address mode or single address mode • Transfer possible in burst transfer mode, block transfer mode, etc. • Repeat area setting function •...
Page 21 Item Specifications • A/D converter Resolution: 10 bits • Input: 12 channels • 6.7 µs minimum conversion time (at 20 MHz operation) • Single or scan mode selectable • Sample-and-hold function • A/D conversion can be activated by external trigger or timer trigger •...
Page 22 Item Specifications • Operating modes Selection of twelve MCU operating modes (F-ZTAT™ version) External Data Bus Operating Operating Description On-Chip Initial Maximum Mode Mode Value Value — — — — — Advanced Expanded mode with on-chip ROM Disabled 16 bits 16 bits disabled 8 bits...
Page 23: Block Diagram
Block Diagram Port D Port E PA7/ A23 PA6/ A22 PA5/ A21 PA4/ A20 EXTAL PA3/ A19 XTAL PA2/ A18 STBY PA1/ A17 H8S/2600 CPU PA0/ A16 WDTOVF PB7/ A15 FWE * PB6/ A14 PB5/ A13 PB4/ A12 PF7 /ø Interrupt controller PB3 / A11 PF6 /AS...
Page 24: Pin Arrangement
Pin Arrangement PD7/D15 P52/SCK2/IRQ2 PE0/D0 P53/ADTRG/IRQ3 PE1/D1 PH2/CS6/(IRQ6) PH3/CS7/OE/(IRQ7) PE2/D2 PG4/ BREQO PE3/D3 PG5/BACK PE4/D4 PG6/BREQ PE5/D5 V CC P40/AN0 PE6/D6 P41/AN1 PE7/D7 P42/AN2 P61/TMRI1/DREQ1/IRQ9 P43/AN3 P60/TMRI0/DREQ0/IRQ8 Vref P27/PO7/TIOCB5/EDRAK1/(IRQ15) AVCC P44/AN4 P26/PO6/TIOCA5/EDRAK0/(IRQ14) P45/AN5 P25/PO5/TIOCB4/(IRQ13) P24/PO4/TIOCA4/(IRQ12) P46/AN6/DA0 Pin Arrangement P23/PO3/TIOCD3/(IRQ11) P47/AN7/DA1 (FP-144) P22/PO2/TIOCC3/(IRQ10) P54 /AN12/IRQ4...
Page 25: Pin Functions In Each Operating Mode
Pin Functions in Each Operating Mode Table 1.2 Pin Functions in Each Operating Mode Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode When EXPE = 1: P83/ P83/ P83/ P83/ P83/ P83/ETEND3/...
Page 26 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode PC5/A5 When EXPE = 1: PC5/A5 When EXPE = 0: PC6/A6 When EXPE = 1: PC6/A6 When EXPE = 0: PC7/A7 When EXPE = 1: PC7/A7 When EXPE = 0:...
Page 27 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode PB6/A14 When EXPE = 1: PB6/A14 When EXPE = 0: PB7/A15 When EXPE = 1: PB7/A15 When EXPE = 0: PA0/A16 When EXPE = 1: PA0/A16 When EXPE = 0:...
Page 28 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode PA7/A23 PA7/A23 PA7/A23 PA7/A23 PA7/A23 When EXPE = 1: PA7/A23 When EXPE = 0: P70/ P70/ P70/ P70/ P70/ When EXPE = 1: EDREQ0/ EDREQ0/ EDREQ0/...
Page 29 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode P11/PO9/ P11/PO9/ P11/PO9/ P11/PO9/ P11/PO9/ P11/PO9/ TIOCB0 TIOCB0 TIOCB0 TIOCB0 TIOCB0 TIOCB0 P12/PO10/ P12/PO10/ P12/PO10/ P12/PO10/ P12/PO10/ P12/PO10/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/...
Page 30 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode P24/PO4/ P24/PO4/ P24/PO4/ P24/PO4/ P24/PO4/ P24/PO4/ TIOCA4/ TIOCA4/ TIOCA4/ TIOCA4/ TIOCA4/ TIOCA4/ (IRQ12) (IRQ12) (IRQ12) (IRQ12) (IRQ12) (IRQ12) P25/PO5/ P25/PO5/ P25/PO5/ P25/PO5/ P25/PO5/ P25/PO5/...
Page 31 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode PE4/D4 PE4/D4 PE4/D4 When EXPE = 1: PE4/D4 When EXPE = 0: PE3/D3 PE3/D3 PE3/D3 When EXPE = 1: PE3/D3 When EXPE = 0: PE2/D2 PE2/D2 PE2/D2...
Page 32 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode When EXPE = 1: I/O3 When EXPE = 0: When EXPE = 1: I/O2 When EXPE = 0: When EXPE = 1: D9 I/O1 When EXPE = 0: When EXPE = 1: D8...
Page 33 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode PF2/LCAS/ PF2/LCAS/ PF2/LCAS/ PF2/LCAS/ PF2/LCAS/ When EXPE = 1: IRQ15 IRQ15 IRQ15 IRQ15 IRQ15 PF2/LCAS/ IRQ15 When EXPE = 0: PF2/IRQ15 PF3/LWR PF3/LWR PF3/LWR...
Page 34 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode PG2/CS2 PG2/CS2 PG2/CS2 PG2/CS2 PG2/CS2 When EXPE = 1: PG2/CS2 When EXPE = 0: PG3/CS3 PG3/CS3 PG3/CS3 PG3/CS3 PG3/CS3 When EXPE = 1: PG3/CS3 When EXPE = 0: PH0/CS4...
Page 35 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode PG5/BACK PG5/BACK PG5/BACK PG5/BACK PG5/BACK When EXPE = 1: PG5/BACK When EXPE = 0: PG6/BREQ PG6/BREQ PG6/BREQ PG6/BREQ PG6/BREQ When EXPE = 1: PG6/BREQ When EXPE = 0: P40/AN0...
Page 36 Flash Pin Name Memory Program- Mode 1 Mode 2 Mode 4 Mode 5 Mode 6 Mode 7 mer Mode P32/RxD0/ P32/RxD0/ P32/RxD0/ P32/RxD0/ P32/RxD0/ P32/RxD0/ IrRxD IrRxD IrRxD IrRxD IrRxD IrRxD P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P31/TxD1 P30/TxD0/ P30/TxD0/ P30/TxD0/ P30/TxD0/ P30/TxD0/ P30/TxD0/...
Page 37: Pin Functions
Clock XTAL Input For connection to a crystal oscillator. See section 19, Clock Pulse Generator, in the H8S/2678 Series Hardware Manual for typical connection diagrams for a crystal oscillator and external clock input. EXTAL Input For connection to a crystal oscillator.
Page 38 Pin No. Type Symbol FP-144 Name and Function Operating mode MD2 to MD0 1, 144, 143 Input Mode pins: These pins set the control operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the MCU is operating.
Page 39 Pin No. Type Symbol FP-144 Name and Function Interrupt signals Input Nonmaskable interrupt: Requests a nonmaskable interrupt. Fix high when not used. IRQ15 to 87, 86, Input Interrupt request 15 to 0: These pins IRQ0 84 to 81, request a maskable interrupt. 61, 60, 130 to 127, 110 to 107,...
Page 40 Pin No. Type Symbol FP-144 Name and Function UCAS Bus control Output Upper column address strobe: Upper column address strobe signal for 16-bit DRAM interface space. Column address strobe signal for 8-bit DRAM interface space. LCAS Output Lower column address strobe: Lower column address strobe signal for 16-bit DRAM interface space.
Page 41 Pin No. Type Symbol FP-144 Name and Function 16-bit timer pulse TCLKD to 51, 49, 46, Clock input D to A: External clock input unit (TPU) TCLKA Input pins. TIOCA0, 43 to 46 Input/ Input capture/output compare match TIOCB0, output A0 to D0: TGR0A to TGR0D input TIOCC0, capture input/output compare...
Page 42 Pin No. Type Symbol FP-144 Name and Function WDTOVF Watchdog timer Output Watchdog timer overflow: Counter (WDT) overflow signal output pin in watchdog timer mode. Serial communi- TxD2, TxD1, 107, 138, Output Transmit data (channels 0, 1, 2): Data cation interface TxD0/IrTxD output pins.
Page 43: Port 8
Pin No. Type Symbol FP-144 Name and Function I/O ports P17 to P10 51 to 48, Input/ Port 1: Eight input/output pins. The 46 to 43 output direction of each pin can be selected in the port 1 data direction register (P1DDR).
Page 44 Pin No. Type Symbol FP-144 Name and Function I/O ports PC7 to PC0 14, 13, Input/ Port C: Eight input/output pins. The 11 to 6 output direction of each pin can be selected in the port C data direction register (PCDDR).
Page 45: Product Lineup
Product Lineup Table 1.4 H8S/2678 Series Product Lineup Package Product Type Model Marking (Hitachi Package Code) H8S/2677* F-ZTAT™ version HD64F2677 HD64F2677VFC 144-pin plastic QFP (FP-144) H8S/2676* F-ZTAT™ version HD64F2676 HD64F2676VFC 144-pin plastic QFP (FP-144) Mask ROM version HD6432676 HD6432676FC H8S/2675*...
Page 46: Section 2 Mcu Operating Modes
Operating Mode Selection (F-ZTAT Version) The H8S/2678 Series F-ZTAT version has twelve operating modes (modes 1, 2, 4 to 7, and 10 to 15) that are selected by the flash write enable pin (FWE) and the mode pins (MD2 to MD0). The input at these pins determines the CPU operating mode and the initial bus width, as shown in table 2.1.
Page 47 Table 2.1 MCU Operating Mode Selection (F-ZTAT Version) External Data Operating Operating On-Chip Initial Max. Mode FWE MD2 MD1 MD0 Mode Description Width Width — — — — — Advanced Expanded mode Disabled 16 bits 16 bits with on-chip ROM disabled 8 bits 16 bits —...
Page 48: Operating Mode Selection (Romless And Mask Rom Versions)
For details see section 18, ROM, in the H8S/2678 Series Hardware Manual. The H8S/2678 Series F-ZTAT Version can be used only in modes 1, 2, 4 to 7, and 10 to 15. This means that the flash write enable pin and mode pins must be set to select one of these modes.
Page 49 ROM enabled Note: * Only modes 1 and 2 are available in the ROMless version. The CPU’s architecture allows for 4 gigabytes of address space, but the H8S/2678 Series chip actually accesses a maximum of 16 Mbytes. Modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices.
Page 50: Register Configuration
The H8S/2678 Series mask ROM version can be used only in modes 1, 2, and 4 to 7, and the ROMless version only in modes 1 and 2. This means that the mode pins must be set to select one of these modes.
Page 51: System Control Register (Syscr)
Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). For details see section 18, ROM, in the H8S/2678 Series Hardware Manual. In the mask ROM and ROMless versions, 0 should be written to this bit.
Page 52: Operating Mode Descriptions
This is an externally expanded mode with on-chip ROM disabled. Operation is the same as in mode 1, except that the initial external bus mode after a reset is 8 bits. 2.3.3 Mode 3 This mode is not supported in the H8S/2678 Series, and must not be selected.
Page 53: Mode 4 (Expanded Mode With On-Chip Rom Enabled)
2.3.4 Mode 4 (Expanded Mode with On-Chip ROM Enabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B, and C function as input ports immediately after a reset, but can be set to function as an address bus.
Page 54: Modes 8 And 9 [F-Ztat Version Only]
2.3.9 Mode 10 [F-ZTAT Version Only] This is a flash memory boot mode. For details see section 18, ROM, in the H8S/2678 Series Hardware Manual. Except for flash memory erasing and programming, operation is the same as in mode 4 (advanced expanded mode with on-chip ROM enabled).
Page 55: Pin Functions In Each Operating Mode
Pin Functions in Each Operating Mode The pin functions of ports A to H vary depending on the operating mode. Table 2.4 shows their functions in each operating mode. Table 2.4 Pin Functions in Each Operating Mode Mode Mode Mode Mode Mode Mode...
Page 56: Memory Map In Each Operating Mode
H8S/2675, and 64 kbytes in the H8S/2673; the on-chip RAM capacity is 8 kbytes. The address space is divided into eight areas. For details see section 4, Bus Controller. Only advanced mode is supported in the H8S/2678 Series.
Page 57 Modes 1 and 2 Mode 4 (expanded modes (expanded mode with on-chip ROM disabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM External address space H'060000 External address space H'FFA000 H'FFA000 On-chip RAM/external On-chip RAM/external address space* address space* H'FFC000 H'FFC000 External address space External address space...
Page 58 Modes 5 and 6 Mode 7 (external ROM activation (single-chip activation expanded modes expanded mode with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM External address space H'060000 H'100000 On-chip ROM External address space/reserved area H'160000 External address space H'FFA000 H'FFA000...
Page 59 Mode 10 Boot mode Mode 11 Boot mode (expanded mode (single-chip activation expanded mode with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM On-chip ROM H'060000 H'060000 External address External space/reserved area address space H'FFA000 H'FFA000 On-chip RAM On-chip RAM H'FFC000 H'FFC000...
Page 60 Modes 13 and 14 Mode 15 User program mode (external ROM activation Mode 12 User program mode (single-chip activation expanded modes (expanded mode expanded mode with on-chip ROM enabled) with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External...
Page 61 Modes 1 and 2 Mode 4 (expanded modes (expanded mode with on-chip ROM disabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'040000 External address space External address space H'FFA000 H'FFA000 On-chip RAM/external On-chip RAM/external address space* address space* H'FFC000 H'FFC000 External address space External address space...
Page 62 Modes 5 and 6 Mode 7 (external ROM activation (single-chip activation expanded modes expanded mode with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM External address space H'040000 H'100000 External address On-chip ROM space/reserved area H'140000 External address space H'FFA000 H'FFA000...
Page 63 Mode 10 Boot mode Mode 11 Boot mode (expanded mode (single-chip activation expanded mode with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM On-chip ROM H'040000 H'040000 External address External space/reserved area address space H'FFA000 H'FFA000 On-chip RAM On-chip RAM H'FFC000 H'FFC000...
Page 64 Mode 15 User program mode Modes 13 and 14 Mode 12 User program mode (single-chip activation (external ROM activation (expanded mode expanded mode expanded modes with on-chip ROM enabled) with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 H'000000 On-chip ROM On-chip ROM External...
Page 65 Modes 1 and 2 Mode 4 (expanded modes (expanded mode with on-chip ROM disabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'020000 External External address space address space H'FFA000 H'FFA000 On-chip RAM/external On-chip RAM/external address space* address space* H'FFC000 H'FFC000 External address space External address space...
Page 66 Modes 5 and 6 Mode 7 (external ROM activation (single-chip activation expanded modes expanded mode with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'020000 External address space External address H'100000 space/reserved area On-chip ROM H'120000 External address space H'FFA000 H'FFA000...
Page 67 Modes 1 and 2 Mode 4 (expanded modes (expanded mode with on-chip ROM disabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'010000 External External address space address space H'FFA000 H'FFA000 On-chip RAM/external On-chip RAM/external address space* address space* H'FFC000 H'FFC000 External address space External address space...
Page 68 Modes 5 and 6 Mode 7 (external ROM activation (single-chip activation expanded modes expanded mode with on-chip ROM enabled) with on-chip ROM enabled) H'000000 H'000000 On-chip ROM H'010000 External address space External address space/reserved area H'100000 On-chip ROM H'110000 External address space H'FFA000 H'FFA000...
Page 69 Modes 1 and 2 (expanded modes with on-chip ROM disabled) H'000000 External address space H'FFA000 On-chip RAM/external address space* H'FFC000 External address space H'FFFC00 Internal I/O registers H'FFFF00 External address space H'FFFF20 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 2.13 H8S/2670 Memory Map in Each Operating Mode...
Page 70: Section 3 Exception Handling And Interrupt Controller
INTM0 and INTM1 bits in INTCR. For details of exception handling and the interrupt controller, see section 2, Exception Handling, and section 3, Interrupt Controller, in the H8S/2678 Series Hardware Manual. Table 3.1...
Page 71: Interrupt Controller
Interrupt Controller 3.2.1 Interrupt Controller Features • Two interrupt control modes  Either of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the interrupt control register (INTCR). • Priorities settable with IPRs ...
Page 72: Block Diagram
3.2.2 Block Diagram Figure 3.1 shows a block diagram of the interrupt controller. INTM1 INTM0 INTCR NMIEG NMI input NMI input unit Interrupt request IRQ input unit IRQ input Vector number Priority ITSR ISCR determination Internal interrupt sources I2 to I0 SWDTEND to TEI Interrupt controller...
Page 73: Pin Configuration
3.2.3 Pin Configuration Table 3.2 summarizes the interrupt controller pins. Table 3.2 Interrupt Controller Pins Name Abbreviation Function Nonmaskable interrupt Input Nonmaskable external interrupt; rising or falling edge can be selected IRQ15 to IRQ0 External interrupt request Input Maskable external interrupts; rising, 15 to 0 falling, or both edges, or level sensing, can be selected...
Page 74: Register Configuration
3.2.4 Register Configuration Table 3.3 summarizes the registers of the interrupt controller. Table 3.3 Interrupt Controller Registers Initial Name Abbreviation Value Address* Interrupt control register INTCR H'00 H'FF31 IRQ sense control register H ISCRH H'0000 H'FE1A IRQ sense control register L ISCRL H'0000 H'FE1C...
Page 75: Register Descriptions
Register Descriptions 3.3.1 Interrupt Control Register (INTCR) — — INTM1 INTM0 NMIEG — — — Initial value Read/Write — — — — — INTCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. INTCR is initialized to H'00 by a reset and in hardware standby mode.
Page 76: Interrupt Priority Registers A To K (Ipra To Iprk)
3.3.2 Interrupt Priority Registers A to K (IPRA to IPRK) — IPR14 IPR13 IPR12 — IPR10 IPR9 IPR8 Initial value Read/Write — — — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value Read/Write — — The IPR registers are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI.
Page 77: Irq Enable Register (Ier)
As shown in table 3.4, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding interrupt.
Page 78: Irq Sense Control Registers H And L (Iscrh, Iscrl)
3.3.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA Initial value Read/Write IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ8SCB IRQ8SCA Initial value Read/Write ISCRL IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value Read/Write IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA...
Page 79: Irq Status Register (Isr)
Bits 15 to 0—IRQ15 Sense Control A and B (IRQ15SCA, IRQ15SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) IRQnSCB IRQnSCA Description Interrupt request generated at IRQn input low level (Initial value) Interrupt request generated at falling edge of IRQn input Interrupt request generated at rising edge of IRQn input Interrupt request generated at both falling and rising edges of IRQn input...
Page 80 Bits 15 to 0—IRQ15 to IRQ0 Flags (IRQ15F to IRQ0F): These bits indicate the status of IRQ15 to IRQ0 interrupt requests. Bit n IRQnF Description [Clearing conditions] (Initial value) • When 0 is written to IRQnF after reading IRQnF = 1 •...
Page 81: Irq Pin Select Register (Itsr)
3.3.6 IRQ Pin Select Register (ITSR) ITS15 ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 Initial value Read/Write ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 Initial value Read/Write ITSR is a 16-bit readable/writable register that selects input pins IRQ15 to IRQ0. ITSR is initialized to H'0000 by a reset and in hardware standby mode.
Page 82: Software Standby Release Irq Enable Register (Ssier)
When an ITSR setting is changed, if the selected pin level before the change is different from the selected pin level after the change, an edge may be generated internally and IRQnF (n = 0 to 15) in ISR may be set at an unintended timing. If the IRQn interrupt (n = 0 to 15) is enabled at this time, the associated interrupt exception handling will be executed.
Page 83: Interrupt Sources
Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ15 to IRQ0) and internal interrupts (56 sources). 3.4.1 External Interrupts There are 17 external interrupt sources: NMI and IRQ15 to IRQ0. Setting an SSI bit to 1 in SSIER enables the corresponding IRQ15–IRQ0 interrupt to be used as a software standby mode release source.
Page 84: Internal Interrupts
Figure 3.3 shows the timing of the setting of IRQnF. ø IRQn input pin IRQnF Figure 3.3 Timing of Setting of IRQnF The vector numbers for IRQ15 to IRQ0 interrupt exception handling are 31 to 16. Detection of IRQ15 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output.
Page 85: Interrupt Vector Table
3.4.3 Interrupt Vector Table Table 3.5 shows interrupt exception handling sources, their vector addresses, and their priority order. In the default priority order, smaller vector numbers have higher priority. Priorities among modules can be set by means of IPR. The priority order when two or more modules are set to the same priority, and the priority order within a module, are fixed as shown in table 3.5.
Page 86 Table 3.5 Interrupt Sources, Vector Addresses, and Priority Order Origin of DMAC Interrupt Vector Vector Activa- Activa- Interrupt Source Source Number Address* Priority tion tion Power-on reset H'0000 — High — — Reserved H'0004 Reserved for system H'0008 H'000C H'0010 Trace H'0014 Reserved for system...
Page 87 Origin of DMAC Interrupt Vector Vector Activa- Activa- Interrupt Source Source Number Address* Priority tion tion SWDTEND (software- H'0080 IPRE14– High — activated data transfer IPRE12 end) WOVI (interval timer) Watchdog H'0084 IPRE10–IPRE8 — — timer Reserved — H'0088 IPRE6–IPRE4 —...
Page 88 Origin of DMAC Interrupt Vector Vector Activa- Activa- Interrupt Source Source Number Address* Priority tion tion TGI3A (TGR3A input H'00E0 IPRG10– High capture/compare match) channel 3 IPRG8 TGI3B (TGR3B input H'00E4 — capture/compare match) TGI3C (TGR3C input H'00E8 — capture/compare match) TGI3D (TGR3D input H'00EC —...
Page 89 Origin of DMAC Interrupt Vector Vector Activa- Activa- Interrupt Source Source Number Address* Priority tion tion DMTEND0A (channel DMAC H'0140 IPRH6–IPRH4 High — 0/channel 0A transfer end) DMTEND0B (channel 0B H'0144 — transfer end) DMTEND1A (channel H'0148 — 1/channel 1A transfer end) DMTEND1B (channel 1B H'014C —...
Page 90 Origin of DMAC Interrupt Vector Vector Activa- Activa- Interrupt Source Source Number Address* Priority tion tion Reserved — H'0190 IPRJ6–IPRJ4 High — — H'0194 H'0198 H'019C H'01A0 IPRJ2–IPRJ0 H'01A4 H'01A8 H'01AC H'01B0 IPRK14–IPRK12 H'01B4 H'01B8 H'01BC H'01C0 IPRK10–IPRK8 H'01C4 H'01C8 H'01CC H'01D0 IPRK6–IPRK4...
Page 91: Interrupt Operation
3.5.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2678 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt.
Page 92 Figure 3.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 Interrupt acceptance control Default priority Interrupt source Vector number determination 8-level mask control I2 to I0 Interrupt control mode 2 Figure 3.4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance control is performed by means of the I bit in CCR.
Page 93 8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed according to the interrupt priority level (IPR) for interrupts selected in interrupt acceptance control. The interrupt source selected is the interrupt with the highest priority level, and for which the priority level set in IPR is higher than the mask level.
Page 94: Interrupt Control Mode 0
3.5.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when the I bit is set to 1.
Page 95 Program execution state Interrupt generated? NMI? I = 0? Hold pending IRQ0? IRQ1? TEI2? Save PC and CCR I ← 1 Read vector address Branch to interrupt service routine Figure 3.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0...
Page 96: Interrupt Control Mode 2
3.5.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 3.6 shows a flowchart of the interrupt acceptance operation in this case. 1.
Page 97 Program execution state Interrupt generated? NMI? Level 7 interrupt? Level 6 interrupt? Mask level 6 Level 1 interrupt? or below? Mask level 5 or below? Mask level 0? Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt...
Page 98: Interrupt Exception Handling Sequence
3.5.4 Interrupt Exception Handling Sequence Figure 3.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory.
Page 99 Figure 3.7 Interrupt Exception Handling...
Page 100: Interrupt Response Times
3.5.5 Interrupt Response Times The H8S/2678 Series is capable of fast word access to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 3.10 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt service routine.
Page 101: Usage Notes
Usage Notes 3.6.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction.
Page 102: Instructions That Disable Interrupts
3.6.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts except NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value is valid two states after instruction execution is completed.
Page 103: Block Diagram
4. Selection of a number of the above For details of interrupt requests that can be used to activate the DTC or DMAC, see section 6, Data Transfer Controller, and section 5, DMA Controller, in the H8S/2678 Series Hardware Manual.
Page 104: Operation
3.7.3 Operation The interrupt controller has three main functions in DTC and DMAC control. Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected with bits DTF3 to DTF0 in DMACR.
Page 105 Table 3.12 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCE Bits Origin of Interrupt Vector Vector Address Interrupt Source Source Number Advanced Mode DTCE* Priority Write to DTVECR Software DTVECR H'0400+ — High (DTVECR[6:0]<<1) IRQ0 External pin H'0420 DTCEA7 IRQ1 H'0422 DTCEA6 IRQ2...
Page 106 Origin of Interrupt Vector Vector Address Interrupt Source Source Number Advanced Mode DTCE* Priority TGI3A (TGR3A compare H'0470 DTCED5 High match/input capture) channel 3 TGI3B (TGR3B compare H'0472 DTCED4 match/input capture) TGI3C (TGR3C compare H'0474 DTCED3 match/input capture) TGI3D (TGR3D compare H'0476 DTCED2 match/input capture)
Page 107 Table 3.13 Interrupt Source Selection and Clearing Control Settings DMAC Interrupt Source Selection/Clearing Control DTCE DISEL DMAC Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt service routine.) : The relevant interrupt is used.
Page 108: Section 4 Bus Controller
Section 4 Bus Controller Overview The H8S/2678 Series has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories and external I/O devices to be connected easily.
Page 109 • Idle cycle insertion  An idle cycle can be inserted in case of external read cycles in different areas  An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle •...
Page 110: Block Diagram
4.1.2 Block Diagram EXDMAC address bus Address CS7 to CS0 Area decoder selector Internal address bus WAIT BREQ BACK External bus controller BREQO Internal bus master bus request signal External bus EXDMAC bus request signal arbiter External bus Internal bus master bus acknowledge signal control signals EXDMAC bus acknowledge signal Internal bus control signals...
Page 111: Pin Configuration
4.1.3 Pin Configuration Table 4.1 summarizes the pins of the bus controller. Table 4.1 Bus Controller Pins Abbre- Name viation Function Address strobe Output Strobe signal indicating that address output on address bus is enabled during access to basic bus interface space. Read Output Strobe signal indicating that basic bus...
Page 112 Abbre- Name viation Function Chip select 5/row address Output Strobe signal indicating that area 5 is strobe 5 selected. DRAM row address strobe signal when area 5 is DRAM interface space. Chip select 6 Output Strobe signal indicating that area 6 is selected.
Page 113: Register Configuration
4.1.4 Register Configuration Table 4.2 summarizes the registers of the bus controller. Table 4.2 Bus Controller Registers Register Initial Value Size Name Abbreviation Reset Address* (Bits) Bus width control register ABWCR H'FF/H'00* H'FEC0 Access state control register ASTCR H'FF H'FEC1 Wait control register A WTCRA H'7777...
Page 114: Register Descriptions
Register Descriptions 4.2.1 Bus Width Control Register (ABWCR) ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 2, 4, 6 Initial value Read/Write Modes 1, 5, 7 Initial value Read/Write ABWCR is an 8-bit readable/writable register that designates each area as either 8-bit access space or 16-bit access space.
Page 115: Wait Control Registers A And B (Wtcra, Wtcrb)
ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 116: Read Strobe Timing Control Register (Rdncr)
WTCRB — — Initial value Read/Write — — Initial value Read/Write Bits 15, 11, 7, and 3—Reserved: These bits are always read as 0 and cannot be modified. Bits 14 to 12, 10 to 8, 6 to 4, 2 to 0—Wait Control (Wn2, Wn1, Wn0): These bits select the number of program wait states for areas designated as 3-state access space in ASTCR.
Page 117 RDNCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 to 0—Read Strobe Timing Control (RDNn): As shown in figure 4.2, the read strobe for an area for which the RDNn bit is set to 1 is negated one half-state earlier than that for an area for which the RDNn bit is cleared to 0.
Page 118: Cs Assertion Period Control Registers (Csacrh, Csacrl)
CS Assertion Period Control Registers (CSACRH, CSACRL) 4.2.5 CSACRH CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0 Initial value Read/Write CSACRL CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0 Initial value Read/Write CSACRH and CSACRL are 8-bit readable/writable registers that specify whether or not the assertion period of the basic bus interface chip select signals (CSn) and address signals is to be extended.
Page 119 CSACRH Bits 7 to 0—CS and Address Signal Assertion Period Control 1 (CSXH7 to CSXH0): These bits specify whether or not the T cycle shown in figure 4.3 is to be inserted. When an area for state, in which only the CSn and address signals which the CSXHn bit is set to 1 is accessed, a T are asserted, is inserted before the normal access cycle.
Page 120: Area 0 Burst Rom I/F Control Register (Bromcrh) Area 1 Burst Rom I/F Control Register (Bromcrl)
Bus cycle Address Read Data HWR, LWR Write Data Figure 4.3 CS and Address Assertion Period Extension (Example of 3-State Access Space and RDWn = 0) 4.2.6 Area 0 Burst ROM I/F Control Register (BROMCRH) Area 1 Burst ROM I/F Control Register (BROMCRL) BROMCRH BSRM0 BSTS02 BSTS01 BSTS00...
Page 121 BROMCRH and BROMCRL are 8-bit readable/writable registers used to make burst ROM interface settings. Area 1 and area 0 burst ROM interface settings can be made independently in BROMCRH and BROMCRL, respectively. BROMCRH and BROMCRL are initialized to H'0000 by a reset and in hardware standby mode. They are not initialized in software standby mode.
Page 122: Bus Control Register (Bcr)
Bit 1 Bit 0 BSWDn1 BSWDn0 Description Maximum 4 words in area n burst access (Initial value) Maximum 8 words in area n burst access Maximum 16 words in area n burst access Maximum 32 words in area n burst access (n = 1 or 0) 4.2.7 Bus Control Register (BCR)
Page 123 when an internal bus master performs an external space access, or when a refresh request is generated. Bit 14 BREQOE Description BREQO output disabled BREQO pin can be used as I/O port (Initial value) BREQO output enabled Bit 13—Reserved: This is a readable/writable bit, but the write value should always be 0. Bit 12—Idle Cycle State Number Select (IDLC): Selects the number of states in the idle cycle set by ICIS1 and ICIS0.
Page 124: Dram Control Register (Dramcr)
Bit 9—Write Data Buffer Enable (WDBE): Selects whether or not the write data buffer function is used for an external write cycle or DMAC single address transfer cycle. Bit 9 WDBE Description Write data buffer function not used (Initial value) Write data buffer function used Bit 8—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin.
Page 125 Bit 15 Description OE signal output disabled OE pin can be used as I/O port (Initial value) OE signal output enabled Bit 14—RAS Assertion Timing Select (RAST): Selects whether, in DRAM access, the RAS signal is asserted from the start of the T cycle (rising edge of ø) or from the falling edge of ø.
Page 126 Bit 12—Column Address Output Cycle Number Select (CAST): Selects whether the column address output cycle in DRAM access comprises 3 states or 2 states. The setting of this bit applies to all areas designated as DRAM space. Bit 12 CAST Description Column address output cycle comprises 2 states (Initial value)
Page 127 Bit 6—RAS Down Mode (RCDM): When access to DRAM space is interrupted by an access to normal bus space, an access to an internal I/O register, etc., this bit selects whether the RAS signal is held low while waiting for the next DRAM access (RAS down mode), or is driven high again (RAS up mode).
Page 128 Bit 4 EDDS Description Full access is always executed when EXDMAC single address transfer is performed in DRAM space (Initial value) Burst access is possible when EXDMAC single address transfer is performed in DRAM space Bit 3—Reserved: This is a readable/writable bit, but the write value should always be 0. Bits 2 to 0—Address Multiplex Select (MXC2 to MXC0): These bits select the size of the shift toward the lower half of the row address in row address/column address multiplexing.
Page 129: Dram Access Control Register (Draccr)
4.2.9 DRAM Access Control Register (DRACCR) DRMI — TPC1 TPC0 — — RCD1 RCD0 Initial value Read/Write DRACCR is an 8-bit readable/writable register used to set the DRAM interface bus specifications. DRACCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Page 130: Refresh Control Register (Refcr)
Bit 1 Bit 0 RCD1 RCD0 Description Wait cycle not inserted between RAS assert cycle and CAS assert cycle (Initial value) 1-state wait cycle inserted between RAS assert cycle and CAS assert cycle 2-state wait cycle inserted between RAS assert cycle and CAS assert cycle 3-state wait cycle inserted between RAS assert cycle and CAS assert cycle...
Page 131 Bit 15 Description [Clearing conditions] • When 0 is written to CMF after reading CMF = 1 while the RFSHE bit is cleared to (Initial value) • When CBR refreshing is executed while the RFSHE bit is set to 1 [Setting condition] When RTCOR = RTCNT Bit 14—Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests...
Page 132 Bit 10 Bit 9 Bit 8 RTCK2 RTCK1 RTCK0 Description Count operation halted (Initial value) Count on ø/2 Count on ø/8 Count on ø/32 Count on ø/128 Count on ø/512 Count on ø/2048 Count on ø/4096 Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When refresh control is not performed, the refresh timer can be used as an interval timer.
Page 133 Bit 3—Self-Refresh Enable (SLFRF): If this bit is set to 1, DRAM self-refresh mode is selected when a transition is made to the software standby state. This bit is valid when the RFSHE bit is set to 1, enabling refresh operations. It is cleared after recovery from software standby mode.
Page 134: Refresh Timer Counter (Rtcnt)
4.2.11 Refresh Timer Counter (RTCNT) Initial value Read/Write RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits RTCK2 to RTCK0 in REFCR. When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and RTCNT is cleared to H'00.
Page 135: Overview Of Bus Control
Overview of Bus Control 4.3.1 Area Division The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 4.5 shows an outline of the memory map.
Page 136: Bus Specifications
4.3.2 Bus Specifications The external space bus specifications consist of five elements: (1) bus width, (2) number of access states, (3) number of program wait states, (4) read strobe timing, and (5) chip select (CS) assertion period extension states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller.
Page 137: Memory Interfaces
4.3.3 Memory Interfaces The memory interfaces of the H8S/2678 Series comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can...
Page 138 An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space. The initial state of each area is basic bus interface, 3-state access space.
Page 139: Chip Select Signals
When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. 4.3.4 Chip Select Signals The chip can output chip select signals (CS0 to CS7) for areas 0 to 7, the signal being driven low when the corresponding external space area is accessed.
Page 140: Basic Bus Interface
Basic Bus Interface 4.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, and CSACR. For details see table 4.3. 4.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Page 141: Valid Strobes
16-Bit Access Space: Figure 4.8 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword access is executed as two word accesses.
Page 142 Table 4.4 Data Buses Used and Valid Strobes Access Read/ Valid Upper Data Bus Lower Data Bus Area Size Write Address Strobe (D15 to D8) (D7 to D0) 8-bit access Byte Read — Valid Invalid space Write — Hi-Z 16-bit access Byte Read Even...
Page 143: Basic Timing
4.4.4 Basic Timing 8-Bit, 2-State Access Space: Figure 4.9 shows the bus timing for an 8-bit, 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle ø...
Page 144 8-Bit, 3-State Access Space: Figure 4.10 shows the bus timing for an 8-bit, 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle ø...
Page 145 16-Bit, 2-State Access Space: Figures 4.11 to 4.13 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be inserted.
Page 146 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 4.12 Bus Timing for 16-Bit, 2-State Access Space (2) (Odd Address Byte Access)
Page 147 Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 4.13 Bus Timing for 16-Bit, 2-State Access Space (3) (Word Access)
Page 148 16-Bit, 3-State Access Space: Figures 4.14 to 4.16 show bus timings for a 16-bit, 3-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the odd address, and the lower half (D7 to D0) for the even address. Wait states can be inserted.
Page 149 Bus cycle ø Address bus D15 to D8 Invalid Read D7 to D0 Valid High Write High impedance D15 to D8 D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 4.15 Bus Timing for 16-Bit, 3-State Access Space (2) (Odd Address Byte Access)
Page 150 Bus cycle ø Address bus D15 to D8 Valid Read D7 to D0 Valid Write D15 to D8 Valid D7 to D0 Valid Notes: 1. n = 0 to 7 2. When RDNn = 0 Figure 4.16 Bus Timing for 16-Bit, 3-State Access Space (3) (Word Access)
Page 151: Wait Control
4.4.5 Wait Control When accessing external space, the H8S/2678 Series chip can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: (1) program wait insertion and (2) pin wait insertion using the WAIT pin.
Page 152 By WAIT pin By program wait ø WAIT Address bus Read Data bus Read data HWR, LWR Write Data bus Write data Notes: 1. Downward arrows indicate the timing of WAIT pin sampling. 2. When RDNn = 0 Figure 4.17 Example of Wait State Insertion Timing The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input disabled.
Page 153: Read Strobe (Rd) Timing
4.4.6 Read Strobe (RD) Timing The read strobe timing can be changed for individual areas by setting bits RDN7 to RDN0 to 1 in RDNCR. When the DMAC or EXDMAC is used in single mode, note that if the read strobe timing is changed by setting RDNn to 1, the RD timing will change relative to the rise of DACK or EDACK.
Page 154: Extension Of Chip Select (Cs) Assertion Period
4.4.7 Extension of Chip Select (CS) Assertion Period Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert states in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle.
Page 155: Dram Interface
4.5.1 Overview In the H8S/2678 Series, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. The DRAM interface allows DRAM to be directly connected to the chip. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in DRAMCR.
Page 156: Address Multiplexing
4.5.3 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to MXC0 in DRAMCR. Table 4.6 shows the correspondence between the settings of MXC2 to MXC0 and the shift size. Table 4.6 Address Multiplexing Settings by Bits MXC2 to MXC0 DRAMCR...
Page 157: Pins Used For Dram Interface
4.5.5 Pins Used for DRAM Interface Table 4.7 shows the pins used for DRAM interfacing and their functions. Table 4.7 DRAM Interface Pins With DRAM Setting Name Function Write enable Output Write enable for DRAM space access RAS2 Row address strobe 2 Output Row address strobe when area 2 is designated as DRAM space...
Page 158: Basic Timing
4.5.6 Basic Timing Figure 4.20 shows the basic access timing for DRAM space. The four states of the basic timing consist of one T (precharge cycle) state, one T (row address output cycle) state, and the T and T (column address output cycle) states. ø...
Page 159: Column Address Output Cycle Control
output from both the RD pin and the OE pin, but in external read cycles for other than DRAM space, the signal is output only from the RD pin. 4.5.7 Column Address Output Cycle Control The column address output cycle can be changed from 2 states to 3 states by setting the CAST bit to 1 in the DRAMCR register.
Page 160: Row Address Output Cycle Control
4.5.8 Row Address Output Cycle Control If the RAST bit is set to 1 in the DRAMCR register, the RAS signal goes low from the beginning of the T state, and the row address hold time and DRAM read access time are changed relative to the fall of the RAS signal.
Page 161 If a row address hold time or read access time is necessary, making a setting in bits RCD1 and RCD0 in the DRACCR register allows from one to three T states, in which row address output is cycle, in which the RAS signal goes low, and the T maintained, to be inserted between the T cycle, in which the column address is output.
Page 162: Precharge State Control
4.5.9 Precharge State Control When DRAM is accessed, a RAS precharge time must be secured. With the H8S/2678 Series, one state is always inserted when DRAM space is accessed. From one to four T states can be selected by setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T cycles according to the DRAM connected and the operating frequency of the chip.
Page 163: Wait Control
4.5.10 Wait Control There are two ways of inserting wait states in a DRAM access cycle: (1) program wait insertion and (2) pin wait insertion using the WAIT pin. Wait states are inserted to extend the CAS assertion period in a read access to DRAM space, and to extend the write data setup time relative to the falling edge of CAS in a write access.
Page 164 By WAIT pin By program wait ø WAIT Row address Column address Address bus RASn (CSn) UCAS, LCAS WE (HWR) High Read OE (RD) Data bus UCAS, LCAS WE (HWR) Write OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 4.25 Example of Wait State Insertion Timing (1) (2-State Column Address Output)
Page 165 By WAIT pin By program wait ø WAIT Row address Column address Address bus RASn (CSn) UCAS, LCAS WE (HWR) High Read OE (RD) Data bus UCAS, LCAS WE (HWR) Write OE (RD) High Data bus Note: Downward arrows indicate the timing of WAIT pin sampling. n = 2 to 5 Figure 4.26 Example of Wait State Insertion Timing (2) (3-State Column Address Output)
Page 166: Byte Access Control
4.5.11 Byte Access Control When DRAM with a ×16 configuration is connected, the 2-CAS access method is used for the control signals needed for byte access. Figure 4.27 shows the control timing for 2-CAS access, and figure 4.28 shows an example of 2- CAS DRAM connection.
Page 167: Burst Operation
H8S/2678 Series chip 2-CAS type 16-Mbit DRAM 1-Mbyte × 16-bit configuration (Address shift size set to 10 bits) 10-bit column address RASn (CSn) UCAS UCAS LCAS LCAS HWR (WE) RD (OE) Row address input: A9 to A0 Column address input:...
Page 168 ø Row address Column address 1 Column address 2 Address bus RASn (CSn) UCAS, LCAS WE (HWR) High OE (RD) Read Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 4.29 Operation Timing in Fast Page Mode (1) (RAST = 0, CAST = 0)
Page 169 ø Row address Column address 1 Column address 2 Address bus RASn (CSn) UCAS, LCAS WE (HWR) High OE (RD) Read Data bus WE (HWR) Write OE (RD) High Data bus Note: n = 2 to 5 Figure 4.30 Operation Timing in Fast Page Mode (2) (RAST = 0, CAST = 1) The bus cycle can also be extended in burst access by inserting wait states.
Page 170  the external bus is released  the RCDM bit or BE bit is cleared to 0 If a transition is made to the all-module-clocks-stopped mode in the RAS down state, the clock will stop with RAS low. To enter the all-module-clocks-stopped mode with RAS high, the RCDM bit must be cleared to 0 before executing the SLEEP instruction.
Page 171: Refresh Control
(RAST = 0, CAST = 0) 4.5.13 Refresh Control The H8S/2678 Series is provided with a DRAM refresh control function. CAS-before-RAS (CBR) refreshing is used. In addition, self-refreshing can be executed when the chip enters the software standby state. Refresh control is enabled when any area is designated as DRAM space in accordance with the setting of bits RMTS2 to RMTS0 in the DRAMCR register.
Page 172 Refreshing is thus repeated at fixed intervals determined by RTCOR and bits RTCK2 to RTCK0. Set a value in RTCOR and bits RTCK2 to RTCK0 that will meet the refreshing interval specification for the DRAM used. When bits RTCK2 to RTCK0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits RTCK2 to RTCK0.
Page 173 ø CSn (RASn) UCAS, LCAS Figure 4.35 CBR Refresh Timing A setting can be made in bits RCW1 and RCW0 to delay RAS signal output by one to three cycles. Use bits RLW1 and RLW0 to adjust the width of the RAS signal. The settings of bits RCW1, RCW0, RLW1, and RLW0 are valid only in refresh operations.
Page 174 Normal access space request ø A23 to A0 HWR (WE) Refresh period Figure 4.37 Example of CBR Refresh Timing (CBRM = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and SLFRF bit to 1 in the REFCR register.
Page 175 Software standby ø CSn (RASn) UCAS, LCAS HWR (WE) High Note: n = 2 to 5 Figure 4.38 Self-Refresh Timing In some DRAMs provided with a self-refresh mode, the RAS signal precharge time after self- refreshing is longer than the normal precharge time. A setting can be made in bits TPCS2 to TPCS0 in the REFCR register to make the precharge time after self-refreshing from 1 to 7 states longer than the normal precharge time.
Page 176: Dmac And Exdmac Single Address Transfer Mode And Dram Interface
Figure 4.39 Example of Timing when Precharge Time after Self-Refreshing Is Extended by 2 States Refreshing and All-Module-Clocks-Stopped Mode: In the H8S/2678 Series, if the ACSE bit is set to 1 in the MSTPCR register, and then a SLEEP instruction is executed with the setting for all...
Page 177 When DDS = 1 or EDDS = 1: Burst access is performed by determining the address only, irrespective of the bus master. With the DRAM interface, the DACK or EDACK output goes low from the T state. Figure 4.40 shows the DACK/EDACK output timing for the DRAM interface when DDS = 1 or EDDS = 1.
Page 178 When DDS = 0 or EDDS = 0: When DRAM space is accessed in DMAC or EXDMAC single address transfer mode, full access (normal access) is always performed. With the DRAM interface, the DACK or EDACK output goes low from the T state.
Page 179: Burst Rom Interface
4.6.1 Overview In the H8S/2678 Series, external space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM space interface enables ROM with burst access capability to be accessed at high speed.
Page 180 Full access Burst access ø Upper address bus Lower address bus Data bus Note: n = 1 or 0 Figure 4.42 Example of Burst ROM Access Timing (1) (ASTn = 1, 2-State Burst Cycle)
Page 181: Wait Control
Full access Burst access ø Upper address bus Lower address bus Data bus Note: n = 1 or 0 Figure 4.43 Example of Burst ROM Access Timing (2) (ASTn = 0, 1-State Burst Cycle) 4.6.3 Wait Control As with the basic bus interface, either (1) program wait insertion or (2) pin wait insertion using the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface.
Page 182: Idle Cycle
Idle Cycle 4.7.1 Operation When the H8S/2678 Series chip accesses external space, it can insert an idle cycle (T ) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. Insertion of a 1- state or 2-state idle cycle can be selected with the IDLC bit in the BCR register.
Page 183 Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1 in the BCR register, an idle cycle is inserted at the start of the write cycle. Figure 4.45 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Page 184 Bus cycle A Bus cycle B Bus cycle A Bus cycle B ø ø Address bus Address bus CS (area A) CS (area A) CS (area B) CS (area B) Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (b) Idle cycle inserted (ICIS1 = 0) (ICIS1 = 1 (initial value))
Page 185 In burst access in RAS down mode, the settings of bits ICIS1, ICIS0, and IDLC are valid and an idle cycle is inserted. The timing in this case is illustrated in figures 4.48 and 4.49. DRAM space read External read DRAM space read ø...
Page 186 DRAM space read External read DRAM space write ø Address bus UCAS, LCAS Data bus Idle cycle Figure 4.49 Example of Idle Cycle Operation in RAS Down Mode (2) (Read after Write) (IDLC = 0, RAST = 0, CAST = 0) Idle Cycle in Case of Normal Space Access after DRAM Space Access: While the DRMI bit is cleared to 0 in the DRACCR register, idle cycle insertion after DRAM space access is disabled.
Page 187 DRAM space read External read DRAM space read ø Address bus UCAS, LCAS Data bus Idle cycle Figure 4.50 Example of Idle Cycle Operation after DRAM Access (1) (Consecutive Reads in Different Areas) (IDLC = 0, RAST = 0, CAST = 0) DRAM space read External write DRAM space read...
Page 188 Table 4.8 shows when idle cycles are inserted in the case of mixed accesses to normal space and DRAM space. Table 4.8 Idle Cycles in Mixed Accesses to Normal Space and DRAM Space Previous Access Next Access ICIS1 ICIS0 DRMI IDLC Idle cycle Normal space read...
Page 189 DRAM space read DRAM space write Address bus RASn (CSn) UCAS, LCAS WE (HWR) OE (RD) Data bus Idle cycle Note: n = 2 to 5 Figure 4.52 Example of Timing for Idle Cycle Insertion in Case of Consecutive Read and Write Accesses to DRAM Space in RAS Down Mode...
Page 190: Pin States In Idle Cycle
2. Remains low in a DRAM space refresh cycle. Write Data Buffer Function The H8S/2678 Series has a write data buffer function for the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses.
Page 191: Bus Release
4.9.1 Overview The H8S/2678 Series chip can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters (except the EXDMAC) continue to operate as long as there is no external access.
Page 192: Operation
1 in the BCR register. Driving the BREQ pin low issues an external bus request to the H8S/2678 Series chip. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high- impedance state, establishing the external bus released state.
Page 193: Pin States In External Bus Released State
4.9.3 Pin States in External Bus Released State Table 4.10 shows pin states in the external bus released state. Table 4.10 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn (n = 7 to 0) High impedance UCAS, LCAS...
Page 194: Transition Timing
4.9.4 Transition Timing Figure 4.54 shows the timing for transition to the bus released state. External space access cycle External bus released state CPU cycle ø High-Z Address bus High-Z Data bus High-Z High-Z High-Z HWR , LWR BREQ BACK BREQO [1] Low level of BREQ signal is sampled at rise of ø.
Page 195: Usage Notes
External Bus Release Function and Software Standby: In the H8S/2678 Series, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip ROM, etc., and no external access occurs.
Page 196: Bus Arbitration
4.10.1 Overview The H8S/2678 Series has a bus arbiter that arbitrates bus master operations. There are four bus masters—the CPU, DTC, DMAC, and EXDMAC—that perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal.
Page 197: Bus Transfer Timing
4.10.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately.
Page 198: Bus Controller Operation In A Reset
For details see section 7, EXDMA Controller, in the H8S/2678 Series Hardware Manual. External Bus Release: When the BREQ pin goes low and an external bus release request is issued while the BRLE bit is set to 1 in the BCR register, a bus request is sent to the bus arbiter.
Page 200: Section 5 I/O Ports
Section 5 I/O Ports Overview The H8S/2678 Series has fifteen I/O ports (ports 1 to 3, P50 to P53, 6 to 8, and A to H), and two input-only ports (port 4 and P54 to P57). Table 5.1 summarizes the port functions. The pins of each port also have other functions.
Page 201 Table 5.1 Port Functions Modes Mode Mode Port Description Pins 1, 2, 5, 6 Port 1 • 8-bit I/O • When EXPE = 0 (after reset): P17/PO15/TIOCB2/ 2-bit I/O port also functioning as port TCLKD/EDRAK3 EXDMA controller output pins 2-bit I/O port also functioning (EDRAK3, EDRAK2), TPU I/O as TPU I/O pins (TCLKD, •...
Page 202 Modes Mode Mode Port Description Pins 1, 2, 5, 6 Port 2 • 8-bit I/O P25/PO5/TIOCB4/ 6-bit I/O port also functioning as TPU I/O pins (TIOCA3, TIOCB3, IRQ13 port TIOCC3, TIOCD3, TIOCA4, TIOCB4), interrupt input pins (IRQ13 to IRQ8), and PPG output pins (PO5 to PO0) •...
Page 203 Modes Mode Mode Port Description Pins 1, 2, 5, 6 Port 5 • 4-bit I/O P57/AN15/DA3/IRQ7 4-bit input port also functioning as A/D converter analog inputs port (AN15 to AN12), D/A converter analog outputs (DA3, DA2), and P56/AN14/DA2/IRQ6 interrupt input pins (IRQ7 to IRQ4) •...
Page 204 Modes Mode Mode Port Description Pins 1, 2, 5, 6 Port 8 • 6-bit I/O • When EXPE = 0 (after reset): P85/EDACK3/IRQ5 6-bit I/O port also functioning as port EXDMA controller I/O pins 6-bit I/O port also functioning P84/ EDACK2/IRQ4 (EDACK3, EDACK2, ETEND3, as interrupt input pins (IRQ5 P83/ETEND3/IRQ3...
Page 205 Modes Mode Mode Port Description Pins 1, 2, 5, 6 Port D • 8-bit I/O PD7/D15–PD0/D8 Data bus input/output When EXPE = 0 (after reset): port I/O port • Built-in When EXPE = 1: Data bus MOS input input/output pull-up Port E •...
Page 206 Modes Mode Mode Port Description Pins 1, 2, 5, 6 Port F • 8-bit I/O PF1/UCAS/IRQ14 When areas 2 to 5 are all When EXPE = 0 (after reset), or port normal space (after reset): I/O when EXPE = 1 and areas 2 to port also functioning as IRQ14 5 are all normal space: I/O port also functioning as IRQ14...
Page 207 Modes Mode Mode Port Description Pins 1, 2, 5, 6 Port G • 7-bit I/O PG2/CS2 When CS2E = 0 (after reset): When EXPE = 0 (after reset), or port I/O port when EXPE1 = 1 and CS2E = 0: I/O port When CS2E = 1 and DDR = 0: Input port When EXPE = 1, CS2E = 1,...
Page 208 Modes Mode Mode Port Description Pins 1, 2, 5, 6 Port H • 4-bit I/O PH2/CS6/IRQ6 When CS6E = 0 (after reset): When EXPE = 0 (after reset), or port I/O port also functioning as when EXPE = 1 and CS6E = 0: IRQ6 interrupt input I/O port also functioning as IRQ6 interrupt input...
Page 209: Port 1
Port 1 5.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and EXDMAC output pins (EDRAK2 and EDRAK3). The functions of pins P15 to P10 are the same in all operating modes, while the functions of pins P17 and P16 change according to the operating mode.
Page 210: Register Configuration
5.2.2 Register Configuration Table 5.2 shows the port 1 register configuration. Table 5.2 Port 1 Registers Name Abbreviation Initial Value Address* Port 1 data direction register P1DDR H'00 H'FE20 Port 1 data register P1DR H'00 H'FF60 Port 1 register PORT1 Undefined H'FF50 Note: * Lower 16 bits of the address.
Page 211: Pin Functions
Port 1 Register (PORT1) Initial value —* —* —* —* —* —* —* —* Read/Write Note: * Determined by the state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. PORT1 cannot be written to; writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR.
Page 212 Table 5.3 Port 1 Pin Functions Selection Method and Pin Functions P17/PO15/ The pin function is switched as shown below according to the combination of the TIOCB2/ TPU channel 2 settings (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TCLKD/ TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in TCR0 EDRAK3...
Page 213 Selection Method and Pin Functions P16/PO14/ The pin function is switched as shown below according to the combination of the TIOCA2/ TPU channel 2 settings (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in EDRAK2 TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, bit EDRAKE in EDMDR2 and bit P16DDR.
Page 214 Selection Method and Pin Functions P15/PO13/ The pin function is switched as shown below according to the combination of the TIOCB1/ TPU channel 1 settings (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TCLKC TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.
Page 215 Selection Method and Pin Functions P14/PO12/ The pin function is switched as shown below according to the combination of the TIOCA1 TPU channel 1 settings (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR.
Page 216 Selection Method and Pin Functions P13/PO11/ The pin function is switched as shown below according to the combination of the TIOCD0/ TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TCLKB TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR.
Page 217 Selection Method and Pin Functions P12/PO10/ The pin function is switched as shown below according to the combination of the TIOCC0/ TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TCLKA TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR.
Page 218 Selection Method and Pin Functions P11/PO9/ The pin function is switched as shown below according to the combination of the TIOCB0 TPU channel 0 settings (by bits MD3 to MD0 in TMDR0 and bits IOB3 to IOB0 in TIOR0H), bit NDER9 in NDERH, and bit P11DDR. TPU channel 0 (1) in table (2) in table below...
Page 219 Selection Method and Pin Functions P10/PO8/ The pin function is switched as shown below according to the combination of the TIOCA0 TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER8 in NDERH, and bit P10DDR.
Page 220: Port 2
Port 2 5.3.1 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as PPG output pins (PO7 to PO0), TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), EXDMAC output pins (EDRAK0 and EDRAK1), and interrupt input pins (IRQ15 to IRQ8). The functions of pins P25 to P20 are the same in all operating modes, while the functions of pins P27 and P26 change according to the operating mode.
Page 221: Register Configuration
5.3.2 Register Configuration Table 5.4 shows the port 2 register configuration. Table 5.4 Port 2 Registers Name Abbreviation Initial Value Address* Port 2 data direction register P2DDR H'00 H'FE21 Port 2 data register P2DR H'00 H'FF61 Port 2 register PORT2 Undefined H'FF51 Note: * Lower 16 bits of the address.
Page 222: Pin Functions
Port 2 Register (PORT2) Initial value —* —* —* —* —* —* —* —* Read/Write Note: * Determined by the state of pins P27 to P20. PORT2 is an 8-bit read-only register that shows the pin states. PORT2 cannot be written to; writing of output data for the port 2 pins (P27 to P20) must always be performed on P2DR.
Page 223 Table 5.5 Port 2 Pin Functions Selection Method and Pin Functions P27/PO7/ The pin function is switched as shown below according to the combination of the TIOCB5/ TPU channel 5 settings (by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in IRQ15/ TIOR5, and bits CCLR1 and CCLR0 in TCR5), bit NDER7 in NDERL, bit EDRAK1...
Page 224 Selection Method and Pin Functions P26/PO6/ The pin function is switched as shown below according to the combination of the TIOCA5/ TPU channel 5 settings (by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in IRQ14/ TIOR5, and bits CCLR1 and CCLR0 in TCR5), bit NDER6 in NDERL, bit EDRAK0 EDRAKE in EDMDR0, bit P26DDR, and bit ITS14 in ITSR.
Page 225 Selection Method and Pin Functions P25/PO5/ The pin function is switched as shown below according to the combination of the TIOCB4/ TPU channel 4 settings (by bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in IRQ13 TIOR4, and bits CCLR1 and CCLR0 in TCR4), bit NDER5 in NDERL, bit P25DDR, and bit ITS13 in ITSR.
Page 226 Selection Method and Pin Functions P24/PO4/ The pin function is switched as shown below according to the combination of the TIOCA4/ TPU channel 4 settings (by bits MD3 to MD0 in TMDR4 and bits IOA3 to IOA0 in IRQ12 TIOR4), bit NDER4 in NDERL, bit P24DDR, and bit ITS12 in ITSR. TPU channel 4 (1) in table (2) in table below...
Page 227 Selection Method and Pin Functions P23/PO3/ The pin function is switched as shown below according to the combination of the TIOCD3/ TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in IRQ11 TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER3 in NDERL, bit P23DDR, and bit ITS11 in ITSR.
Page 228 Selection Method and Pin Functions P22/PO2/ The pin function is switched as shown below according to the combination of the TIOCC3/ TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in IRQ10 TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER2 in NDERL, bit P22DDR, and bit ITS10 in ITSR.
Page 229 Selection Method and Pin Functions P21/PO1/ The pin function is switched as shown below according to the combination of the TIOCB3/IRQ9 TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER1 in NDERL, bit P21DDR, and bit ITS9 in ITSR.
Page 230 Selection Method and Pin Functions P20/PO0/ The pin function is switched as shown below according to the combination of the TIOCA3/IRQ8 TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER0 in NDERL, bit P20DDR, and bit ITS8 in ITSR.
Page 231: Port 3
Port 3 5.4.1 Overview Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI input/output pins (TxD0/IrTxD, RxD0/IrRxD, SCK0, TxD1, RxD1, and SCK1), and a bus control signal output pin (OE). The functions of pins P34 to P30 are the same in all operating modes, while the function of pin P35 changes according to the operating mode.
Page 232: Register Configuration
5.4.2 Register Configuration Table 5.6 shows the port 3 register configuration. Table 5.6 Port 3 Registers Name Abbreviation Initial Value* Address* Port 3 data direction register P3DDR H'00 H'FE22 Port 3 data register P3DR H'00 H'FF62 Port 3 register PORT3 Undefined H'FF52 Port 3 open drain control register...
Page 233 Port 3 Data Register (P3DR) — — P35DR P34DR P33DR P32DR P31DR P30DR Initial value Read/Write — — P3DR is a 6-bit readable/writable register that stores output data for the port 3 pins (P35 to P30). Bits 7 and 6 are reserved; they are always read as 0 and cannot be modified. P3DR is initialized to H'00 (bits 5 to 0) by a reset and in hardware standby mode.
Page 234: Pin Functions
P3ODR is a 6-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P35 to P30). Bits 7 and 6 are reserved; they are always read as 0 and cannot be modified. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin.
Page 235 Table 5.7 Port 3 Pin Functions Selection Method and Pin Functions P35/SCK1/OE The pin function is switched as shown below according to the combination of the C/A bit in SMR of SCI1, bits CKE0 and CKE1 and RMTS2 to RMTS0 in SCR, bit OES in PFCR2, and bit P35DDR.
Page 236 Selection Method and Pin Functions P33/RxD1 The pin function is switched as shown below according to the combination of bit RE in SCR of SCI1 and bit P33DDR. P33DDR — Pin function P33 input pin P33 output pin* RxD1 input pin Note: * NMOS open-drain output when P33ODR = 1.
Page 237: Port 4
Port 4 5.5.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes.
Page 238: Pin Functions
Port 4 Register (PORT4) The pin states are always read when a port 4 read is performed. Initial value —* —* —* —* —* —* —* —* Read/Write Note: * Determined by the state of pins P47 to P40. 5.5.3 Pin Functions Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1).
Page 239: Port 5
Port 5 5.6.1 Overview Port 5 comprises a 4-bit I/O port (P53 to P50) and a 4-bit input-only port (P57 to P54). Port 5 pins also function as SCI input/output pins (TxD2, RxD2, and SCK2), the A/D converter input pin (ADTRG), A/D converter analog input pins (AN12 to AN15), D/A converter analog output pins (DA2 and DA3), and interrupt input pins (IRQ7 to IRQ0).
Page 240 Port 5 Data Direction Register (P5DDR) — — — — P53DDR P52DDR P51DDR P50DDR Initial value Read/Write — — — — P5DDR is a 4-bit write-only register, the individual bits of which specify input or output for the pins of port 5. P5DDR cannot be read; if it is, an undefined value will be read. Bits 7 to 4 are reserved.
Page 241: Pin Functions
PORT5 is an 8-bit read-only register that shows the pin states. PORT5 cannot be written to; writing of output data for the port 5 pins (P53 to P50) must always be performed on P5DR. When a port 5 read is performed, the pin states are always read from bits 7 to 4 regardless of the P5DDR settings.
Page 242 Table 5.10 Port 5 Pin Functions Selection Method and Pin Functions P57/AN15/ The pin function is switched as shown below according to bit ITS7 in ITSR. DA3/IRQ7 IRQ7 interrupt input pin* Pin function AN15 input DA3 output Note: * IRQ7 input when ITS7 = 0. P56/AN14/ The pin function is switched as shown below according to bit ITS6 in ITSR.
Page 243 Selection Method and Pin Functions P52/SCK2/ The pin function is switched as shown below according to the combination of bit IRQ2 C/A in SMR of SCI2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR. CKE1 —...
Page 244: Port 6
Port 6 5.7.1 Overview Port 6 is a 6-bit I/O port. Port 6 pins also function as 8-bit timer input/output pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1), interrupt input pins (IRQ13 to IRQ8), and DMAC input/output pins (DREQ0, TEND0, DACK0, DREQ1, TEND1, and DACK1). Port 6 pin functions are the same in all operating modes.
Page 245 Port 6 Data Direction Register (P6DDR) — — P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value Read/Write — — P6DDR is a 6-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Bits 7 and 6 are reserved.
Page 246: Pin Functions
Bits 7 and 6 are reserved; if read they will return an undefined value. If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. After a reset and in hardware standby mode, PORT6 contents are determined by the pin states, as P6DDR and P6DR are initialized.
Page 247 Table 5.12 Port 6 Pin Functions Selection Method and Pin Functions P65/TMO1/ The pin function is switched as shown below according to the combination of bit DACK1/IRQ13 DMACS in PFCR2, bit SAE1 in DMABCRH, bits OS3 to OS0 in TCSR1 of the 8- bit timer, bit P65DDR, and bit ITS13 in ITSR.
Page 248 Selection Method and Pin Functions P63/TMCI1/ The pin function is switched as shown below according to the combination of bit TEND1/IRQ11 DMACS in PFCR2, bit TEE1 in DMATCR of the DMAC, bit P63DDR, and bit ITS11 in ITSR. TEE1 DMACS —...
Page 249 Selection Method and Pin Functions P60/TMRI0/ The pin function is switched as shown below according to the combination of bit DREQ0/IRQ8 P60DDR and bit ITS8 in ITSR. P60DDR Pin function P60 input pin P60 output pin TMRI0 input pin DREQ0 input pin* IRQ8 interrupt input pin* Notes: 1.
Page 250: Port 7
Port 7 5.8.1 Overview Port 7 is a 6-bit I/O port. Port 7 pins also function as DMAC input/output pins (DREQ0, TEND0, DACK0, DREQ1, TEND1, and DACK1) and EXDMAC input/output pins (EDREQ0, ETEND0, EDACK0, EDREQ1, ETEND1, and EDACK1). The functions of pins P75 to P70 change according to the operating mode.
Page 251: Register Configuration
5.8.2 Register Configuration Table 5.13 shows the port 7 register configuration. Table 5.13 Port 7 Registers Name Abbreviation Initial Value Address* Port 7 data direction register P7DDR H'00* H'FE26 Port 7 data register P7DR H'00* H'FF66 Port 7 register PORT7 Undefined H'FF56 Port function control register 2...
Page 252 P7DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 7 Register (PORT7) — — Initial value —* —* —* —* —* —* Undefined Undefined Read/Write — —...
Page 253: Pin Functions
5.8.3 Pin Functions Port 7 pins also function as DMAC input/output pins (DREQ0, TEND0, DACK0, DREQ1, TEND1, and DACK1) and EXDMAC input/output pins (EDREQ0, ETEND0, EDACK0, EDREQ1, ETEND1, and EDACK1). Port 7 pin functions are shown in table 5.14. Table 5.14 Port 7 Pin Functions Selection Method and Pin Functions P75/DACK1/ The pin function is switched as shown below according to the combination of bit...
Page 254 Selection Method and Pin Functions P74/DACK0/ The pin function is switched as shown below according to the combination of bit EDACK0 DMACS in PFCR2, bit SAE0 in DMABCRH, bit AMS in EDMDR0, and bit P74DDR. Modes 1, 2, 4, 5, 6, 7 (EXPE = 1) SAE0 —...
Page 255 Selection Method and Pin Functions P73/TEND1/ The pin function is switched as shown below according to the combination of bit ETEND1 DMACS in PFCR2, bit TEE1 in DMATCR of the DMAC, bit ETENDE in EDMDR1 of the EXDMAC, and bit P73DDR. Modes 1, 2, 4, 5, 6, 7 (EXPE = 1) ETENDE TEE1...
Page 256 Selection Method and Pin Functions P72/TEND0/ The pin function is switched as shown below according to the combination of bit ETEND0 DMACS in PFCR2, bit TEE0 in DMATCR of the DMAC, bit ETENDE in EDMDR0 of the EXDMAC, and bit P72DDR. Modes 1, 2, 4, 5, 6, 7 (EXPE = 1) ETENDE TEE0...
Page 257: Overview
Port 8 5.9.1 Overview Port 8 is a 6-bit I/O port. Port 8 pins also function as interrupt input pins (IRQ0 to IRQ5) and EXDMAC input/output pins (EDREQ2, ETEND2, EDACK2, EDREQ3, ETEND3, and EDACK3). The functions of pins P85 to P80 change according to the operating mode. The interrupt input pins (IRQ0 to IRQ5) can be switched by making a setting in ITSR.
Page 258: Register Configuration
5.9.2 Register Configuration Table 5.15 shows the port 8 register configuration. Table 5.15 Port 8 Registers Name Abbreviation Initial Value Address* Port 8 data direction register P8DDR H'00* H'FE27 Port 8 data register P8DR H'00* H'FF67 Port 8 register PORT8 Undefined H'FF57 Notes: 1.
Page 259: Pin Functions
P8DR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. Port 8 Register (PORT8) — — Initial value —* —* —* —* —* —* Undefined Undefined Read/Write — —...
Page 260 Table 5.16 Port 8 Pin Functions Selection Method and Pin Functions P85/IRQ5/ The pin function is switched as shown below according to the combination of bit EDACK3 AMS in EDMDR3 of the EXDMAC, bit P85DDR, and bit ITS5 in ITSR. Modes 1, 2, 4, 5, 6, 7 (EXPE = 1) P85DDR —...
Page 261 Selection Method and Pin Functions P83/IRQ3/ The pin function is switched as shown below according to the combination of bit ETEND3 ETENDE in EDMDR3 of the EXDMAC, bit P83DDR, and bit ITS3 in ITSR. Modes 1, 2, 4, 5, 6, 7 (EXPE = 1) ETENDE P83DDR —...
Page 262 Selection Method and Pin Functions P81/IRQ1/ The pin function is switched as shown below according to the combination of bit EDREQ3 P81DDR and bit ITS1 in ITSR. P81DDR Pin function P81 input pin P81 output pin EDREQ3 input pin IRQ1 interrupt input* Note: * IRQ1 input when ITS1 = 1.
Page 263: Overview
5.10 Port A 5.10.1 Overview Port A is an 8-bit I/O port. Port A pins also function as address bus outputs. The pin functions change according to the operating mode. Address output or port output can be selected with bits A23E to A16E in PFCR1.
Page 264: Register Configuration
5.10.2 Register Configuration Table 5.17 shows the port A register configuration. Table 5.17 Port A Registers Name Abbreviation Initial Value Address* Port A data direction register PADDR H'00 H'FE29 Port A data register PADR H'00 H'FF69 Port A register PORTA Undefined H'FF59 Port A MOS pull-up control register...
Page 265 • Mode 4 When the corresponding bit of A23E to A16E is set to 1, setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port.
Page 266 After a reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its prior state in software standby mode. Port A MOS Pull-Up Control Register (PAPCR) PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value Read/Write PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function...
Page 267 PFCR1 is an 8-bit readable/writable register that performs I/O port control. All the bits are valid in modes 4 and 7, and bits 7 to 5 are valid in modes 1, 2, 5, and 6. PFCR1 is initialized to H'FF by a reset and in hardware standby mode.
Page 268 Bit 2—Address 18 Enable (A18E): Enables or disables output for address output 18 (A18). Valid only in modes 4 and 7. Bit 2 A18E Description DR output when PA2DDR = 1 A18 output when PA2DDR = 1 (Initial value) Bit 1—Address 17 Enable (A17E): Enables or disables output for address output 17 (A17). Valid only in modes 4 and 7.
Page 269: Pin Functions
5.10.3 Pin Functions Port A pins also function as address outputs. Port A pin functions are shown in table 5.18. Table 5.18 Port A Pin Functions Selection Method and Pin Functions PA7/A23 The pin function is switched as shown below according to the operating mode, bit EXPE, bits A23E to A21E, and bit PADDR.
Page 270 5.10.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used by pins PA7 to PA5 in modes 1, 2, 5, and 6, and by all pins in modes 4 and 7.
Page 271 5.11 Port B 5.11.1 Overview Port B is an 8-bit I/O port. Port B pins also function as address bus outputs. The pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 5.10 shows the port B pin configuration.
Page 272: Register Configuration
5.11.2 Register Configuration Table 5.20 shows the port B register configuration. Table 5.20 Port B Registers Name Abbreviation Initial Value Address* Port B data direction register PBDDR H'00 H'FE2A Port B data register PBDR H'00 H'FF6A Port B register PORTB Undefined H'FF5A Port B MOS pull-up control register...
Page 273 Port B Data Register (PBDR) PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value Read/Write PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode.
Page 274: Pin Functions
In modes 4 and 7, when a PBDDR bit is cleared to 0 (input port setting), setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PBPCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode.
Page 275 5.11.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 276 5.12 Port C 5.12.1 Overview Port C is an 8-bit I/O port. Port C pins also function as address bus outputs. The pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 5.11 shows the port C pin configuration.
Page 277 5.12.2 Register Configuration Table 5.23 shows the port C register configuration. Table 5.23 Port C Registers Name Abbreviation Initial Value Address* Port C data direction register PCDDR H'00 H'FE2B Port C data register PCDR H'00 H'FF6B Port C register PORTC Undefined H'FF5B Port C MOS pull-up control register...
Page 278 Port C Data Register (PCDR) PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR Initial value Read/Write PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode.
Page 279: Pin Functions
In modes 4 and 7, when a PCDDR bit is cleared to 0 (input port setting), setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PCPCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode.
Page 280 5.12.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 and 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 281 5.13 Port D 5.13.1 Overview Port D is an 8-bit I/O port. Port D pins also function as data bus input/output pins. The pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 5.12 shows the port D pin configuration.
Page 282: Register Configuration
5.13.2 Register Configuration Table 5.26 shows the port D register configuration. Table 5.26 Port D Registers Name Abbreviation Initial Value Address* Port D data direction register PDDDR H'00 H'FE2C Port D data register PDDR H'00 H'FF6C Port D register PORTD Undefined H'FF5C Port D MOS pull-up control register...
Page 283 Port D Data Register (PDDR) PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR Initial value Read/Write PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode.
Page 284 In mode 7, when a PDDDR bit is cleared to 0 (input port setting), setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode.
Page 285 5.13.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 286: Overview
5.14 Port E 5.14.1 Overview Port E is an 8-bit I/O port. Port E pins also function as data bus input/output pins. The pin functions change according to the operating mode and the bus mode (8-bit or 16-bit). Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 5.13 shows the port E pin configuration.
Page 287: Register Configuration
5.14.2 Register Configuration Table 5.29 shows the port E register configuration. Table 5.29 Port E Registers Name Abbreviation Initial Value Address* Port E data direction register PEDDR H'00 H'FE2D Port E data register PEDR H'00 H'FF6D Port E register PORTE Undefined H'FF5D Port E MOS pull-up control register...
Page 288 Port E Data Register (PEDR) PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial value Read/Write PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode.
Page 289: Pin Functions
PEPCR is initialized to H'00 by a reset and in hardware standby mode. It retains its prior state in software standby mode. 5.14.3 Pin Functions Port E pins also function as data input/output pins. Port E pin functions are shown in table 5.30. Table 5.30 Port E Pin Functions Selection Method and Pin Functions PE7/D7...
Page 290 5.14.4 MOS Input Pull-Up Function Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in 8-bit bus mode. MOS input pull-up can be specified as on or off on a bit-by-bit basis.
Page 291: Overview
5.15 Port F 5.15.1 Overview Port F is an 8-bit I/O port. Port F pins also function as interrupt input pins (IRQ14 and IRQ15), bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, UCAS, and WAIT), and the system clock (ø) output pin. The AS and LWR output pins can be switched by making a setting in PFCR2.
Page 292 5.15.2 Register Configuration Table 5.32 shows the port F register configuration. Table 5.32 Port F Registers Name Abbreviation Initial Value Address* Port F data direction register PFDDR H'80/H'00* H'FE2E Port F data register PFDR H'00 H'FF6E Port F register PORTF Undefined H'FF5E Port function control register 2...
Page 293 Pin PF3 functions as the LWR output pin when LWROE is set to 1. When LWROE is cleared to 0, pin PF3 is an I/O port and its function can be switched with PF3DDR. Pins PF2 to PF0 function as bus control input/output pins (LCAS, UCAS, and WAIT) when the appropriate bus controller settings are made.
Page 294 Port F Register (PORTF) Initial value —* —* —* —* —* —* —* —* Read/Write Note: * Determined by the state of pins PF7 to PF0. PORTF is an 8-bit read-only register that shows the pin states. PORTF cannot be written to; writing of output data for the port F pins (PF7 to PF0) must always be performed on PFDR.
Page 295 Bit 2—LWR Output Enable (LWROE): Enables or disables LWR output. Bit 2 LWROE Description PF3 is designated as I/O port and does not function as LWR output pin PF3 is designated as LWR output pin (Initial value) Bit 1—OE Output Select (OES): Selects the OE output pin port when the OEE bit is set to 1 in DRAMCR (enabling OE output).
Page 296 Table 5.33 Port F Pin Functions Selection Method and Pin Functions PF7/ø The pin function is switched as shown below according to bit PF7DDR. Operating 1, 2, 4, 5, 6, 7 mode PFDDR Pin function PF7 input pin ø output pin PF6/AS The pin function is switched as shown below according to the operating mode, bit EXPE, bit PF6DDR, and bit ASOE.
Page 297 Selection Method and Pin Functions PF3/LWR The pin function is switched as shown below according to the operating mode, bit EXPE, bit PF3DDR, and bit LWROE. Operating 1, 2, 4, 5, 6 mode EXPE — LWROD — PF3DDR — — Pin function output input...
Page 298 Selection Method and Pin Functions PF1/UCAS/ The pin function is switched as shown below according to the combination of the IRQ14 operating mode, bit EXPE, bits RMTS2 to RMTS0 in DRAMCR, and bit PF1DDR. Operating 1, 2, 4, 5, 6 mode EXPE —...
Page 299: Overview
5.16 Port G 5.16.1 Overview Port G is a 7-bit I/O port. Port G pins also function as bus control signal output pins (BREQ, BACK, BREQO, and CS3 to CS0). CS3 to CS0 output can be enabled or disabled by making a setting in PFCR0.
Page 300 Port G Data Direction Register (PGDDR) — PG6DDR PG5DDR PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR Modes 1, 2, 5, 6 Initial value Read/Write — Modes 4 and 7 Initial value Read/Write — PGDDR is a 7-bit write-only register, the individual bits of which specify input or output for the pins of port G.
Page 301 Port G Data Register (PGDR) — PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR Initial value Read/Write — PGDR is a 7-bit readable/writable register that stores output data for the port G pins (PG6 to PG0). Bit 7 is reserved; it is always read as 0, and cannot be modified. PGDR is initialized to H'00 by a reset and in hardware standby mode.
Page 302 Bits 7 to 0—CS7 to CS0 Enable (CS7E to CS0E): These bits enable or disable the corresponding CSn output. Bit n CSnE Description Pin is designated as I/O port and does not function as CSn output pin Pin is designated as CSn output pin (Initial value) (n = 7 to 0) 5.16.3...
Page 303 Selection Method and Pin Functions PG4/BREQO The pin function is switched as shown below according to the operating mode, bit EXPE, bit BRLE, bit BREQOE, and bit PG4DDR. Operating 1, 2, 4, 5, 6 mode EXPE — BRLE — BREQOE —...
Page 304 5.17 Port H 5.17.1 Overview Port H is a 4-bit I/O port. Port H pins also function as bus control signal output pins (CS7 to CS4 and OE) and interrupt signal input pins (IRQ7 and IRQ6). Figure 5.16 shows the port H pin configuration. Port H pins Pin functions in modes 1, 2, 4, 5, 6, and 7 PH3 / CS7 / OE / IRQ7...
Page 305 Port H Data Direction Register (PHDDR) — — — — PH3DDR PH2DDR PH1DDR PH0DDR Initial value Read/Write — — — — PHDDR is a 4-bit write-only register, the individual bits of which specify input or output for the pins of port H. PHDDR cannot be read; if it is, an undefined value will be read. PHDDR is initialized to H'00 by a reset and in hardware standby mode.
Page 306 Port H Data Register (PHDR) — — — — PH3DR PH2DR PH1DR PH0DR Initial value Read/Write — — — — PHDR is a 4-bit readable/writable register that stores output data for the port H pins (PH3 to PH0). Bits 7 to 4 are reserved; they are always read as 0 and cannot be modified. PHDR is initialized to H'00 by a reset and in hardware standby mode.
Page 307: Pin Functions
Bits 7 to 0—CS7 to CS0 Enable (CS7E to CS0E): These bits enable or disable the corresponding CSn output. Bit n CSnE Description Pin is designated as I/O port and does not function as CSn output pin Pin is designated as CSn output pin (Initial value) (n = 7 to 0) Port Function Control Register 2 (PFCR2)
Page 308 Table 5.37 Port H Pin Functions Selection Method and Pin Functions PH3/CS7/ The pin function is switched as shown below according to the operating mode, bit OE/IRQ7 EXPE, bit OEE, bit OES, bit CS7E, and bit PH3DDR. Operating 1, 2, 4, 5, 6 mode EXPE —...
Page 309: Pin Functions
5.18 Pin Functions 5.18.1 Port States in Each Processing State Table 5.38 I/O Port States in Each Processing State Hardware Program Port Name Operating Standby Software Bus-Released Execution State Pin Name Mode Reset Mode Standby Mode State Sleep Mode Port 1 1, 2, 4 to 7 keep keep...
Page 310 Hardware Program Port Name Operating Standby Software Bus-Released Execution State Pin Name Mode Reset Mode Standby Mode State Sleep Mode PA7/A23 1, 2, 4 to 7 [Address output, OPE = 0] [Address output] [Address output] A23 to A21 PA6/A22 [Address output, OPE = 1] [Otherwise] [Otherwise] PA5/A21...
Page 311 Hardware Program Port Name Operating Standby Software Bus-Released Execution State Pin Name Mode Reset Mode Standby Mode State Sleep Mode Port C 1, 2, 5, 6 [OPE = 0] Address output A7 to A0 [OPE = 1] keep [Address output, OPE = 0] [Address output] [Address output] A7 to A0...
Page 312 Hardware Program Port Name Operating Standby Software Bus-Released Execution State Pin Name Mode Reset Mode Standby Mode State Sleep Mode RD, HWR PF5/RD 1, 2, 4 to 6 [OPE = 0] PF4/HWR [OPE = 1] [RD, HWR output, [RD, HWR [RD, HWR output] OPE = 0]...
Page 313 Hardware Program Port Name Operating Standby Software Bus-Released Execution State Pin Name Mode Reset Mode Standby Mode State Sleep Mode BREQO output PG4/ 1, 2, 4 to 7 [BREQO output] [BREQO output] BREQO BREQO BREQO BREQO [Otherwise] [Otherwise] [Otherwise] keep keep I/O port PG3/CS3...
Page 314: I/O Port Block Diagrams
5.19 I/O Port Block Diagrams 5.19.1 Port 1 Reset P1nDDR WDDR1 Reset P1nDR PPG module WDR1 Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ RDR1 PWM output RPOR1 Input capture input WDDR1: Write to P1DDR WDR1: Write to P1DR RPOR1: Read port 1...
Page 315 Reset P1nDDR WDDR1 Reset P1nDR PPG module WDR1 Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ RDR1 PWM output RPOR1 Input capture input External clock input WDDR1: Write to P1DDR WDR1: Write to P1DR RPOR1: Read port 1 RDR1: Read P1DR...
Page 316 Reset P16DDR Modes 1, 2, 4, 5, 6 WDDR1 Mode 7 Reset P16DR PPG module WDR1 Pulse output enable Pulse output System controller EXPE EXDMAC module EDREQ acknowledge enable EDREQ acknowledge output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1...
Page 317 Reset P17DDR Modes 1, 2, 4, 5, 6 WDDR1 Mode 7 Reset P17DR PPG module WDR1 Pulse output enable Pulse output System controller EXPE EXDMAC module EDREQ acknowledge enable EDREQ acknowledge output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1...
Page 318: Port 2
5.19.2 Port 2 Reset P2nDDR WDDR2 Reset P2nDR PPG module WDR2 Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ RDR2 PWM output RPOR2 Input capture input Interrupt controller ITSm IRQmB WDDR2: Write to P2DDR WDR2: Write to P2DR RPOR2: Read port 2...
Page 319 Reset P2nDDR Modes 1, 2, 4, 5, 6 WDDR2 Mode 7 Reset P2nDR PPG module WDR2 Pulse output enable Pulse output System controller EXPE EXDMAC module EDREQ acknowledge enable EDREQ acknowledge output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2...
Page 320: Port 3
5.19.3 Port 3 Reset P3nDDR WDDR3 Reset P3nDR WDR3 Reset P3nODR WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 RPOR3 WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RPOR3: Read port 3 RDR3: Read P3DR RODR3: Read P3ODR n = 0 or 1...
Page 321 Reset P3nDDR WDDR3 Reset P3nDR WDR3 Reset P3nODR WODR3 RODR3 SCI module Serial receive data enable RDR3 RPOR3 Serial receive data WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RPOR3: Read port 3 RDR3: Read P3DR RODR3: Read P3ODR n = 2 or 3 Notes: 1.
Page 322 Reset P34DDR WDDR3 Reset P34DR WDR3 Reset P34ODR WODR3 RODR3 SCI module Serial clock output enable Serial clock output Serial clock input enable RDR3 RPOR3 Serial clock input WDDR3: Write to P3DDR WDR3: Write to P3DR WODR3: Write to P3ODR RPOR3: Read port 3 RDR3: Read P3DR...
Page 323 Reset P35DDR Modes 1, 2, 4, 5, 6 WDDR3 System controller Mode 7 EXPE Reset P35DR Bus controller WDR3 Reset PFCR2 WPFCR2 RPFCR2 Reset P35ODR WODR3 RPOR3 SCI module Serial clock output enable Serial clock output Serial clock input enable RDR3 RPOR3 Serial clock input...
Page 324: Port 4
5.19.4 Port 4 RPOR4 A/D converter module Analog input RPOR4: Read port 4 n = 0 to 5 Figure 5.27 Port 4 Block Diagram (a) (Pins P40 to P45) RPOR4 A/D converter module Analog input D/A converter module Output enable Analog output RPOR4: Read port 4 n = 6 or 7...
Page 325: Port 5
5.19.5 Port 5 Reset P50DDR WDDR5 Reset P50DR WDR5 SCI module Serial transmit enable Serial transmit data RDR5 RPOR5 Interrupt controller ITS0 IRQ0 WDDR5: Write to P5DDR WDR5: Write to P5DR RPOR5: Read port 5 RDR5: Read P5DR Note: * Output enable signal Priority order: SCI >...
Page 326 Reset P51DDR WDDR5 Reset P51DDR SCI module WDR5 Serial receive data enable RDR5 RPOR5 Serial receive data Interrupt controller ITS0 IRQ1 WDDR5: Write to P5DDR WDR5: Write to P5DR RPOR5: Read port 5 RDR5: Read P5DR Note: * Output enable signal Figure 5.30 Port 5 Block Diagram (b) (Pin P51)
Page 327 Reset P52DDR WDDR5 Reset P52DR SCI module WDR5 Serial clock output enable Serial clock output Serial clock input enable RDR5 RPOR5 Serial clock input Interrupt controller ITS2 IRQ2 WDDR5: Write to P5DDR WDR5: Write to P5DR RPOR5: Read port 5 RDR5: Read P5DR Note: * Output enable signal...
Page 328 Reset P53DDR WDDR5 Reset P53DR WDR5 RDR5 RPOR5 A/D converter A/D conversion external trigger input Interrupt controller ITS3 IRQ3 WDDR5: Write to P5DDR WDR5: Write to P5DR RPOR5: Read port 5 RDR5: Read P5DR Note: * Output enable signal Figure 5.32 Port 5 Block Diagram (d) (Pin P53)
Page 329 RPOR5 Interrupt controller ITSn IRQn A/D converter module Analog input RPOR5: Read port 5 n = 4 or 5 Figure 5.33 Port 5 Block Diagram (e) (Pins P54 and P55) RPOR5 Interrupt controller ITSn IRQn A/D converter module Analog input D/A converter module Output enable Analog output...
Page 330: Port 6
5.19.6 Port 6 Reset P6nDDR WDDR6 Reset P6nDR WDR6 RDR6 RPOR6 DMA controller DMA request input 8-bit timer module Counter external reset input Interrupt controller ITSm IRQm WDDR6: Write to P6DDR WDR6: Write to P6DR RPOR6: Read port 6 RDR6: Read P6DR n = 0 or 1 m = 8 or 9...
Page 331 Reset P6nDDR WDDR6 Reset P6nDR WDR6 Reset PFCR2 DMACS WPFCR2 RPFCR2 DMA controller DMA transfer end enable DMA transfer end RDR6 RPOR6 8-bit timer module Counter external clock input Interrupt controller ITSm IRQm WDDR6: Write to P6DDR Note: * Output enable signal WDR6: Write to P6DR Priority order: DMACS = 0...
Page 332 Reset P6nDDR WDDR6 Reset P6nDR WDR6 Reset PFCR2 DMACS WPFCR2 RPFCR2 DMA controller DMA transfer acknowledge enable DMA transfer acknowledge 8-bit timer module Compare match output enable Compare match output RDR6 RPOR6 Interrupt controller ITSm IRQm WDDR6: Write to P6DDR Note: * Output enable signal WDR6: Write to P6DR...
Page 333: Port 7
5.19.7 Port 7 Reset P7nDDR WDDR7 Reset P7nDR WDR7 RDR7 RPOR7 DMA controller DMA request input EXDMA controller EXDMA request input WDDR7: Write to P7DDR WDR7: Write to P7DR RPOR7: Read port 7 RDR7: Read P7DR n = 0 or 1 Note: * Output enable signal Figure 5.38 Port 7 Block Diagram (a) (Pins P70 and P71)
Page 334 Reset P7nDDR Modes 1, 2, 4, 5, 6 WDDR7 Mode 7 Reset P7nDR WDR7 Reset PFCR2 DMACS WPFCR2 RPFCR2 DMA controller DMA transfer end enable DMA transfer end System controller EXPE EXDMA controller EXDMA transfer end enable EXDMA transfer end RDR7 RPOR7 WDDR7:...
Page 335 Reset P7nDDR Modes 1, 2, 4, 5, 6 WDDR7 Mode 7 Reset P7nDR WDR7 Reset PFCR2 DMACS WPFCR2 RPFCR2 DMA controller DMA transfer acknowledge enable DMA transfer acknowledge System controller EXPE EXDMA controller EXDMA transfer acknowledge enable EXDMA transfer acknowledge RDR7 RPOR7 WDDR7:...
Page 336: Port 8
5.19.8 Port 8 Reset P8nDDR WDDR8 Reset P8nDR WDR8 RDR8 RPOR8 EXDMA controller EXDMA request input Interrupt controller ITSn IRQn WDDR8: Write to P8DDR WDR8: Write to P8DR RPOR8: Read port 8 RDR8: Read P8DR n = 0 or 1 Note: * Output enable signal Figure 5.41 Port 8 Block Diagram (a) (Pins P80 and P81)
Page 337 Reset Modes 1, 2, 4, 5, 6 P8nDDR Mode 7 WDDR8 Reset P8nDR System controller WDR8 EXPE EXDMA controller EXDMA transfer end enable EXDMA transfer end RDR8 RPOR8 Interrupt controller ITSn IRQn WDDR8: Write to P8DDR Note: * Output enable signal WDR8: Write to P8DR Priority order: Modes 1, 2, 4, 5, 6, 7 (EXPE = 1)
Page 338 Reset Modes 1, 2, 4, 5, 6 P8nDDR Mode 7 WDDR8 Reset P8nDR System controller WDR8 EXPE EXDMA controller EXDMA transfer acknowledge EXDMA transfer acknowledge enable RDR8 RPOR8 Interrupt controller ITSn IRQn WDDR8: Write to P8DDR Note: * Output enable signal WDR8: Write to P8DR Priority order: Modes 1, 2, 4, 5, 6, 7 (EXPE = 1)
Page 339: Port A
5.19.9 Port A Reset PAnPCR Mode 4 Mode 7 WPCRA RPCRA PFCR1 WPFCR1 RPFCR1 Reset PAnDDR Modes 1, 2, 5, 6 System controller WDDRA EXPE Mode 4 Reset Mode 7 PAnDR Modes 1, 2, 5, 6 WDRA Reset PAnODR WODRA RODRA RDRA RPORA...
Page 340 Reset PAnPCR WPCRA RPCRA PFCR1 WPFCR1 RPFCR1 Reset PAnDDR Modes WDDRA 1, 2, 4, 5, 6 Reset Mode 7 PAnDR WDRA Reset PAnODR WODRA RODRA System controller EXPE RDRA RPORA WDDRA: Write to PADDR RPORA: Read port A WDRA: Write to PADR RDRA: Read PADR WODRA: Write to PAODR...
Page 341: 5.19.10 Port B
5.19.10 Port B Reset PBnPCR Mode 4 Mode 7 WPCRB RPCRB Reset Modes PBnDDR 1, 2, 5, 6 WDDRB Reset PBnDR WDRB Mode 4 Mode 7 System controller EXPE RDRB RPORB WDDRB: Write to PBDDR WDRB: Write to PBDR WPCRB: Write to PBPCR RPORB: Read port B RDRB: Read PBDR...
Page 342: 5.19.11 Port C
5.19.11 Port C Reset PCnPCR Mode 4 Mode 7 WPCRC RPCRC Reset PCnDDR Modes 1, 2, 5, 6 WDDRC Reset PCnDR Mode 4 WDRC Mode 7 System controller EXPE RDRC RPORC WDDRC: Write to PCDDR WDRC: Write to PCDR WPCRC: Write to PCPCR RPORC: Read port C RDRC: Read PCDR...
Page 343: 5.19.12 Port D
5.19.12 Port D Reset Mode 7 PDnPCR WPCRD RPCRD Reset PDnDDR WDDRD Reset Modes PDnDR 1, 2, 4, 5, 6 Mode 7 System controller WDRD EXPE External data upper write RDRD External data lower write RPORD External data upper read External data lower read WDDRD: Write to PDDDR...
Page 344: 5.19.13 Port E
5.19.13 Port E Reset PEnPCR All areas 8-bit access space Mode 7 WPCRE RPCRE Reset External PEnDDR data write WDDRE Reset All areas 8-bit access space PEnDR Modes 1, 2, 4, 5, 6 WDRE System controller Mode 7 EXPE RDRE RPORE WDDRE: Write to PEDDR External data...
Page 345: 5.19.14 Port F
5.19.14 Port F Reset Modes 1, 2, 4, 5, 6 PF0DDR WDDRF Mode 7 System controller EXPE Reset PF0DR WDRF RDRF RPORF Bus controller WAITE WAIT input WDDRF: Write to PFDDR WDRF: Write to PFDR RPORF: Read port F RDRF: Read PFDR Note: * Output enable signal Figure 5.50 Port F Block Diagram (a) (Pin PF0)
Page 346 Reset PF1DDR WDDRF DRAM space Reset Modes PF1DR 1, 2, 4, 5, 6 System controller Mode 7 WDRF EXPE Bus controller UCAS output RDRF RPORF Interrupt controller ITS14 IRQ14 input WDDRF: Write to PFDDR WDRF: Write to PFDR RPORF: Read port F RDRF: Read PFDR Note: * Output enable signal...
Page 347 Reset PF2DDR WDDRF Any DRAM space area is 16-bit access space Reset Modes PF2DR 1, 2, 4, 5, 6 System controller Mode 7 WDRF EXPE Bus controller LCAS output RDRF RPORF Interrupt controller ITS15 IRQ15 input WDDRF: Write to PFDDR WDRF: Write to PFDR RPORF: Read port F...
Page 348 PFCR2 LWROE WPFCR2 RPFCR2 Reset PF3DDR WDDRF Reset PF3DR System controller WDRF EXPE Modes 1, 2, 4, 5, 6 Bus controller Mode 7 LWR output RDRF RPORF WDDRF: Write to PFDDR WDRF: Write to PFDR WPFCR2: Write to PFCR2 RPORF: Read port F RDRF: Read PFDR...
Page 349 Reset Modes 1, 2, 4, 5, 6 Mode 7 PF4DDR WDDRF Reset Mode 7 PF4DR Modes 1, 2, 4, 5, 6 Mode 7 WDRF System controller EXPE Bus controller HWR output RDRF RPORF WDDRF: Write to PFDDR WDRF: Write to PFDR RPORF: Read port F RDRF: Read PFDR...
Page 350 Reset Modes 1, 2, 4, 5, 6 Mode 7 PF5DDR WDDRF Reset Mode 7 PF5DR Modes 1, 2, 4, 5, 6 Mode 7 WDRF System controller EXPE Bus controller RD output RDRF RPORF WDDRF: Write to PFDDR WDRF: Write to PFDR RPORF: Read port F RDRF: Read PFDR...
Page 351 PFCR2 ASOE WPFCR2 RPFCR2 Reset PF6DDR WDDRF Reset PF6DR System controller WDRF EXPE Modes 1, 2, 4, 5, 6 Bus controller Mode 7 AS output RDRF RPORF WDDRF: Write to PFDDR WDRF: Write to PFDR WPFCR2: Write to PFCR2 RPORF: Read port F RDRF: Read PFDR...
Page 352 Modes Mode 1, 2, 4, 5, 6 Reset PF7DDR WDDRF Reset PF7DR WDRF ø RDRF RPORF WDDRF: Write to PFDDR WDRF: Write to PFDR RPORF: Read port F RDRF: Read PFDR Note: * Output enable signal Figure 5.57 Port F Block Diagram (h) (Pin PF7)
Page 353: 5.19.15 Port G
5.19.15 Port G Modes 1, 2, 5, 6 Modes 4, 7 Reset PG0DDR WDDRG PFCR0 CS0E WPFCR0 RPFCR0 Reset PG0DR Modes 1, 2, 4, 5, 6 WDRG System controller Mode 7 EXPE Bus controller RDRG RPORG WDDRG: Write to PGDDR WDRG: Write to PGDR WPFCR0: Write to PFCR0...
Page 354 Reset PG0DDR WDDRG PFCR0 CSnE WPFCR0 RPFCR0 Reset PGnDR Modes 1, 2, 4, 5, 6 WDRG System controller Mode 7 EXPE Bus controller RDRG RPORG WDDRG: Write to PGDDR WDRG: Write to PGDR WPFCR0: Write to PFCR0 RPORG: Read port G RDRG: Read PGDR RPFCR0: Read PFCR0...
Page 355 Reset PG4DDR WDDRG Reset PG4DR Modes 1, 2, 4, 5, 6 System controller Mode 7 WDRG EXPE Bus controller BRLE BREQOE BREQO RDRG RPORG WDDRG: Write to PGDDR WDRG: Write to PGDR RPORG: Read port G RDRG: Read PGDR Note: * Output enable signal Figure 5.60 Port G Block Diagram (c) (Pin PG4)
Page 356 Reset PG5DDR WDDRG Reset PG5DR Modes 1, 2, 4, 5, 6 System controller Mode 7 WDRG EXPE Bus controller BRLE BACK RDRG RPORG WDDRG: Write to PGDDR WDRG: Write to PGDR RPORG: Read port G RDRG: Read PGDR Note: * Output enable signal Figure 5.61 Port G Block Diagram (d) (Pin PG5)
Page 357 Reset Modes 1, 2, 4, 5, 6 PG6DDR WDDRG Mode 7 System controller EXPE Reset PG6DR WDRG RDRG RPORG Bus controller BRLE BREQ input WDDRG: Write to PGDDR WDRG: Write to PGDR RPORG: Read port G RDRG: Read PGDR Note: * Output enable signal Figure 5.62 Port G Block Diagram (e) (Pin PG6)
Page 358: 5.19.16 Port H
5.19.16 Port H Reset PHnDDR WDDRH PFCR0 CSmE WPFCR0 RPFCR0 Reset PHnDR Modes 1, 2, 4, 5, 6 System controller Mode 7 WDRH EXPE Bus controller RDRH RPORH WDDRH: Write to PHDDR WDRH: Write to PHDR WPFCR0: Write to PFCR0 RPORH: Read port H RDRH:...
Page 359 Reset PH2DDR WDDRH PFCR0 CS6E WPFCR0 RPFCR0 Reset PH2DR Modes 1, 2, 4, 5, 6 System controller Mode 7 WDRH EXPE Bus controller RDRH RPORH Interrupt controller ITS6 IRQ6 input WDDRH: Write to PHDDR WDRH: Write to PHDR WPFCR0: Write to PFCR0 RPORH: Read port H RDRH:...
Page 360 Reset Modes 1, 2, 4, 5, 6 PH3DR WDRH Mode 7 PFCR0 CS7E WPFCR0 RPFCR0 Reset System controller Modes PH3DR 1, 2, 4, 5, 6 EXPE WDRH Bus controller Mode 7 PFCR2 WPFCR2 RPFCR2 RDRH RPORH Interrupt controller ITS7 IRQ7 input WDDRH: Write to PHDDR WDRH: Write to PHDR...
Page 362: Section 6 Supporting Module Block Diagrams
Section 6 Supporting Module Block Diagrams Interrupt Controller 6.1.1 Features • Selection of two interrupt control modes • Eight priority levels can be set for each module with IPR • Independent vector addresses • 17 external interrupt pins (NMI, IRQ15 to IRQ0) •...
Page 363: Pins
6.1.3 Pins Table 6.1 Interrupt Controller Pins Name Abbreviation Function Nonmaskable interrupt Input Nonmaskable external interrupt; rising or falling edge can be selected IRQ15 to IRQ0 External interrupt requests 15 to 0 Input Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected DMA Controller 6.2.1...
Page 364: Block Diagram
6.2.2 Block Diagram Internal address bus Internal interrupts TGI0A Address buffer TGI1A TGI2A Processor TGI3A TGI4A TGI5A MAR0A TXI0 IOAR0A RXI0 Control logic TXI1 ETCR0A RXI1 MAR0B External pins IOAR0B DREQ0 ETCR0B DREQ1 DMAWER TEND0 MAR1A DMATCR TEND1 IOAR1A DMACR0A DACK0 DACK1 ETCR1A...
Page 365: Pins
6.2.3 Pins Table 6.2 DMAC Pins Channel Name Abbreviation Function DREQ0 DMA request 0 Input DMAC channel 0 external request DACK0 DMA transfer Output DMAC channel 0 single address acknowledge 0 transfer acknowledge TEND0 DMA transfer end 0 Output DMAC channel 0 transfer end DREQ1 DMA request 1 Input...
Page 366: Block Diagram
6.3.2 Block Diagram DTC register information is located in on-chip RAM*. As the DTC and on-chip RAM (1-kbyte) are connected by a 32-bit bus, a 32-bit read or write of DTC register information can be executed in one state. Note: * When the DTC is used, the RAME bit must be set to 1 in SYSCR. Internal address bus Interrupt controller On-chip RAM...
Page 367: Exdma Controller (Exdmac)
EXDMA Controller (EXDMAC) 6.4.1 Features • Four channels • Physical address space (16-Mbyte flat external space) • Byte or word transfer data length can be selected • Maximum number of transfers: 16M (16,777,215)/infinite (free-running) • Selection of dual address mode or single address mode •...
Page 368: Block Diagram
6.4.2 Block Diagram Bus controller Data buffer Address buffer External pins EDREQn Processor EDRAKn Control logic ETENDn EDSARn EDACKn EDDARn Interrupt request signals to CPU for EDMDRn individual channels EDTCRn EDACRn Internal data bus Legend EDSARn: EXDMA source address register EDDARn: EXDMA destination address register EDTCRn: EXDMA transfer count register EDMDRn: EXDMA mode control register...
Page 369: Pins
6.4.3 Pins Table 6.3 EXDMAC Pins Channel Name Abbreviation Function EDREQ0 EXDMA transfer Input EXDMAC channel 0 external request request 0 EDACK0 EXDMA transfer Output EXDMAC channel 0 single address acknowledge 0 transfer acknowledge ETEND0 EXDMA transfer Output EXDMAC channel 0 transfer end end 0 EDREQ0 EDRAK0...
Page 370: 16-Bit Timer Pulse Unit
16-bit Timer Pulse Unit 6.5.1 Features • Six 16-bit timer channels • Maximum 16 pulse inputs/outputs • Selection of 8 counter input clocks for each channel • Compare match, input capture, counter clear operation, synchronous operation, and PWM mode can be set for each channel •...
Page 371: Block Diagram
6.5.2 Block Diagram [Interrupt request signals] Channel 3: TGI3A [Input/output pins] TGI3B Channel 3: TIOCA3 TGI3C TIOCB3 TGI3D TIOCC3 TCI3V TIOCD3 Channel 4: TGI4A Channel 4: TIOCA4 TGI4B TIOCB4 TCI4V Channel 5: TIOCA5 TCI4U TIOCB5 Channel 5: TGI5A TGI5B TCI5V TCI5U [Clock input] Internal clock:...
Page 372: Pins
6.5.3 Pins Table 6.4 TPU Pins Abbre- Channel Name viation Function Clock input A TCLKA Input External clock A input pin (Channel 1 and 5 phase counting mode A-phase input) Clock input B TCLKB Input External clock B input pin (Channel 1 and 5 phase counting mode B-phase input) Clock input C...
Page 373: Programmable Pulse Generator
Abbre- Channel Name viation Function Input capture/out compare TIOCA4 TGR4A input capture input/output match A4 compare output/PWM output pin Input capture/out compare TIOCB4 TGR4B input capture input/output match B4 compare output/PWM output pin Input capture/out compare TIOCA5 TGR5A input capture input/output match A5 compare output/PWM output pin Input capture/out compare...
Page 374 6.6.2 Block Diagram Compare match signals NDERH NDERL Control logic PO15 Pulse output PO14 pins, group 3 PO13 PO12 NDRH PODRH PO11 Pulse output PO10 pins, group 2 Pulse output pins, group 1 PODRL NDRL Pulse output pins, group 0 Legend PMR: PPG output mode register...
Page 375: 8-Bit Timer
6.6.3 Pins Table 6.5 PPG Pins Name Abbreviation Function Pulse output 0 Output Group 0 pulse output Pulse output 1 Output Pulse output 2 Output Pulse output 3 Output Pulse output 4 Output Group 1 pulse output Pulse output 5 Output Pulse output 6 Output...
Page 376 6.7.2 Block Diagram External clocks Internal clocks TMCI0 ø/8 TMCI1 ø/64 ø/8192 Clock 1 Clock 0 Clock selection TCORA0 TCORA1 Compare match A1 Comparator A0 Comparator A1 Compare match A0 Overflow 1 TMO0 TCNT0 TCNT1 Overflow 01 TMRI0 Clear 0 Clear 1 Compare match B1 Compare match B0...
Page 377: Features
6.7.3 Pins Table 6.6 8-Bit Timer Pins Channel Name AbbreviationI/O Function Timer output pin 0 TMO0 Output Compare match output Timer clock input pin 0 TMCI0 Input Counter external clock input Timer reset input pin 0 TMRI0 Input Counter external reset input Timer output pin 1 TMO1 Output...
Page 378: Block Diagram
6.8.2 Block Diagram ø/2 Overflow Interrupt ø/64 WOVI control ø/128 (interrupt request ø/512 signal) Clock Clock selection ø/2048 ø/8192 ø/32768 WDTOVF * Reset ø/131072 control Internal reset Internal clocks signal RSTCSR TCNT TSCR interface Module bus Legend TCSR: Timer control/status register TCNT: Timer counter RSTCSR: Reset control/status register...
Page 379: Features
Serial Communication Interface 6.9.1 Features • Three independent on-chip channels in the H8S/2678 Series • Selection of synchronous or asynchronous serial communication mode • Full-duplex communication capability • Selection of LSB-first or MSB-first transfer • Built-in baud rate generator allows any bit rate to be selected •...
Page 380: Pins
6.9.3 Pins Table 6.8 SCI Pins Channel Name Abbreviation Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output Serial clock pin 1 SCK1 SCI1 clock input/output Receive data pin 1...
Page 381: Smart Card Interface
6.10 Smart Card Interface 6.10.1 Features • IC card (smart card) interface conforming to ISO/IEC7816-3 supported as SCI extension function • Switching between normal SCI and smart card interface by means of register setting • Built-in baud rate generator allows any bit rate to be selected •...
Page 382: Features
6.10.3 Pins Table 6.9 Smart Card Interface Pins Channel Name Abbreviation Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0 Input SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output Serial clock pin 1 SCK1 SCI1 clock input/output...
Page 383: Block Diagram
6.11.2 Block Diagram IrDA SCI0 Pulse encoder TxD0/IrTxD Pulse decoder RxD0/IrRxD IrCR Figure 6.11 Block Diagram of IrDA 6.11.3 Pins Table 6.10 IrDA Pins Channel Name Abbreviation Function Serial clock pin 0 SCK0 SCI0 clock input/output Receive data pin 0 RxD0/IrRxD Input SCI0 receive data input...
Page 384: Features
6.12 A/D Converter 6.12.1 Features • 10-bit resolution • Twelve input channels • Settable analog conversion voltage range • Conversion time: 6.7 µs per channel (at 20 MHz operation) • Selection of single mode or scan mode as operating mode •...
Page 385: Block Diagram
6.12.2 Block Diagram Internal data bus Module data bus 10-bit D/A – Comparator Multiplexer Control circuit AN12 Sample-and-hold AN13 circuit AN14 AN15 ADI interrupt signal ADTRG Conversion start trigger from 8-bit timer or TPU Legend ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C...
Page 386: Pins
6.12.3 Pins Table 6.11 A/D Converter Pins Abbre- Name viation Function Analog power supply pin AVCC Input Analog circuit power supply Analog ground pin AVSS Input Analog circuit ground and reference voltage Reference voltage pin Vref Input A/D conversion reference voltage Analog input pin 0 Input Channel set 0 (CH3 =1) group 0 analog input...
Page 387: Features
6.13 D/A Converter 6.13.1 Features • 8-bit resolution • Output on two channels to maximum four channels • Maximum conversion time of 10 µs (with 20 pF capacitive load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode •...
Page 388: Pins
6.13.3 Pins Table 6.12 D/A Converter Pins Name Abbreviation Function Analog power supply pin AVCC Input Analog circuit power supply Analog ground pin AVSS Input Analog circuit ground and reference voltage Analog output pin 0 Output Channel 0 analog output Analog output pin 1 Output Channel 1 analog output...
Page 389: Ram
6.14 6.14.1 Features • Sixteen kbytes or eight kbytes of on-chip high-speed static RAM • Connected to the CPU by a 16-bit data bus, enabling one-state access to both byte data and word data • Can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR) 6.14.2 Block Diagram...
Page 390: Block Diagrams
6.15 6.15.1 Features • Connected to the bus master by a 16-bit data bus, enabling one-state access to both byte data and word data • The flash memory version (F-ZTAT) can be erased and programmed on-board as well as with a PROM programmer •...
Page 391 Internal address bus Internal data bus (16 bits) FLMCR1 FLMCR2 Operating FWE pin Bus interface/controller mode Mode pins EBR1 EBR2 RAMER SYSCR Flash memory (256 kbytes) Legend FLMCR1: Flash memory control register 1 FLMCR2: Flash memory control register 2 EBR1: Erase block register 1 EBR2: Erase block register 2...
Page 392: Block Diagram
6.16 Clock Pulse Generator 6.16.1 Features • Comprises an oscillator, PLL (phase-locked loop) circuit, and frequency divider • Generates system clock (ø) and internal clock 6.16.2 Block Diagram PLLCR SCKCR STC0, STC1 SCK2 to SCK0 EXTAL PLL circuit Frequency Oscillator (×1, ×2, ×4) divider XTAL...
Page 394: Electrical Characteristics Of Mask Rom Version
Section 7 Electrical Characteristics Electrical Characteristics of Mask ROM Version (H8S/2677, H8S/2676, H8S/2675, H8S/2673) and ROMless Version (H8S/2670) 7.1.1 Absolute Maximum Ratings Table 7.1 lists the absolute maximum ratings. Table 7.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +4.6 PLLV Input voltage (except port 4, P54 to P57)
Page 395: Dc Characteristics
7.1.2 DC Characteristics Table 7.2 DC Characteristics Conditions: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), = –40°C to +85°C (wide-range specifications) Test Item Symbol...
Page 396 Test Item Symbol Unit Conditions µA Input — — 10.0 = 0.5 to leakage – 0.5 V current µA STBY, NMI, — — MD2 to MD0 µA Port 4, — — = 0.5 to P54 to P57 – 0.5 V µA Three-state Ports 1 to 3,...
Page 397 6. I depends on V and f as follows: max = 1.0 (mA) + TBD (mA/(MHz × V)) × V × f (normal operation) max = 1.0 (mA) + TBD (mA/(MHz × V)) × V × f (sleep mode) Table 7.3 Permissible Output Currents Conditions: V = 2.7 V to 3.6 V, AV...
Page 398: Ac Characteristics
7.1.3 AC Characteristics C = 50 pF: ports A to H C = 30 pF: ports 1 to 3, Chip output pin P50 to P53, ports 6 to 8 CL = 2.4 kΩ RH = 12 kΩ Input/output timing measurement level: 1.5 V (V = 2.7 V to 3.6 V) Figure 7.1 Output Load Circuit...
Page 399 Clock Timing Table 7.4 Clock Timing Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 400 ø Figure 7.2 System Clock Timing EXTAL DEXT DEXT STBY OSC1 OSC1 ø Figure 7.3 (1) Oscillation Stabilization Timing...
Page 401 Oscillator ø NMIEG SSBY NMI exception handling Software standby mode NMI exception (power-down mode) handling Oscillation NMIEG = 1 stabilization time SSBY = 1 OSC2 SLEEP instruction Figure 7.3 (2) Oscillation Stabilization Timing...
Page 402 Control Signal Timing Table 7.5 Control Signal Timing Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 403 ø RESS RESS RESW Figure 7.4 Reset Input Timing ø NMIS NMIH NMIW IRQW IRQi (i = 0 to 15)* IRQS IRQH (edge input) IRQS Note: * Necessary for SSIER setting to clear software standby mode. Figure 7.5 Interrupt Input Timing...
Page 404 Bus Timing Table 7.6 Bus Timing Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 405 Condition A Condition B Test Item Symbol Unit Conditions Read data hold — — Figure 7.6 to RDH2 time 2 Figure 7.19 1.0 × t 1.0 × t Read data — – 25 — – 20 access time 1 1.5 × t 1.5 ×...
Page 406 Condition A Condition B Test Item Symbol Unit Conditions 1.0 × t 1.0 × t Write data setup – 20 — – 13 — Figure 7.6 to WDS2 time 2 Figure 7.19 1.5 × t 1.5 × t Write data setup –...
Page 407 Condition A Condition B Test Item Symbol Unit Conditions 1.0 × t 1.0 × t Precharge – 20 — – 20 — Figure 7.6 to PCH1 time 1 Figure 7.19 1.5 × t 1.5 × t Precharge – 20 — –...
Page 408 ø A23 to A0 CSD1 CS7 to CS0 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD2 HWR, LWR Write WDH1 WSW1 D15 to D0 DACD1 DACD2 DACK0, DACK1...
Page 409 ø A23 to A0 CSD1 CS7 to CS0 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD1 HWR, LWR WDS1 Write WDH1 WSW2 D15 to D0 DACD1 DACD2 DACK0, DACK1...
Page 410 ø A23 to A0 CS7 to CS0 Read (RDNn = 1) D15 to D0 Read (RDNn = 0) D15 to D0 HWR, LWR Write D15 to D0 WAIT Figure 7.8 Basic Bus Timing: Three-State Access, One Wait...
Page 411 ø A23 to A0 CSD1 CS7 to CS0 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD2 HWR, LWR Write WDS2 WSW1 WDH3 D15 to D0 DACD1 DACD2 DACK0, DACK1...
Page 412 ø A23 to A0 CSD1 CS7 to CS0 RSD1 RSD1 Read RDS1 RDH1 (RDNn = 1) D15 to D0 RSD1 RSD2 Read RDS2 RDH2 (RDNn = 0) D15 to D0 WRD2 WRD1 HWR, LWR WDS3 Write WSW2 WDH3 D15 to D0 DACD1 DACD2 DACK0, DACK1...
Page 413 ø A23 to A6, A5 to A1 CS7 to CS0 RSD2 Read RDS2 RDH2 D15 to D0 HWR, LWR Figure 7.11 Burst ROM Access Timing: One-State Burst Access...
Page 414 ø A23 to A6, A5 to A1 CS7 to CS0 RSD2 RDS2 RDH2 Read D15 to D0 HWR, LWR Figure 7.12 Burst ROM Access Timing: Two-State Burst Access...
Page 415 ø A23 to A0 CSD3 CSD2 RAS5 to RAS2 PCH2 CASD1 CASD1 UCAS CASW1 LCAS OED1 OED1 OE, RD Read RDS2 RDH2 D15 to D0 OE, RD WCS1 WCH1 WRD2 WRD2 Write WDS1 WDH2 D15 to D0 DACD1 DACD2 DACK0, DACK1 EDACD1 EDACD2 EDACK0 to EDACK3...
Page 416 Tcwp ø A23 to A0 RAS5 to RAS2 UCAS, LCAS OE, RD Read D15 to D0 UCAS, LCAS OE, RD Write D15 to D0 WAIT DACK0, DACK1 EDACK0 to EDACK3 DACK and EDACK timing: when DDS = 0 and EDDS = 0 Note: RAS timing: when RAST = 0 Tcw:...
Page 417 ø A23 to A0 RAS5 to RAS2 CPW1 UCAS LCAS OE, RD Read D15 to D0 OE, RD Write RCS1 D15 to D0 DACD1 DACD2 DACK0, DACK1 EDACD1 EDACD2 EDACK0 to EDACK3 DACK and EDACK timing: when DDS = 1 and EDDS = 1 Note: RAS timing: when RAST = 0 Figure 7.15 DRAM Access Timing: Two-State Burst Access...
Page 418 ø A23 to A0 CSD3 CSD2 RAS5 to RAS2 PCH1 CASD1 CASD2 UCAS CASW2 LCAS OED2 OED1 OE, RD Read RDS2 RDH2 D15 to D0 OE, RD WCS2 WCH2 WRD2 WRD2 Write WDS2 WDH3 D15 to D0 DACD1 DACD2 DACK0, DACK1 EDACD1 EDACD2 EDACK0 to EDACK3...
Page 419 ø A23 to A0 RAS5 to RAS0 CPW2 UCAS LCAS OE, RD Read D15 to D0 OE, RD Write RCS2 D15 to D0 DACK0, DACK1 EDACK0 to EDACK3 DACK and EDACK timing: when DDS = 1 and EDDS = 1 Note: RAS timing: when RAST = 1 Figure 7.17 DRAM Access Timing: Three-State Burst Access...
Page 420 TRc1 TRc2 ø CSD1 CSD2 RAS5 to RAS2 CSR1 CASD1 CASD1 UCAS, LCAS Figure 7.18 CAS-Before-RAS Refresh Timing TRrw TRc1 TRcw TRc2 ø CSD1 CSD2 RAS5 to RAS2 CSR2 CASD1 CASD1 UCAS, LCAS Figure 7.19 CAS-Before-RAS Refresh Timing (with Wait Cycle Insertion)
Page 421 Self-refresh DRAM access Tpsr ø CSD2 CSD2 RAS5 to RAS2 RPS2 CASD1 CASD1 UCAS, LCAS Figure 7.20 Self-Refresh Timing (Return from Software Standby Mode: RAST = 0) Self-refresh DRAM access Tpsr ø CSD2 CSD2 RAS5 to RAS2 RPS1 CASD1 CASD1 UCAS to LCAS Figure 7.21 Self-Refresh Timing (Return from Software Standby Mode: RAST = 1)
Page 422 ø BREQS BREQS BREQ BACD BACD BACK A23 to A0 CS7 to CS0 (RAS5 to RAS2) D15 to D0 AS, RD HWR, LWR UCAS, LCAS, OE Figure 7.22 External Bus Release Timing ø BACK BRQOD BRQOD BREQO Figure 7.23 External Bus Request Output Timing...
Page 423 DMAC and EXDMAC Timing Table 7.7 DMAC and EXDMAC Timing Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 424 ø A23 to A0 CS7 to CS0 (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) DACD1 DACD2 DACK0, DACK1 EDACD1 EDACD2 EDACK0 to EDACK3 Figure 7.24 DMAC and EXDMAC Single Address Transfer Timing: Two-State Access...
Page 425 ø A23 to A0 CS7 to CS0 (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) DACD1 DACD2 DACK0, DACK1 EDACD1 EDACD2 EDACK0 to EDACK3 Figure 7.25 DMAC and EXDMAC Single Address Transfer Timing: Three-State Access...
Page 426 T2 or T3 ø TEND0, TEND1 ETED ETED ETEND0 to ETEND3 Figure 7.26 DMAC and EXDMAC TEND/ETEND Output Timing ø DRQS DRQH DREQ0, DREQ1 EDRQS DERQH EDREQ0 to EDREQ3 Figure 7.27 DMAC and EXDMAC DREQ/EDREQ Input Timing ø EDRKD EDRKD EDRAK0 to EDRAK3 Figure 7.28 EXDMAC EDRAK Output Timing...
Page 427 Timing of On-Chip Supporting Modules Table 7.8 Timing of On-Chip Supporting Modules Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 428 Condition A Condition B Test Item Symbol Unit Conditions 8-bit Timer output delay — — Figure7.33 TMOD timer time Timer reset input — — Figure7.35 TMRS setup time Timer clock input — — Figure7.34 TMCS setup time Timer Single-edge — —...
Page 429 ø Ports 1 to 8, A to H (read) Ports 1 to 3, 6 to 9, P53 to P50, ports A to H (write) Figure 7.29 I/O Port Input/Output Timing ø PO15 to PO0 Figure 7.30 PPG Output Timing ø TOCD Output compare output*...
Page 430 ø TCKS TCKS TCLKA to TCLKD TCKWL TCKWH Figure 7.32 TPU Clock Input Timing ø TMOD TMO0, TMO1 Figure 7.33 8-Bit Timer Output Timing ø TMCS TMCS TMCI0, TMCI1 TMCWL TMCWH Figure 7.34 8-Bit Timer Clock Input Timing ø TMRS TMRI0, TMRI1 Figure 7.35 8-Bit Timer Reset Input Timing...
Page 431 ø WOVD WOVD WDTOVF Figure 7.36 WDT Output Timing SCKW SCKr SCKf SCK0 to SCK2 Scyc Figure 7.37 SCK Clock Input Timing SCK0 to SCK2 TxD0 to TxD2 (transmit data) RxD0 to RxD2 (receive data) Figure 7.38 SCI Input/Output Timing: Synchronous Mode ø...
Page 432: Conversion Characteristics
7.1.4 A/D Conversion Characteristics Table 7.9 A/D Conversion Characteristics Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 433: D/A Conversion Characteristics
7.1.5 D/A Conversion Characteristics Table 7.10 D/A Conversion Characteristics Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 434: Electrical Characteristics Of F-Ztat Version (H8S/2677, H8S/2676)
Electrical Characteristics of F-ZTAT Version (H8S/2677, H8S/2676) 7.2.1 Absolute Maximum Ratings Table 7.11 lists the absolute maximum ratings. Table 7.11 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage –0.3 to +4.0 PLLV Input voltage (FWE) –0.3 to V +0.3 Input voltage (except port 4, P54 to P57) –0.3 to V...
Page 435: Dc Characteristics
7.2.2 DC Characteristics Table 7.12 DC Characteristics Conditions: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V* = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications) Test...
Page 436 Test Item Symbol Unit Conditions µA Input — — 10.0 = 0.5 to leakage – 0.5 V current µA STBY, NMI, — — MD2 to MD0 µA Port 4, — — = 0.5 to P54 to P57 – 0.5 V µA Three-state Ports 1 to 3,...
Page 437 6. I depends on V and f as follows: max = 1.0 (mA) + TBD (mA/(MHz × V)) × V × f (normal operation) max = 1.0 (mA) + TBD (mA/(MHz × V)) × V × f (sleep mode) Table 7.13 Permissible Output Currents Conditions: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V...
Page 438: Ac Characteristics
7.2.3 AC Characteristics Clock Timing Table 7.14 Clock Timing Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 439 Control Signal Timing Table 7.15 Control Signal Timing Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –...
Page 440 Bus Timing Table 7.16 Bus Timing Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 441 Condition A Condition B Test Item Symbol Unit Conditions Read data hold — — Figure7.6 to RDH1 time 1 Figure7.19 Read data hold — — RDH2 time 2 1.0 × t 1.0 × t Read data — – 25 — –...
Page 442 Condition A Condition B Test Item Symbol Unit Conditions Write data delay — — Figure7.6 to time Figure7.19 0.5 × t 0.5 × t Write data setup – 20 — – 13 — WDS1 time 1 1.0 × t 1.0 × t Write data setup –...
Page 443 Condition A Condition B Test Item Symbol Unit Conditions 1.0 × t 1.0 × t CAS precharge – 20 — – 20 — Figure7.6 to CPW1 time 1 Figure7.19 1.5 × t 1.5 × t CAS precharge – 20 — –...
Page 444 DMAC and EXDMAC Timing Table 7.17 DMAC and EXDMAC Timing Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 445 Timing of On-Chip Supporting Modules Table 7.18 Timing of On-Chip Supporting Modules Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 446 Condition A Condition B Test Item Symbol Unit Conditions Overflow output — — Figure 7.36 WOVD delay time Input Asynchronous t — — Figure 7.37 Scyc clock cycle Synchronous — — Input clock pulse SCKW Scyc width Input clock rise time —...
Page 447: A/D Conversion Characteristics
7.2.4 A/D Conversion Characteristics Table 7.19 A/D Conversion Characteristics Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 448: D/A Conversion Characteristics
7.2.5 D/A Conversion Characteristics Table 7.20 D/A Conversion Characteristics Condition A*: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, ø = 2 MHz to 20 MHz, T = –20°C to +75°C (regular specifications), T = –40°C to +85°C (wide-range specifications)
Page 449: Flash Memory Characteristics
7.2.6 Flash Memory Characteristics Table 7.21 Flash Memory Characteristics Conditions: V = 2.7 V to 3.6 V, AV = 2.7 V to 3.6 V, V = 2.7 V to AV = AV = 0 V, T = 0°C to 75°C (program/erase operating temperature range: regular specifications), T = 0°C to 85°C (program/erase operating temperature range: wide-range specifications)
Page 450 Test Item Symbol Unit Conditions µs Erasing Wait time after — — SWE bit setting* µs Wait time after — — ESU bit setting* µs Wait time after — — Erase time E bit setting* wait α µs Wait time after —...
Page 451: Usage Note
Usage Note The F-ZTAT and mask ROM versions both satisfy the electrical characteristics shown in this manual, but actual electrical characteristic values, operating margins, noise margins, and other properties may vary due to differences in manufacturing process, on-chip ROM, layout patterns, and so on.
Page 452: Section 8 Registers
Section 8 Registers List of Registers (Address Order) Table 8.1 List of Registers (Address Order) Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'BC00 16/32* bits H'BFFF CHNE DISEL...
Page 453 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FDD4 EDDAR1 — — — — — — — — EXDMAC 16 bits channel 1 H'FDD5 H'FDD6 H'FDD7 H'FDD8 EDTCR1 —...
Page 454 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FDF8 EDTCR3 — — — — — — — — EXDMAC 16 bits channel 3 H'FDF9 H'FDFA H'FDFB H'FDFC EDMDR3 EDRAKE ETENDE EDREQS AMS MDS1...
Page 455 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FE1E IrCR IrCKS2 IrCKS1 IrCKS0 — — — — IrDA 8 bits H'FE20 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Ports 8 bits H'FE21 P2DDR...
Page 456 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FE8C TGR3C TPU3 16 bits H'FE8D H'FE8E TGR3D H'FE8F H'FE90 TCR4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU4 16 bits...
Page 457 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FECC BCR BRLE BREQ0E — IDLC ICIS1 ICIS0 WDBE WAITE 16 bits controller H'FECD — — — — —...
Page 458 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FEFA MAR1BL DMAC 16 bits H'FEFB H'FEFC IOAR1B H'FEFD H'FEFE ETCR1B H'FEFF H'FF20 DMAWER — — — — WE1B WE1A WE0B...
Page 459 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FF27 DMABCRL DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Short 16 bits address mode DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A...
Page 460 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FF59 PORTA Ports 8 bits H'FF5A PORTB H'FF5B PORTC H'FF5C PORTD H'FF5D PORTE H'FF5E PORTF H'FF5F PORTG — H'FF60 P1DR P17DR...
Page 461 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FF84 SSR1 TDRE RDRF ORER FER/ TEND MPBT SCI1, 8 bits ERS* smart card interface 1 H'FF85 RDR1 H'FF86 SCMR1 —...
Page 462 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FFBC TCSR WT/IT — — CKS2 CKS1 CKS0 Watchdog 16 bits (read) timer H'FFBD TCNT (read) H'FFBF RSTCSR WOVF RSTE —...
Page 463 Abbre- Module Address viation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name Width H'FFF0 TCR2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2 16 bits H'FFF1 TMDR2 — — — —...
Page 464: List Of Registers (By Module)
List of Registers (By Module) Table 8.2 List of Registers (By Module) Module Register Abbreviation R/W Initial Value Address* Interrupt Interrupt control register INTCR H'00 H'FF31 controller IRQ sense control register H ISCRH H'0000 H'FF1A IRQ sense control register L ISCRL H'0000 H'FF1C...
Page 465 Module Register Abbreviation R/W Initial Value Address* DMAC DMA write enable register DMAWER H'00 H'FF20 channels 0 DMA terminal control register DMATCR H'00 H'FF21 and 1 DMA control register 0A DMACR0A H'00 H'FF22 DMA control register 0B DMACR0B H'00 H'FF23 DMA control register 1A DMACR1A H'00...
Page 466 Module Register Abbreviation R/W Initial Value Address* EXDMAC EXDMA source address register 2 EDSAR2 Undefined H'FDE0 channel 2 EXDMA destination address EDDAR2 Undefined H'FDE4 register 2 EXDMA transfer count register 2 EDTCR2 Undefined H'FDE8 EXDMA mode control register 2 EDMDR2 R/W* H'0000 H'FDEC...
Page 467 Module Register Abbreviation R/W Initial Value Address* TPU0 Timer interrupt enable register 0 TIER0 H'40 H'FFD4 Timer status register 0 TSR0 R/(W)* H'C0 H'FFD5 Timer counter 0 TCNT0 H'0000 H'FFD6 Timer general register 0A TGR0A H'FFFF H'FFD8 Timer general register 0B TGR0B H'FFFF H'FFDA...
Page 468 Module Register Abbreviation R/W Initial Value Address* TPU3 Timer general register 3C TGR3C H'FFFF H'FE8C Timer general register 3D TGR3D H'FFFF H'FE8E TPU4 Timer control register 4 TCR4 H'00 H'FE90 Timer mode register 4 TMDR4 H'C0 H'FE91 Timer I/O control register 4 TIOR4 H'00 H'FE92...
Page 469 Module Register Abbreviation R/W Initial Value Address* 8-bit timer Timer control register 0 TCR0 H'00 H'FFB0 Timer control/status register 0 TCSR0 R/(W)* H'00 H'FFB2 Timer constant register A0 TCORA0 H'FF H'FFB4 Timer constant register B0 TCORB0 H'FF H'FFB6 Timer counter 0 TCNT0 H'00 H'FFB8...
Page 470 Module Register Abbreviation R/W Initial Value Address* SCI1 Transmit data register 1 TDR1 H'FF H'FF83 Serial status register 1 SSR1 R/(W)* H'84 H'FF84 Receive data register 1 RDR1 H'00 H'FF85 Smart card mode register 1 SCMR1 H'F2 H'FF86 SCI2 Serial mode register 2 SMR2 H'00 H'FF88...
Page 471 Module Register Abbreviation R/W Initial Value Address* On-chip System control register SYSCR H'81 H'FF3D Flash Flash memory control register 1 FLMCR1* R/W* H'00* H'FFC8* memory Flash memory control register 2 FLMCR2* R/W* H'00* H'FFC9* Erase block register 1 EBR1* R/W* H'00* H'FFCA* Erase block register 2...
Page 472 Module Register Abbreviation R/W Initial Value Address* Port 5 Port 5 data direction register P5DDR H'00 H'FE24 Port 5 data register P5DR H'00 H'FF64 Port 5 register PORT5 Undefined H'FF54 Port 6 Port 6 data direction register P6DDR H'00 H'FE25 Port 6 data register P6DR H'00...
Page 473 9. Only 0 can be written to bits 7 to 5, to clear the flags. 10. For information on writing, see section 11.2.4, Notes on Register Access, in the H8S/2678 Series Hardware Manual. 11. Only 0 can be written to bit 7, to clear the flag.
Page 474 12. Flash memory registers are allocated to the same addresses as other registers. Register selection is performed by means of the FLSHE bit in the system control register (SYSCR). 13. In modes in which the on-chip flash memory is disabled, a read will return H'00, and writes are invalid.
Page 475: Register Descriptions
Register Descriptions Register Register Address to which the Name of acronym name register is mapped on-chip supporting module DACR01—D/A Control Register 01 H'FFA6 D/A Converter numbers Initial bit DAOE1 DAOE0 — — — — — values Initial value Names of the bits.
Page 476 MRA—DTC Mode Register A H'BC00 to H'BFFF Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — — — DTC Data Transfer Size 0 Byte-size transfer Word-size transfer DTC Transfer Mode Select 0 Destination is repeat area or block area Source is repeat area or block area...
Page 477 MRB—DTC Mode Register B H'BC00 to H'BFFF CHNE DISEL CHNS — — — — — Initial value Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write — — — — — — — — Reserved bits (write 0) DTC Chain Transfer Select CHNE CHNS Description...
Page 478 DAR—DTC Destination Address Register H'BC00 to H'BFFF · · · · · · · · · Initial value — — — — — · · · — — — — — Read/Write Specifies data transfer destination address *: Undefined CRA—DTC Transfer Count Register A H'BC00 to H'BFFF Initial value Read/Write...
Page 479 EDSAR0—EXDMA Source Address Register 0 H'FDC0 EXDMAC — — — — — — — — Initial value — — — — — — — — Read/Write Initial value Read/Write Specifies transfer source address *: Undefined EDDAR0—EXDMA Destination Address Register 0 H'FDC4 EXDMAC —...
Page 480 EDTCR0—EXDMA Transfer Count Register 0 H'FDC8 EXDMAC — — — — — — — — Initial value — — — — — — — — Read/Write Initial value Read/Write Normal transfer mode: 24-bit transfer counter Block transfer mode: Block size (bits 23 to 16) 16-bit transfer counter (bits 15 to 0) *: Undefined...
Page 481 EDMDR0—EXDMA Mode Control Register 0 H'FDCC EXDMAC EDRAKE ETENDE EDREQS MDS1 MDS0 Initial value R/(W) R/(W) Read/Write Mode Select 1 and 0 Auto request, cycle steal mode, normal transfer mode Auto request, burst mode, normal transfer mode External request, cycle steal mode, normal transfer mode External request, cycle steal mode, block transfer mode...
Page 482 EDIE TCEIE SDIR DTSIZE BGUP — — Initial value R/(W) * R/(W) Read/Write Bus Give-Up Bus is not released in burst mode or block transfer mode In burst mode or block transfer mode, the bus is transferred if requested by an internal bus master Data Transmit Size Byte-size (8-bit) specification...
Page 483 EDACR0—EXDMA Address Control Register 0 H'FDCE EXDMAC SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 Initial value Read/Write Source Address Repeat Area Source address (EDSAR) is not designated as repeat area Lower 1 bit of EDSAR (2-byte area) designated as repeat area Lower 2 bits of EDSAR (4-byte area) designated as repeat area Lower 3 bits of EDSAR (8-byte area) designated as repeat area Lower 4 bits of EDSAR (16-byte area) designated as repeat area...
Page 484 DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 Initial value Read/Write Destination Address Repeat Area Destination address (EDDAR) is not designated as repeat area Lower 1 bit of EDDAR (2-byte area) designated as repeat area Lower 2 bits of EDDAR (4-byte area) designated as repeat area Lower 3 bits of EDDAR (8-byte area) designated as repeat area Lower 4 bits of EDDAR (16-byte area) designated as repeat area : (Continues in the same way)
Page 485 EDSAR1—EXDMA Source Address Register 1 H'FDD0 EXDMAC — — — — — — — — Initial value — — — — — — — — Read/Write Initial value Read/Write Specifies transfer source address *: Undefined EDDAR1—EXDMA Destination Address Register 1 H'FDD4 EXDMAC —...
Page 486 EDTCR1—EXDMA Transfer Count Register 1 H'FDD8 EXDMAC — — — — — — — — Initial value — — — — — — — — Read/Write Initial value Read/Write Normal transfer mode: 24-bit transfer counter Block transfer mode: Block size (bits 23 to 16) 16-bit transfer counter (bits 15 to 0) *: Undefined...
Page 487 EDMDR1—EXDMA Mode Control Register 1 H'FDDC EXDMAC EDRAKE ETENDE EDREQS MDS1 MDS0 Initial value R/(W) R/(W) Read/Write Mode Select 1 and 0 Auto request, cycle steal mode, normal transfer mode Auto request, burst mode, normal transfer mode External request, cycle steal mode, normal transfer mode External request, cycle steal mode, block transfer mode...
Page 488 EDIE TCEIE SDIR DTSIZE BGUP — — Initial value R/(W) * R/(W) Read/Write Bus Give-Up Bus is not released in burst mode or block transfer mode In burst mode or block transfer mode, the bus is transferred if requested by an internal bus master Data Transmit Size Byte-size (8-bit) specification...
Page 489 EDACR1—EXDMA Address Control Register 1 H'FDDE EXDMAC SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 Initial value Read/Write Source Address Repeat Area Source address (EDSAR) is not designated as repeat area Lower 1 bit of EDSAR (2-byte area) designated as repeat area Lower 2 bits of EDSAR (4-byte area) designated as repeat area Lower 3 bits of EDSAR (8-byte area) designated as repeat area Lower 4 bits of EDSAR (16-byte area) designated as repeat area...
Page 490 DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 Initial value Read/Write Destination Address Repeat Area Destination address (EDDAR) is not designated as repeat area Lower 1 bit of EDDAR (2-byte area) designated as repeat area Lower 2 bits of EDDAR (4-byte area) designated as repeat area Lower 3 bits of EDDAR (8-byte area) designated as repeat area Lower 4 bits of EDDAR (16-byte area) designated as repeat area : (Continues in the same way)
Page 491 EDSAR2—EXDMA Source Address Register 2 H'FDE0 EXDMAC — — — — — — — — Initial value — — — — — — — — Read/Write Initial value Read/Write Specifies transfer source address *: Undefined EDDAR2—EXDMA Destination Address Register 2 H'FDE4 EXDMAC —...
Page 492 EDTCR2—EXDMA Transfer Count Register 2 H'FDE8 EXDMAC — — — — — — — — Initial value — — — — — — — — Read/Write Initial value Read/Write Normal transfer mode: 24-bit transfer counter Block transfer mode: Block size (bits 23 to 16) 16-bit transfer counter (bits 15 to 0) *: Undefined...
Page 493 EDMDR2—EXDMA Mode Control Register 2 H'FDEC EXDMAC EDRAKE ETENDE EDREQS MDS1 MDS0 Initial value R/(W) R/(W) Read/Write Mode Select 1 and 0 Auto request, cycle steal mode, normal transfer mode Auto request, burst mode, normal transfer mode External request, cycle steal mode, normal transfer mode External request, cycle steal mode, block transfer mode...
Page 494 EDIE TCEIE SDIR DTSIZE BGUP — — Initial value R/(W) * Read/Write R/(W) Bus Give-Up Bus is not released in burst mode or block transfer mode In burst mode or block transfer mode, the bus is transferred if requested by an internal bus master Data Transmit Size Byte-size (8-bit) specification...
Page 495 EDACR2—EXDMA Address Control Register 2 H'FDEE EXDMAC SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 Initial value Read/Write Source Address Repeat Area Source address (EDSAR) is not designated as repeat area Lower 1 bit of EDSAR (2-byte area) designated as repeat area Lower 2 bits of EDSAR (4-byte area) designated as repeat area Lower 3 bits of EDSAR (8-byte area) designated as repeat area Lower 4 bits of EDSAR (16-byte area) designated as repeat area...
Page 496 DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 Initial value Read/Write Destination Address Repeat Area Destination address (EDDAR) is not designated as repeat area Lower 1 bit of EDDAR (2-byte area) designated as repeat area Lower 2 bits of EDDAR (4-byte area) designated as repeat area Lower 3 bits of EDDAR (8-byte area) designated as repeat area Lower 4 bits of EDDAR (16-byte area) designated as repeat area : (Continues in the same way)
Page 497 EDSAR3—EXDMA Source Address Register 3 H'FDF0 EXDMAC — — — — — — — — Initial value — — — — — — — — Read/Write Initial value Read/Write Specifies transfer source address *: Undefined EDDAR3—EXDMA Destination Address Register 3 H'FDF4 EXDMAC —...
Page 498 EDTCR3—EXDMA Transfer Count Register 3 H'FDF8 EXDMAC — — — — — — — — Initial value — — — — — — — — Read/Write Initial value Read/Write Normal transfer mode: 24-bit transfer counter Block transfer mode: Block size (bits 23 to 16) 16-bit transfer counter (bits 15 to 0) *: Undefined...
Page 499 EDMDR3—EXDMA Mode Control Register 3 H'FDFC EXDMAC EDRAKE ETENDE EDREQS MDS1 MDS0 Initial value R/(W) R/(W) Read/Write Mode Select 1 and 0 Auto request, cycle steal mode, normal transfer mode Auto request, burst mode, normal transfer mode External request, cycle steal mode, normal transfer mode External request, cycle steal mode, block transfer mode...
Page 500 EDIE TCEIE SDIR DTSIZE BGUP — — Initial value R/(W) * R/(W) Read/Write Bus Give-Up Bus is not released in burst mode or block transfer mode In burst mode or block transfer mode, the bus is transferred if requested by an internal bus master Data Transmit Size Byte-size (8-bit) specification...
Page 501 EDACR3—EXDMA Address Control Register 3 H'FDFE EXDMAC SAT1 SAT0 SARIE SARA4 SARA3 SARA2 SARA1 SARA0 Initial value Read/Write Source Address Repeat Area Source address (EDSAR) is not designated as repeat area Lower 1 bit of EDSAR (2-byte area) designated as repeat area Lower 2 bits of EDSAR (4-byte area) designated as repeat area Lower 3 bits of EDSAR (8-byte area) designated as repeat area Lower 4 bits of EDSAR (16-byte area) designated as repeat area...
Page 502 DAT1 DAT0 DARIE DARA4 DARA3 DARA2 DARA1 DARA0 Initial value Read/Write Destination Address Repeat Area Destination address (EDDAR) is not designated as repeat area Lower 1 bit of EDDAR (2-byte area) designated as repeat area Lower 2 bits of EDDAR (4-byte area) designated as repeat area Lower 3 bits of EDDAR (8-byte area) designated as repeat area Lower 4 bits of EDDAR (16-byte area) designated as repeat area : (Continues in the same way)
Page 503 IPRA—Interrupt Priority Register A H'FE00 Interrupt Controller IPRB—Interrupt Priority Register B H'FE02 Interrupt Controller IPRC—Interrupt Priority Register C H'FE04 Interrupt Controller IPRD—Interrupt Priority Register D H'FE06 Interrupt Controller IPRE—Interrupt Priority Register E H'FE08 Interrupt Controller IPRF—Interrupt Priority Register F H'FE0A Interrupt Controller IPRG—Interrupt Priority Register G H'FE0C...
Page 504 ITSR—IRQ Pin Select Register H'FE16 Interrupt Controller ITS15 ITS14 ITS13 ITS12 ITS11 ITS10 ITS9 ITS8 Initial value Read/Write ITS7 ITS6 ITS5 ITS4 ITS3 ITS2 ITS1 ITS0 Initial value Read/Write IRQ Input Pin Select ITSn Description IRQn requests are accepted at the IRQn pin IRQn requests are accepted at the (IRQn) pin (n = 15 to 0)
Page 505 SSIER—Software Standby Release IRQ Enable Register H'FE18 Interrupt Controller SSI15 SSI14 SSI13 SSI12 SSI11 SSI10 SSI9 SSI8 Initial value Read/Write SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0 Initial value Read/Write Software Standby Release IRQ Setting SSIn Description IRQn requests are not sampled in the software standby state When an IRQn request occurs in the software standby state, the chip recovers from the software...
Page 506 ISCRH—IRQ Sense Control Register H H'FE1A Interrupt Controller ISCRL—IRQ Sense Control Register L H'FE1C Interrupt Controller ISCRH IRQ15SCB IRQ15SCA IRQ14SCB IRQ14SCA IRQ13SCB IRQ13SCA IRQ12SCB IRQ12SCA Initial value Read/Write IRQ11SCB IRQ11SCA IRQ10SCB IRQ10SCA IRQ9SCB IRQ9SCA IRQ8SCB IRQ8SCA Initial value Read/Write ISCRL IRQ7SCB IRQ7SCA IRQ6SCB...
Page 507 IrCR—IrDA Control Register H'FE1E IrDA IrCKS2 IrCKS1 IrCKS0 — — — — Initial value — — — — Read/Write IrDA Clock Select 2 to 0 B × 3/16 (3/16 of bit rate) ø/2 ø/4 ø/8 ø/16 ø/32 ø/64 ø/128 IrDA Enable Pins TxD0/IrTxD and RxD0/IrRxD function as TxD0 and RxD0 Pins TxD0/IrTxD and RxD0/IrRxD function as IrTxD and IrRxD P1DDR—Port 1 Data Direction Register...
Page 508 P2DDR—Port 2 Data Direction Register H'FE21 Port 2 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value Read/Write Specify input or output for individual port 2 pins P3DDR—Port 3 Data Direction Register H'FE22 Port 3 — — P35DDR P34DDR P33DDR P32DDR P31DDR...
Page 509 P7DDR—Port 7 Data Direction Register H'FE26 Port 7 — — P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR Initial value Read/Write — — Specify input or output for individual port 7 pins P8DDR—Port 8 Data Direction Register H'FE27 Port 8 — — P85DDR P84DDR P83DDR...
Page 510 PCDDR—Port C Data Direction Register H'FE2B Port C PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value Read/Write Specify input or output for individual port C pins PDDDR—Port D Data Direction Register H'FE2C Port D PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR...
Page 511 PFDDR—Port F Data Direction Register H'FE2E Port F PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 1, 2, 4, 5, 6 Initial value Read/Write Mode 7 Initial value Read/Write Specify input or output for individual port F pins PGDDR—Port G Data Direction Register H'FE2F Port G —...
Page 512 PFCR0—Port Function Control Register 0 H'FE32 Ports CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E Initial value Read/Write CS7 to CS0 Enable Pin is designated as I/O port and does not function as CSn output pin Pin is designated as CSn output pin (n = 7 to 0) PFCR1—Port Function Control Register 1 H'FE33...
Page 513 PFCR2—Port Function Control Register 2 H'FE34 Ports — — — — ASOE LWROE DMACS Initial value — — — — Read/Write DMAC Control Pin Select P65 to P60 are designated as DMAC control pins P75 to P70 are designated as DMAC control pins OE Output Select P35 is designated as OE output pin PH3 is designated as OE output pin...
Page 514 PAPCR—Port A MOS Pull-Up Control Register H'FE36 Port A PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value Read/Write Bit-by-bit control of MOS input pull-up function incorporated into port A PBPCR—Port B MOS Pull-Up Control Register H'FE37 Port B PB7PCR PB6PCR PB5PCR...
Page 515 PEPCR—Port E MOS Pull-Up Control Register H'FE3A Port E PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value Read/Write Bit-by-bit control of MOS input pull-up function incorporated into port E P3ODR—Port 3 Open Drain Control Register H'FE3C Port 3 —...
Page 516 TCR3—Timer Control Register 3 H'FE80 TPU3 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write Timer Prescaler Internal clock: count on ø/1 Internal clock: count on ø/4 Internal clock: count on ø/16 Internal clock: count on ø/64 External clock: count on TCLKA pin input Internal clock: count on ø/1024 Internal clock: count on ø/256 Internal clock: count on ø/4096...
Page 517 TMDR3—Timer Mode Register 3 H'FE81 TPU3 — — Initial value Read/Write — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — *: Don’t care Notes: 1.
Page 518 TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR3A I/O Control TGR3A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match 1 0 0 Output disabled...
Page 519 TIOR3L—Timer I/O Control Register 3L H'FE83 TPU3 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value Read/Write TRG3C I/O Control TGR3C Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match 1 0 0 Output disabled...
Page 520 TIER3—Timer Interrupt Enable Register 3 H'FE84 TPU3 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value Read/Write — — TGR Interrupt Enable A Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB)
Page 521 TSR3—Timer Status Register 3 H'FE85 TPU3 — — — TCFV TGFD TGFC TGFB TGFA Initial value Read/Write — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt and DISEL bit in DTC’s MRB register is 0 •...
Page 522 TCNT3—Timer Counter 3 H'FE86 TPU3 Initial value Read/Write Up-counter TGR3A—Timer General Register 3A H'FE88 TPU3 TGR3B—Timer General Register 3B H'FE8A TPU3 TGR3C—Timer General Register 3C H'FE8C TPU3 TGR3D—Timer General Register 3D H'FE8E TPU3 Initial value Read/Write...
Page 523 TCR4—Timer Control Register 4 H'FE90 TPU4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Timer Prescaler Internal clock: count on ø/1 Internal clock: count on ø/4 Internal clock: count on ø/16 Internal clock: count on ø/64 External clock: count on TCLKA pin input External clock: count on TCLKC pin input Internal clock: count on ø/1024...
Page 524 TMDR4—Timer Mode Register 4 H'FE91 TPU4 — — — — Initial value Read/Write — — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 525 TIOR4—Timer I/O Control Register 4 H'FE92 TPU4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR4A I/O Control TGR4A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match 1 0 0 Output disabled...
Page 526 TIER4—Timer Interrupt Enable Register 4 H'FE94 TPU4 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB)
Page 527 TSR4—Timer Status Register 4 H'FE95 TPU4 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt and DISEL bit in DTC’s MRB register is 0 •...
Page 528 TCNT4—Timer Counter 4 H'FE96 TPU4 Initial value Read/Write Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR4A—Timer General Register 4A H'FE98 TPU4...
Page 529 TCR5—Timer Control Register 5 H'FEA0 TPU5 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: count on ø/1 Internal clock: count on ø/4 Internal clock: count on ø/16 Internal clock: count on ø/64 External clock: count on TCLKA pin input External clock: count on TCLKC pin input Internal clock: count on ø/256...
Page 530 TMDR5—Timer Mode Register 5 H'FEA1 TPU5 — — — — Initial value Read/Write — — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 531 TIOR5—Timer I/O Control Register 5 H'FEA2 TPU5 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR5A I/O Control TGR5A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match 1 0 0 Output disabled...
Page 532 TIER5—Timer Interrupt Enable Register 5 H'FEA4 TPU5 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB)
Page 533 TSR5—Timer Status Register 5 H'FEA5 TPU5 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A [Clearing conditions] • When DTC is activated by TGIA interrupt and DISEL bit in DTC’s MRB register is 0 •...
Page 534 TCNT5—Timer Counter 5 H'FEA6 TPU5 Initial value Read/Write Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR5A—Timer General Register 5A H'FEA8 TPU5...
Page 535 ABWCR—Bus Width Control Register H'FEC0 Bus Controller ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 2, 4, 6 Initial value Read/Write Modes 1, 5, 7 Initial value Read/Write Area 7 to 0 Bus Width Control 0 Area n is designated as 16-bit access space Area n is designated as 8-bit access space (n = 15 to 0) ASTCR—Access State Control Register...
Page 536 WTCRA—Wait Control Register A H'FEC2 Bus Controller WTCRB—Wait Control Register B H'FEC4 Bus Controller WTCRA — — Initial value Read/Write — — Initial value Read/Write WTCRB — — Initial value Read/Write — — Initial value Read/Write Wait Control Description Program wait not inserted in area n external access 1 program wait state inserted in area n external access 2 program wait states inserted in area n external access 3 program wait states inserted in area n external access...
Page 537 RDNCR—Read Strobe Timing Control Register H'FEC6 Bus Controller RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0 Initial value Read/Write Read Strobe Timing Control RDNn Description In an area n read access, the RD strobe is negated at the end of the read cycle In an area n read access, the RD strobe is negated one half-state before the end of the read cycle (n = 7 to 0)
Page 538 CSACRH, CSACRL—CS Assertion Period Control Registers H'FEC8 Bus Controller CSACRH CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0 Initial value Read/Write CS and Address Signal Assertion Period Control 1 CSXHn Description In area n basic bus interface access, the CSn and address assertion period (T ) is not extended In area n basic bus interface access, the CSn and...
Page 539 BROMCRH—Area 0 Burst ROM I/F Control Register H'FECA Bus Controller BROMCRL—Area 1 Burst ROM I/F Control Register H'FECB Bus Controller BROMCRH BSRM0 BSTS02 BSTS01 BSTS00 — — BSWD01 BSWD00 Initial value Read/Write BROMCRL BSRM1 BSTS12 BSTS11 BSTS10 — — BSWD11 BSWD10 Initial value Read/Write...
Page 540 BCR—Bus Control Register H'FECC Bus Controller BRLE BREQOE — IDLC ICIS1 ICIS0 WDBE WAITE Initial value Read/Write WAIT Pin Enable Wait input by WAIT pin disabled WAIT pin can be used as I/O port Wait input by WAIT pin enabled Write Data Buffer Enable Write data buffer function not used Write data buffer function used...
Page 541 RAMER—RAM Emulation Register H'FECE (F-ZTAT Version Only) — — — — RAMS RAM2 RAM1 RAM0 Initial value — — — — Read/Write RAM Select, Flash Memory Area Select RAM Area Modes 5, 6, 13, 14 Modes 4, 7, 10, 11, 12, 15 RAMS RAM2...
Page 542 DRAMCR—DRAM Control Register H'FED0 Bus Controller RAST — CAST — RMTS2 RMTS1 RMTS0 Initial value Read/Write DRAM Space Select Description RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 Normal space Normal space DRAM space Normal space DRAM space DRAM space —...
Page 543 RCDM EDDS — MXC2 MXC1 MXC0 Initial value Read/Write Address Multiplex Select 8-bit shift • When 8-bit access space is designated: Row address bits A23 to A8 used for comparison • When 16-bit access space is designated: Row address bits A23 to A9 used for comparison 9-bit shift •...
Page 544 DRACCR—DRAM Access Control Register H'FED2 Bus Controller DRMI — TPC1 TPC0 — — RCD1 RCD0 Initial value Read/Write RAS-CAS Wait Control Wait cycle not inserted between RAS assert cycle and CAS assert cycle 1-state wait cycle inserted between RAS assert cycle and CAS assert cycle 2-state wait cycle inserted between RAS assert cycle and CAS assert cycle 3-state wait cycle inserted between...
Page 545 REFCR—Refresh Control Register H'FED4 Bus Controller CMIE RCW1 RCW0 — RTCK2 RTCK1 RTCK0 Initial value R/(W) * Read/Write Refresh Counter Clock Select Count operation halted Count on ø/2 Count on ø/8 Count on ø/32 Count on ø/128 Count on ø/512 Count on ø/2048 Count on ø/4096 CAS-RAS Wait Control...
Page 546 RFSHE CBRM RLW1 RLW0 SLFRF TPCS2 TPCS1 TPCS0 Initial value Read/Write Self-Refresh Precharge Cycle Control RAS precharge cycle after self-refresh = [TPC set value] states RAS precharge cycle after self-refresh = [TPC set value + 1] states RAS precharge cycle after self-refresh = [TPC set value + 2] states RAS precharge cycle after self-refresh = [TPC set value + 3] states...
Page 547 RTCNT—Refresh Timer Counter H'FED6 Bus Controller Initial value Read/Write Count value based on internal clock RTCOR—Refresh Time Control Register H'FED7 Bus Controller Initial value Read/Write Period for compare match operations with RTCNT...
Page 548 MAR0AH—Memory Address Register 0AH H'FEE0 DMAC MAR0AL—Memory Address Register 0AL H'FEE2 DMAC — — — — — — — — MAR0AH Initial value Read/Write — — — — — — — — MAR0AL Initial value Read/Write In short address mode: Specifies transfer destination/transfer source address In full address mode: Specifies transfer source address *: Undefined...
Page 549 ETCR0A—Transfer Count Register 0A H'FEE6 DMAC ETCR0A Initial value Read/Write Sequential mode Transfer counter and idle mode Normal mode Repeat mode Holds number of transfers Transfer counter Block transfer mode Holds block size Block size counter *: Undefined MAR0BH—Memory Address Register 0BH H'FEE8 DMAC MAR0BL—Memory Address Register 0BL...
Page 550 IOAR0B—I/O Address Register 0B H'FEEC DMAC IOAR0B Initial value Read/Write In short address mode: Specifies transfer destination/transfer source address In full address mode: Not used *: Undefined ETCR0B—Transfer Count Register 0B H'FEEE DMAC ETCR0B Initial value Read/Write Sequential mode Transfer counter and idle mode Repeat mode Holds number of transfers...
Page 551 MAR1AH—Memory Address Register 1AH H'FEF0 DMAC MAR1AL—Memory Address Register 1AL H'FEF2 DMAC — — — — — — — — MAR1AH Initial value Read/Write — — — — — — — — MAR1AL Initial value Read/Write In short address mode: Specifies transfer destination/transfer source address In full address mode: Not used *: Undefined...
Page 552 ETCR1A—Transfer Count Register 1A H'FEF6 DMAC ETCR1A Initial value Read/Write Sequential mode Transfer counter Idle mode Normal mode Repeat mode Holds number of transfers Transfer counter Block transfer mode Holds block size Block size counter *: Undefined MAR1BH—Memory Address Register 1BH H'FEF8 DMAC MAR1BL—Memory Address Register 1BL...
Page 553 IOAR1B—I/O Address Register 1B H'FEFC DMAC IOAR1B Initial value Read/Write In short address mode: Specifies transfer destination/transfer source address In full address mode: Not used *: Undefined ETCR1B—Transfer Count Register 1B H'FEFE DMAC ETCR1B Initial value Read/Write Sequential mode Transfer counter and idle mode Repeat mode Holds number of transfers...
Page 554 DMAWER—DMA Write Enable Register H'FF20 DMAC DMAWER — — — — WE1B WE1A WE0B WE0A Initial value — — — — Read/Write Write Enable 0A Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Write Enable 0B...
Page 555 DMATCR—DMA Terminal Control Register H'FF21 DMAC — — TEE1 TEE0 — — — — DMATCR Initial value Read/Write — — — — — — TEND0 Pin Enable TEND0 pin output disabled TEND0 pin output enabled TEND1 Pin Enable TEND1 pin output disabled TEND1 pin output enabled...
Page 556 DMACR0A—DMA Control Register 0A H'FF22 DMAC DMACR1A—DMA Control Register 1A H'FF24 DMAC DMACR0B—DMA Control Register 0B H'FF23 DMAC DMACR1B—DMA Control Register 1B H'FF25 DMAC Full address mode DMACRA DTSZ SAID SAIDE BLKDIR BLKE — — — DMACRA Initial value Read/Write Block Direction/Block Enable Transfer in normal mode Transfer in block transfer mode,...
Page 557 Full address mode DMACRB DMACRB — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 Initial value Read/Write Data Transfer Factor DTF3 DTF2 DTF1 DTF0 Block Transfer Mode Normal Mode — — A/D converter conversion end — interrupt DREQ pin falling edge input DREQ pin falling edge input DREQ pin low-level input DREQ pin low-level input...
Page 558 Short address mode DTSZ DTID DTDIR DTF3 DTF2 DTF1 DTF0 DMACR Initial value Read/Write Data Transfer Factor Channel A Channel B — Activated by A/D converter conversion end interrupt Activated by DREQ pin — falling edge input Activated by DREQ pin —...
Page 559 DMABCRH—DMA Band Control Register H'FF26 DMAC DMABCRL—DMA Band Control Register H'FF27 DMAC Full address mode DMABCRH DMABCRH FAE1 FAE0 — — DTA1 — DTA0 — Initial value Read/Write Channel 0 Data Transfer Acknowledge Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 1 Data Transfer Acknowledge...
Page 560 Full address mode DMABCRL DMABCRL DTME1 DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A Initial value Read/Write Channel 0 Data Transfer Interrupt Enable A Transfer end interrupt disabled Transfer end interrupt enabled Channel 0 Data Transfer Interrupt Enable B Transfer suspended interrupt disabled Transfer suspended interrupt enabled Channel 1 Data Transfer Interrupt Enable A Transfer end interrupt disabled...
Page 561 Short address mode DMABCRH DMABCRH FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Initial value Read/Write Channel 0A Data Transfer Acknowledge Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 0B Data Transfer Acknowledge Clearing of selected internal interrupt source at time of DMA transfer is disabled...
Page 562 Short address mode DMABCRL DMABCRL DTE1B DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Initial value Read/Write Channel 0A Data Transfer Interrupt Enable Transfer end interrupt disabled Transfer end interrupt enabled Channel 0B Data Transfer Interrupt Enable Transfer end interrupt disabled Transfer end interrupt enabled Channel 1A Data Transfer Interrupt Enable Transfer end interrupt disabled...
Page 563 DTCER—DTC Enable Register H'FF28 to H'FF2F DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value Read/Write DTC Activation Enable DTC activation by interrupt is disabled [Clearing conditions] • When data transfer ends with the DISEL bit set to 1 •...
Page 564 DTVECR—DTC Vector Register H'FF30 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value Read/Write R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) R/(W) Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing conditions] •...
Page 565 INTCR—Interrupt Control Register H'FF31 Interrupt Controller — — INTM1 INTM0 NMIEG — — — Initial value — — — — — Read/Write NMI Edge Select Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input Interrupt Control Mode 1 and 0 Interrupt Control...
Page 566 ISR—IRQ Status Register H'FF34 Interrupt Controller IRQ15F IRQ14F IRQ13F IRQ12F IRQ11F IRQ10F IRQ9F IRQ8F Initial value R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * Read/Write IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value R/(W) *...
Page 567 SBYCR—Standby Control Register H'FF3A System Control SSBY — — STS3 STS2 STS1 STS0 Initial value — — Read/Write Standby Timer Select 3 to 0 Reserved Reserved Reserved Reserved Reserved Standby time = 64 states Standby time = 512 states Standby time = 1,024 states Standby time = 2,048 states Standby time = 4,096 states Standby time = 16,384 states...
Page 568 SCKCR—System Clock Control Register H'FF3B System Control PSTOP — — — STCS SCK2 SCK1 SCK0 Initial value Read/Write — — System Clock Select 2 to 0 1/16 1/32 — Setting prohibited Frequency Multiplication Factor Switching Mode Select 0 Specified multiplication factor is valid after transition to software standby mode Specified multiplication factor is valid immediately after STC bits are rewritten...
Page 569 SYSCR—System Control Register H'FF3D System Control — — MACS — FLSHE — EXPE RAME Initial value —* Read/Write — RAM Enable 0 On-chip RAM disabled On-chip RAM enabled External Bus Mode Enable 0 External bus disabled External bus enabled Flash Memory Control Register Enable 0 Flash memory control registers are not selected for area H'FFFFC8 to H'FFFFCB Flash memory control registers are selected for...
Page 570 MSTPCRH—Module Stop Control Register H H'FF40 Power-Down State MSTPCRL—Module Stop Control Register L H'FF41 Power-Down State MSTPCRH MSTPCRL Initial value Read/Write All-module-clocks-stop mode enable Specify Module Stop Mode All-module-clocks-stop mode disabled Module stop mode cleared All-module-clocks-stop mode enabled Module stop mode set Correspondence between MSTP Bits and On-Chip Supporting Functions Register Module...
Page 571 PLLCR—PLL Control Register H'FF45 Clock Pulse Generator — — — — — — STC1 STC0 Initial value — — — — — Read/Write Frequency multiplication factor × 1 × 2 × 4 Setting prohibited...
Page 572 PCR—PPG Output Control Register H'FF46 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value Read/Write Pulse Output Group 0 Output Trigger Select 0 TPU channel 0 compare match TPU channel 1 compare match TPU channel 2 compare match TPU channel 3 compare match Pulse Output Group 1 Output Trigger Select 0 TPU channel 0 compare match TPU channel 1 compare match...
Page 573 PMR—PPG Output Mode Register H'FF47 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV Initial value Read/Write Group n Non-Overlap Normal operation in pulse output group 0 (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group n (1 output and 0 output can be performed independently at compare match A and B in the selected TPU channel)
Page 574 NDERH—Next Data Enable Register H H'FF48 NDERL—Next Data Enable Register L H'FF49 NDERH NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value Read/Write Next Data Enable 0 Pulse outputs PO15 to PO8 are disabled Pulse outputs PO15 to PO8 are enabled NDERL NDER7 NDER6...
Page 575 PODRH—Output Data Register H H'FF4A PODRL—Output Data Register L H'FF4B PODRH POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Holds output data when pulse output is used PODRL POD7 POD6 POD5 POD4...
Page 576 NDRH—Next Data Register H H'FF4C (FF4E) 1. When pulse output group output triggers are the same a. Address: H'FF4C NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value Read/Write Holds next data for pulse output groups 3 and 2 b.
Page 577 NDRL—Next Data Register L H'FF4D (FF4F) 1. When pulse output group output triggers are the same a. Address: H'FF4D NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value Read/Write Holds next data for pulse output groups 1 and 0 b.
Page 578 PORT1—Port 1 Register H'FF50 Port 1 —* —* —* —* Initial value —* —* —* —* Read/Write State of port 1 pins Note: * Determined by the state of pins P17 to P10. PORT2—Port 2 Register H'FF51 Port 2 Initial value —* —* —*...
Page 579 PORT4—Port 4 Register H'FF53 Port 4 —* —* —* —* Initial value —* —* —* —* Read/Write State of port 4 pins Note: * Determined by the state of pins P47 to P40. PORT5—Port 5 Register H'FF54 Port 5 Initial value —* —* —*...
Page 580 PORT7—Port 7 Register H'FF56 Port 7 — — —* —* Initial value —* —* —* —* Read/Write — — State of port 7 pins Note: * Determined by the state of pins P75 to P70. PORT8—Port 8 Register H'FF57 Port 8 —...
Page 581 PORTB—Port B Register H'FF5A Port B —* —* —* —* Initial value —* —* —* —* Read/Write State of port B pins Note: * Determined by the state of pins PB7 to PB0. PORTC—Port C Register H'FF5B Port C Initial value —* —* —*...
Page 582 PORTE—Port E Register H'FF5D Port E —* —* —* —* Initial value —* —* —* —* Read/Write State of port E pins Note: * Determined by the state of pins PE7 to PE0. PORTF—Port F Register H'FF5E Port F Initial value —* —* —*...
Page 583 P1DR—Port 1 Data Register H'FF60 Port 1 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR Initial value Read/Write Stores output data for port 1 pins (P17 to P10) P2DR—Port 2 Data Register H'FF61 Port 2 P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR...
Page 584 P6DR—Port 6 Data Register H'FF65 Port 6 — — P65DR P64DR P63DR P62DR P61DR P60DR Initial value Read/Write — — Stores output data for port 6 pins (P65 to P60) P7DR—Port 7 Data Register H'FF66 Port 7 — — P75DR P74DR P73DR P72DR...
Page 585 PBDR—Port B Data Register H'FF6A Port B PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value Read/Write Stores output data for port B pins (PB7 to PB0) PCDR—Port C Data Register H'FF6B Port C PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR...
Page 586 PFDR—Port F Data Register H'FF6E Port F PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR Initial value Read/Write Stores output data for port F pins (PF7 to PF0) PGDR—Port G Data Register H'FF6F Port G — PG6DR PG5DR PG4DR PG3DR PG2DR PG1DR PG0DR...
Page 587 PHDDR—Port H Data Direction Register H'FF74 Port H — — — — PH3DDR PH2DDR PH1DDR PH0DDR Initial value Read/Write — — — — Specify input or output for individual port H pins...
Page 588 SMR0—Serial Mode Register 0 H'FF78 SCI0 STOP CKS1 CKS0 Initial value Read/Write Clock Select 0 ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode 0 Multiprocessor function disabled Multiprocessor format selected Stop Bit Length 0 1 stop bit 2 stop bits Parity Mode 0 Even parity Odd parity...
Page 589 SMR0—Serial Mode Register 0 H'FF78 Smart Card Interface 0 BCP1 BCP0 CKS1 CKS0 Initial value Read/Write Clock Select 0 ø clock ø/4 clock ø/16 clock ø/64 clock Basic Clock Pulse BCP1 BCP0 Basic Clock Pulse 32 clock periods 64 clock periods 372 clock periods 256 clock periods Parity Mode...
Page 590 BRR0—Bit Rate Register 0 H'FF79 SCI0, Smart Card Interface 0 Initial value Read/Write Sets the serial transmit/receive bit rate Note: For details see section 12.2.8, Bit Rate Register (BRR), in the H8S/2678 Series Hardware Manual.
Page 591 SCR0—Serial Control Register 0 H'FF7A SCI0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable Asynchronous Internal clock/SCK pin functions as mode I/O port Synchronous Internal clock/SCK pin functions as mode serial clock output Asynchronous Internal clock/SCK pin functions as mode clock output Synchronous...
Page 592 SCR0—Serial Control Register 0 H'FF7A Smart Card Interface 0 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable (In smart card interface mode, with bit 7 of SMR set to 1) SCMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 See the SCI specification...
Page 593 TDR0—Transmit Data Register 0 H'FF7B SCI0, Smart Card Interface 0 Initial value Read/Write Stores data for serial transmission...
Page 594 SSR0—Serial Status Register 0 H'FF7C SCI0 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition]...
Page 595 SSR0—Serial Status Register 0 H'FF7C Smart Card Interface 0 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received...
Page 596 RDR0—Receive Data Register 0 H'FF7D SCI0, Smart Card Interface 0 Initial value Read/Write Stores received serial data SCMR0—Smart Card Mode Register 0 H'FF7E SCI0, Smart Card Interface 0 — — — — SDIR SINV — SMIF Initial value Read/Write — —...
Page 597 SMR1—Serial Mode Register 1 H'FF80 SCI1 STOP CKS1 CKS0 Initial value Read/Write Clock Select 0 ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode 0 Multiprocessor function disabled Multiprocessor format selected Stop Bit Length 0 1 stop bit 2 stop bits Parity Mode 0 Even parity Odd parity...
Page 598 SMR1—Serial Mode Register 1 H'FF80 Smart Card Interface 1 BCP1 BCP0 CKS1 CKS0 Initial value Read/Write Clock Select 0 ø clock ø/4 clock ø/16 clock ø/64 clock Basic Clock Pulse BCP1 BCP0 Basic Clock Pulse 32 clock periods 64 clock periods 372 clock periods 256 clock periods Parity Mode...
Page 599 BRR1—Bit Rate Register 1 H'FF81 SCI1, Smart Card Interface 1 Initial value Read/Write Sets the serial transmit/receive bit rate Note: For details see section 12.2.8, Bit Rate Register (BRR), in the H8S/2678 Series Hardware Manual.
Page 600 SCR1—Serial Control Register 1 H'FF82 SCI1 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable Asynchronous Internal clock/SCK pin functions as mode I/O port Synchronous Internal clock/SCK pin functions as mode serial clock output Asynchronous Internal clock/SCK pin functions as mode clock output Synchronous...
Page 601 SCR1—Serial Control Register 1 H'FF82 Smart Card Interface 1 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable (In smart card interface mode, with bit 7 of SMR set to 1) SCMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 See the SCI specification...
Page 602 TDR1—Transmit Data Register 1 H'FF83 SCI1, Smart Card Interface 1 Initial value Read/Write Stores data for serial transmission...
Page 603 SSR1—Serial Status Register 1 H'FF84 SCI1 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition]...
Page 604 SSR1—Serial Status Register 1 H'FF84 Smart Card Interface 1 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received...
Page 605 RDR1—Receive Data Register 1 H'FF85 SCI1, Smart Card Interface 1 Initial value Read/Write Stores received serial data SCMR1—Smart Card Mode Register 1 H'FF86 SCI1, Smart Card Interface 1 — — — — SDIR SINV — SMIF Initial value Read/Write — —...
Page 606 SMR2—Serial Mode Register 2 H'FF88 SCI2 STOP CKS1 CKS0 Initial value Read/Write Clock Select 0 ø clock ø/4 clock ø/16 clock ø/64 clock Multiprocessor Mode 0 Multiprocessor function disabled Multiprocessor format selected Stop Bit Length 0 1 stop bit 2 stop bits Parity Mode 0 Even parity Odd parity...
Page 607 SMR2—Serial Mode Register 2 H'FF88 Smart Card Interface 2 BCP1 BCP0 CKS1 CKS0 Initial value Read/Write Clock Select 0 ø clock ø/4 clock ø/16 clock ø/64 clock Basic Clock Pulse BCP1 BCP0 Basic Clock Pulse 32 clock periods 64 clock periods 372 clock periods 256 clock periods Parity Mode...
Page 608 BRR2—Bit Rate Register 2 H'FF89 SCI2, Smart Card Interface 2 Initial value Read/Write Sets the serial transmit/receive bit rate Note: For details see section 12.2.8, Bit Rate Register (BRR), in the H8S/2678 Series Hardware Manual.
Page 609 SCR2—Serial Control Register 2 H'FF8A SCI2 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable Asynchronous Internal clock/SCK pin functions as mode I/O port Synchronous Internal clock/SCK pin functions as mode serial clock output Asynchronous Internal clock/SCK pin functions as mode clock output Synchronous...
Page 610 SCR2—Serial Control Register 2 H'FF8A Smart Card Interface 2 MPIE TEIE CKE1 CKE0 Initial value Read/Write Clock Enable (In smart card interface mode, with bit 7 of SMR set to 1) SCMR SCR Setting SCK Pin Function SMIF C/A, GM CKE1 CKE0 See the SCI specification...
Page 611 TDR2—Transmit Data Register 2 H'FF8B SCI2, Smart Card Interface 2 Initial value Read/Write Stores data for serial transmission...
Page 612 SSR2—Serial Status Register 2 H'FF8C SCI2 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition]...
Page 613 SSR2—Serial Status Register 2 H'FF8C Smart Card Interface 2 TDRE RDRF ORER TEND MPBT Initial value Read/Write R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Multiprocessor Bit Transfer Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit [Clearing condition] When data with a 0 multiprocessor bit is received...
Page 614 RDR2—Receive Data Register 2 H'FF8D SCI2, Smart Card Interface 2 Initial value Read/Write Stores received serial data SCMR2—Smart Card Mode Register 2 H'FF8E SCI2, Smart Card Interface 2 — — — — SDIR SINV — SMIF Initial value Read/Write — —...
Page 615 ADDRAH—A/D Data Register AH H'FF90 A/D Converter ADDRAL—A/D Data Register AL H'FF91 A/D Converter ADDRBH—A/D Data Register BH H'FF92 A/D Converter ADDRBL—A/D Data Register BL H'FF93 A/D Converter ADDRCH—A/D Data Register CH H'FF94 A/D Converter ADDRCL—A/D Data Register CL H'FF95 A/D Converter ADDRDH—A/D Data Register DH H'FF96...
Page 616 ADCSR—A/D Control/Status Register H'FF98 A/D Converter ADIE ADST SCAN Initial value R/W * Read/Write Channel Select Note: CH2, CH1, and CH0 are used in combination with bit 2 (CH3) in ADCR. See ADCR—A/D Control Register (H'FF99) for details. Clock Select Note: CKS is used in combination with bit 3 (CKS1) in ADCR.
Page 617 ADCR—A/D Control Register H'FF99 A/D Converter TRGS1 TRGS0 — — CKS1 — — Initial value Read/Write — — — — Channel Select Selects the analog input channel(s). Make the input channel setting when conversion is halted (ADST = 0). Channel Selection Description Single Mode Scan Mode...
Page 618 DADR0—D/A Data Register 0 H'FFA4 D/A Converter DADR1—D/A Data Register 1 H'FFA5 D/A Converter Initial value Read/Write Stores data for D/A conversion DACR01—D/A Control Register 01 H'FFA6 D/A Converter DAOE1 DAOE0 — — — — — Initial value Read/Write — —...
Page 619 DADR2—D/A Data Register 2 H'FFA8 D/A Converter DADR3—D/A Data Register 3 H'FFA9 D/A Converter Initial value Read/Write Stores data for D/A conversion DACR23—D/A Control Register 23 H'FFAA D/A Converter DAOE1 DAOE0 — — — — — Initial value Read/Write — —...
Page 620 TCR0—Timer Control Register 0 H'FFB0 8-Bit Timer Channel 0 TCR1—Timer Control Register 1 H'FFB1 8-Bit Timer Channel 1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value Read/Write Clock Select Clock input disabled Internal clock: count at falling edge of ø/8 Internal clock: count at falling edge of ø/64 Internal clock: count at falling...
Page 621 TCSR0—Timer Control/Status Register 0 H'FFB2 8-Bit Timer Channel 0 TCSR1—Timer Control/Status Register 1 H'FFB3 8-Bit Timer Channel 1 TCSR0 CMFB CMFA ADTE Initial value R/(W)* R/(W)* R/(W)* Read/Write TCSR1 CMFB CMFA — Initial value R/(W)* R/(W)* R/(W)* — Read/Write Output Select No change when compare match A occurs 0 is output when compare match A occurs 1 is output when compare match A occurs...
Page 622 TCORA0—Time Constant Register A0 H'FFB4 8-Bit Timer Channel 0 TCORA1—Time Constant Register A1 H'FFB5 8-Bit Timer Channel 1 TCORA0 TCORA1 Initial value Read/Write TCORB0—Time Constant Register B0 H'FFB6 8-Bit Timer Channel 0 TCORB1—Time Constant Register B1 H'FFB7 8-Bit Timer Channel 1 TCORB0 TCORB1 Initial value...
Page 623 OVF is cleared automatically by an internal reset. The method for writing to TCSR is different from that for general registers to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access, in the H8S/2678 Series Hardware Manual.
Page 624 Notes: * Can only be written with 0, to clear the flag. The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting. For details see section 11.2.4, Notes on Register Access, in the H8S/2678 Series Hardware Manual.
Page 625 TSTR—Timer Start Register H'FFC0 — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value Read/Write — — Counter start 0 TCNTn count operation is stopped TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained.
Page 626 FLMCR1—Flash Memory Control Register 1 H'FFC8 Flash Memory (F-ZTAT Version Only) Initial value Read/Write Program 0 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase 0 Erase mode cleared Transition to erase mode [Setting condition] When FWE = 1, SWE = 1,...
Page 627 Power on reset or hardware standby mode An error has occurred during flash memory programming/erasing Flash memory program/erase protection (error protection) is enabled [Setting condition] See section 18.10.3, Error Protection, in the H8S/2678 Series Hardware Manual. EBR1—Erase Block Register 1 H'FFCA Flash Memory EBR2—Erase Block Register 2...
Page 628 TCR0—Timer Control Register 0 H'FFD0 TPU0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write Time Prescaler Internal clock: count on ø/1 Internal clock: count on ø/4 Internal clock: count on ø/16 Internal clock: count on ø/64 External clock: count on TCLKA pin input External clock: count on TCLKB pin input External clock: count on TCLKC pin input External clock: count on TCLKD pin input...
Page 629 TMDR0—Timer Mode Register 0 H'FFD1 TPU0 — — Initial value Read/Write — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 — *: Don’t care Notes: 1.
Page 630 TIOR0H—Timer I/O Control Register 0H H'FFD2 TPU0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR0A I/O Control TGR0A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match 1 0 0 Output disabled...
Page 631 TIOR0L—Timer I/O Control Register 0L H'FFD3 TPU0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value Read/Write TGR0C I/O Control TGR0C Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match 1 0 0 Output disabled...
Page 632 TIER0—Timer Interrupt Enable Register 0 H'FFD4 TPU0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value Read/Write — — TGR Interrupt Enable A Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB)
Page 633 TSR0—Timer Status Register 0 H'FFD5 TPU0 — — — TCFV TGFD TGFC TGFB TGFA Initial value Read/Write — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* TGRA Input Capture/Output Compare Flag [Clearing conditions] • When DTC is activated by TGIA interrupt and DISEL bit in DTC’s MRB register is 0 •...
Page 634 TCNT0—Timer Counter 0 H'FFD6 TPU0 Initial value Read/Write Up-counter TGR0A—Timer General Register 0A H'FFD8 TPU0 TGR0B—Timer General Register 0B H'FFDA TPU0 TGR0C—Timer General Register 0C H'FFDC TPU0 TGR0D—Timer General Register 0D H'FFDE TPU0 Initial value Read/Write...
Page 635 TCR1—Timer Control Register 1 H'FFE0 TPU1 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: count on ø/1 Internal clock: count on ø/4 Internal clock: count on ø/16 Internal clock: count on ø/64 External clock: count on TCLKA pin input External clock: count on TCLKB pin input Internal clock: count on ø/256...
Page 636 TMDR1—Timer Mode Register 1 H'FFE1 TPU1 — — — — Initial value Read/Write — — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 637 TIOR1—Timer I/O Control Register 1 H'FFE2 TPU1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR1A I/O Control TGR1A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match 1 0 0 Output disabled...
Page 638 TIER1—Timer Interrupt Enable Register 1 H'FFE4 TPU1 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB)
Page 639 TSR1—Timer Status Register 1 H'FFE5 TPU1 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* TGRA Input Capture/Output Compare Flag [Clearing conditions] • When DTC is activated by TGIA interrupt and DISEL bit in DTC’s MRB register is 0 •...
Page 640 TCNT1—Timer Counter 1 H'FFE6 TPU1 Initial value Read/Write Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR1A—Timer General Register 1A H'FFE8 TPU1...
Page 641 TCR2—Timer Control Register 2 H'FFF0 TPU2 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value Read/Write — Time Prescaler Internal clock: count on ø/1 Internal clock: count on ø/4 Internal clock: count on ø/16 Internal clock: count on ø/64 External clock: count on TCLKA pin input External clock: count on TCLKB pin input External clock: count on TCLKC pin input...
Page 642 TMDR2—Timer Mode Register 2 H'FFF1 TPU2 — — — — Initial value Read/Write — — — — Mode Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 —...
Page 643 TIOR2—Timer I/O Control Register 2 H'FFF2 TPU2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value Read/Write TGR2A I/O Control TGR2A Output disabled is output Initial output is 0 output at compare match compare 0 output register 1 output at compare match Toggle output at compare match 1 0 0 Output disabled...
Page 644 TIER2—Timer Interrupt Enable Register 2 H'FFF4 TPU2 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value Read/Write — — — TGR Interrupt Enable A Interrupt request (TGIA) by TGFA bit disabled Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B Interrupt request (TGIB) by TGFB bit disabled Interrupt request (TGIB)
Page 645 TSR2—Timer Status Register 2 H'FFF5 TPU2 TCFD — TCFU TCFV — — TGFB TGFA Initial value Read/Write — R/(W)* R/(W)* — — R/(W)* R/(W)* TGRA Input Capture/Output Compare Flag [Clearing conditions] • When DTC is activated by TGIA interrupt and DISEL bit in DTC’s MRB register is 0 •...
Page 646 TCNT2—Timer Counter 2 H'FFF6 TPU2 Initial value Read/Write Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR2A—Timer General Register 2A H'FFF8 TPU2...

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Hitachi H8S/2678 Series Reference Manual

Section 1 Overview

Section 2 MCU Operating Modes

Section 3 Exception Handling and Interrupt Controller

Section 4 Bus Controller

Section 5 I/O Ports

Section 6 Supporting Module Block Diagrams

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Summary of Contents for Hitachi H8S/2678 Series