Timing Of Host Interface (Pio) - Toshiba SR-C8002 Product Specification

6.2.2.Timing of Host Interface (PIO)

Figure 9 shows the Host Interface Timings
Address valid*1
DIOR-/DIOW-*1
Write data valid*1
Read data valid*1
IOCS16-*1
IORDY
*1: In all timing diagrams, the low line indicator negated, and the upper line
indicators asserted.
PIO timing parameters min (ns) max (ns)
t0 Cycle time
t1 Address valid to DIOR/DIOW-setup
t2 DIOR/DIOW-pulse wide
t2i DIOR/DIOW-recovery time
t3 DIOW-data setup
t4 DIOW-data hold
t5 DIOR-data setup
t6 DIOR-data hold
t6Z DIOR-data tristate
t7 Addr valid to IOCS 16-assertion
t8 Addr valid to IOCS 16-negation
t9 DIOR/DIOW-to address valid hold
tRD Read Data Valid to IORDY active
tA IORDY setup
tB IORDY pulse wide
t1
t7
tA
Figure 9 Host Interface Timing (PIO Mode4)
t0
t2
t3
t5
tB
tRD
Min Time (ns)
120
25
70
25
20
10
20
5
10
0
14/24
t9
t2i
t4
t6Z
t6
t8
Max Time (ns)
30
30
30
35
1250
SR-C8002 Rev.1.0