Page 1 TOSHIBA Original CMOS 32-Bit Microcontroller TLCS-900/H1 Series TMP92CF30FG Semiconductor Company...
Page 2 Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, “Notes and Restrictions”.
Page 3: Outline And Features
TMP92CF30 CMOS 32-Bit Microcontroller TMP92CF30FG Outline and Features The TMP92CF30 is a high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data. The TMP92CF30FG is housed in a 176-pin QFP package. (1) CPU: 32-bit CPU (High-speed 900/H1 CPU) •...
Page 4 TMP92CF30 (11) I S (Inter-IC Sound) interface: 1 channel • S bus mode selectable (Master, transmission only) • Data Format is supported Left/Right Justify • 128-byte FIFO buffer (64 bytes × 2) (12) SDRAM controller:1 channel • Supports 16-Mbit, 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit SDR (Single-data-rate) SDRAM •...
Page 5 TMP92CF30 (24) SPI controller: 1 channel • Supports SPI mode of SD card and MMC card • Built-in FIFO buffer of 32 bytes to each Input/Output (25) Product/Sum calculation: 1 channel • Supports calculation 32 × 32 + 64 = 64 bits, 64 − 32 × 32 = 64 bits and 32 × 32 − 64 =64 bits •...
Page 6 TMP92CF30 DVCC3A [8] (AN0 to AN1)PG0 to PG1 10-bit 6ch 900/H1 CPU (AN2, MX)PG2 DVCC1A [4] (AN3, MY, ADTRG)PG3 DVCC1B [1] Converter (AN4, AN5) PG4 to PG5 DVSSCOM [8] AVCC, AVSS DVCC1C [1] VREFH, VREFL DVSS1C [1] (PX, INT4)P96 Touch screen H-OSC (PY)P97 (TSI)
Page 7: Pin Assignment And Pin Functions
TMP92CF30 Pin Assignment and Pin Functions The assignment of input/output pins for TMP92CF30, their names and functions are as follows; Pin Assignment Diagram (Top View) Figure 2.1.1 shows the pin assignment of the TMP92CF30. VREFH P71, WRLL NDRE VREFL P70, AVCC PC6, EA28, SPCLK...
Page 8: Pin Names And Functions
TMP92CF30 Pin names and Functions The names of the input/output pins and their functions are described below. Table 2.2.1 Pin names and functions (1/6) Number Pin name Functions of Pins D0 to D7 Data: Data bus D0 to D7 P10 to P17 Port 1: I/O port input or output specifiable in units of bits D8 to D15 Data: Data bus D8 to D15...
Page 9 TMP92CF30 Table 2.2.1 Pin names and functions (2/6) Number Pin name Functions of Pins Output Port 86: Output port CSZD Output Expanded address ZD: Outputs “Low” when address is within specified address area Output Chip select for NAND Flash 0: Outputs “Low” when NAND Flash 0 is enable Output Port 87: Output port CSXB...
Page 10 TMP92CF30 Table 2.2.1 Pin names and functions (3/6) Number Pin name Functions of Pins Port F0: I/O port I2S0CKO Output Outputs clock for I Port F1: I/O port I2S0DO Output Outputs data for I Port F2: I/O port I2S0WS Output Outputs word select signal for I Output Port F7: Output port...
Page 11 TMP92CF30 Table 2.2.1 Pin names and functions (4/6) Number Pin name Functions of Pins PK0 to PK7 Output Port K0 to PK7: Output port PL0 to PL7 Port L0 to L7: I/O port D16 to D23 Output Data bus D16 to D23 Output Port M1: Output port TA1OUT...
Page 12 TMP92CF30 Table 2.2.1 Pin names and functions (5/6) Number Pin name Functions of Pins Port R0: I/O port SPDI Input Data input pin for SD card Port R1: I/O port SPDO Output Data output pin for SD card Port R2: I/O port SPCS Output Chip select signal for SD card...
Page 13 TMP92CF30 Table 2.2.1 Pin names and functions (6/6) Number Pin name Functions of Pins USB-data connecting pin D+, D− Connect pull-up(DVCC3A) or pull-down resistor to both pins to avoid through current when USB is not in use. Input Non-maskable interrupt pin. Operation mode;...
Page 14: Operation
TMP92CF30 Operation This section describes the basic components, functions and operation of the TMP92CF30. The TMP92CF30 contains an advanced high-speed 32-bit CPU (TLCS-900/H1 CPU) 3.1.1 CPU Outline The TLCS-900/H1 CPU is a high-speed, high-performance CPU based on the TLCS-900/L1 CPU. The TLCS-900/H1 CPU has an expanded 32-bit internal data bus to process Instructions more quickly.
Page 15 TMP92CF30 3.1.2 Reset Operation When resetting the TMP92CF30 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the input Low for at least 20 system clocks (32µs at RESET X1=10MHz).
Page 16 TMP92CF30 Write Read Figure 3.1.1 TMP92CF30 Reset timing chart 2009-06-12 92CF30-14...
Page 17 TMP92CF30 This LSI has the restriction for the order of supplying power. Be sure to supply external 3.3V power with 1.5V power is supplied. When Powering off When Powering on DVCC1A DVCC1B 1.5V DVCC1C Power Power should fall and Power should rise and stabilizes within 100 ms.
Page 18: Operation Mode
TMP92CF30 3.1.3 Setting of AM0 and AM1 Set AM1 and AM0 pins as shown in Table 3.1.2 according to system usage. Table 3.1.2 Operation Mode Setup Table Mode Setup input pin Operation Mode RESET 16-bit external bus starting 32-bit external bus starting Test mode (Prohibit to set) Test mode (Prohibit to set) 2009-06-12...
Page 19: Memory Map
TMP92CF30 Memory Map Figure 3.2.1 is a memory map of the TMP92CF30. 000000H Internal I/O Direct area(n) (8 Kbyte) 000100H 64Kbyte area 001FF0H (nn) 002000H Internal RAM 010000H (128 Kbyte) 021FFFH Don’t access area (Note2) 046000H (Internal Back Up RAM 16Kbyte) 04A000H External memory 16Mbyte area...
Page 20 TMP92CF30 3.3 Differences between the TMP92CZ26A/CF26A and the TMP92CF30 The TMP92CF30 is a lower pin-count version of the TMP92CF26A with fewer functions (there are some added functions). Sections 3.3.1 through 3.3.13 describe the functions that are deleted or newly added to the TMP29CF30.
Page 21 TMP92CF30 3.3.3 Port Pins Deleted In the TMP92CF30, the following port pins are deleted as opposed to the TMP92CZ26A/CF26A. And TMP92CF30 support the external 32bit bus function except for access to SDRAM. Added: External 32bit bus function added. (However, if an ICE using the TMP92CF26A is used to development and debugging, it is possible only to operate by 16 bit bus mode.) Deleted:...
Page 22 TMP92CF30 3.3.5 One of the I S Channels Deleted and I S Function Modified [Deleted function] The TMP92CF30 has only one I S channel (Channel 0), whereas the TMP92CZ26A/CF26A has Channels 0 and 1. [Modified function] The monophonic data output format of the I S function is modified as shown below.
Page 23 TMP92CF30 NMI Pin Added 3.3.6 In the TMP92CF30, the pin is newly added. This pin must always be fixed to high TEST level. TMP92CF30 is added the external 32bit bus function. The newly added the external 32bit bus function cannot be supported development tools using TMP92CF26A. Please use NMI pin for BREAK function etc, if ROM emulator is used for development.
Page 24 TMP92CF30 3.3.10 LCD Controller Functions Added and Deleted [Deleted function] The TMP92CF30 does not support the LCD controller, which is available in the TMP92CZ26A/CF26A. 3.3.11 SIO Channel Added and SIO Function Modified [Added function] In the TMP92CZ26A/CF26A only one SIO channel is available, whereas the TMP92CF30 has two SIO channels.
Page 25 TMP92CF30 3.3.12 Interrupt Sources Deleted and Modified [Deleted function] As the number of I S channels is reduced from two channels to one channel, the corresponding interrupt vector is deleted. [Modified function] As the number of SIO channels is increased from one channel to two channels, the interrupt vectors for SIO1 serial receive end and SIO1 serial transmission end are added in the TMP92CF30.
Page 26 TMP92CF30 Table 3.3.1 summarizes the differences between the TMP92CZ26A and the TMP92CF30. For details, refer to the chapter on each functional block. Table 3.3.1 Differences between the TMP92CZ26A and the TMP92CF30 Item TMP92CZ26A TMP92CF30 Note 288 KB 144 KB 8 KB (BOOT) None Package FBGA228-P-1515-0.80A...
Page 27 TMP92CF30 Clock Function and Standby Function The TMP92CF30 contains (1) clock gear, (2) clock doubler (PLL), (3) standby controller and (4) noise reduction circuits. They are used for low-power, low-noise systems. This chapter is organized as follows: 3.4.1 Block diagram of system clock 3.4.2 SFR 3.4.3 System clock controller 3.4.4 Clock doubler (PLL)
Page 28 TMP92CF30 The clock operating modes are as follows: (a) PLL-OFF Mode (X1, X2 pins only), (b) PLL-ON Mode (X1, X2, and PLL). Figure 3.4.1 shows a transition figure. Reset /16) OSCH release Reset instruction IDLE2 mode instruction interrupt (I/O operate) STOP mode PLL-OFF mode interrupt...
Page 29 TMP92CF30 3.4.1 Block diagram of system clock SYSCR0<WUEF> SYSCR2<WUPTM1:0> ÷4 φT0 Warming up timer (High/Low frequency oscillator circuit) φT0TMR ÷2 ÷2 Lock up timer ÷8 (PLL) SYSCR0<XTEN > SYSCR0<PRCK> PLLCR1<PLLON>, PLLCR0<LUPFG> Low frequency Oscillator circuit fc/2 fc/4 fc/8 Clock Doubler0 ÷2 fc/16 (PLL0)
Page 30: High Frequency
TMP92CF30 TMP92CF30 has two PLL circuits: one is for CPU (PLL0) and the other for USB (PLL1). Each PLL can be controlled independently. Frequency of external oscillator is 6 to 10MHz. Don’t connect oscillator more than 10MHz. When clock is input by using external oscillator, range of input frequency is 6 to 10MHz.
Page 31 TMP92CF30 3.4.2 SYSCR0 bit Symbol XTEN USBCLK1 USBCLK0 WUEF PRCK (10E0H) Read/write Reset State Function Select the clock of Warm-up Select USB(f -frequency Timer Prescaler oscillator 00:Disable clock 0: Write circuit (fs) 01: Reserved 0: f Don’t care 10: X1USB 1: f 0: Stop Note3...
Page 32 TMP92CF30 − EMCCR0 Bit symbol PROTECT EXTIN DRVOSCH DRVOSCL (10E3H) Read/Write Reset State Function Protect Always fc oscillator fs oscillator 1: External flag write “0”. drive ability drive ability clock 0: OFF 1: NORMAL 1: NORMAL 0: WEAK 0: WEAK 1: ON EMCCR1 Bit symbol...
Page 33 TMP92CF30 FCSEL LUPFG PLLCR0 bit symbol (10E8H) Read/Write Reset State Function Select Lock-up fc-clock timer 0: f Status flag OSCH 1: f 0: not end 1: end Note: Ensure that the logic of PLLCR0<LUPFG> is different from 900/L1’s DFM. PLL0 PLL1 LUPSEL PLLTIMES...
Page 34: System Clock Controller
TMP92CF30 3.4.3 System clock controller The system clock controller generates the system clock signal (f ) for the CPU core and internal I/O. SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of each oscillator. SYSCR1<GEAR2:0> sets the high frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8, fc/16).
Page 35 TMP92CF30 3.4.4 Clock doubler (PLL) PLL0 outputs the f clock signal, which is 12 or 16 times as fast as f . A low-speed OSCH frequency oscillator can be used as external oscillator, even though the internal clock is high-frequency. Since Reset initializes PLL0 to stop status, so setting to PLLCR0 and PLLCR1-register is needed before use.
Page 36 TMP92CF30 The following is an example of settings for PLL0-starting and PLL0 stopping. (Example-1) PLL0-starting PLLCR0 10E8H PLLCR1 10E9H (PLLCR1),1XXXXXXXXB Enables PLL0 operation and starts lock up. LUP: 5,(PLLCR0) Detects end of lock-up Z,LUP (PLLCR0), X1XXXXXXB Changes fc from 10 MHz to 60 MHz. X: Don't care <PLL0>...
Page 37 TMP92CF30 Limitations on the use of PLL0 1. When stopping PLL operation during PLL0 use, execute the following settings in the same order. (PLLCR0),X0XXXXXXB Change the clock f to f OSCH (PLLCR1),0XXXXXXXB Stop PLL0 X: Don't care 2. When shifting to STOP mode during PLL use, execute the following settings in the same order.
Page 38 TMP92CF30 3.4.5 Noise reduction circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator circuit (2) Reduced drivability for low-frequency oscillator circuit (3) Single drive for high-frequency oscillator circuit (4) Runaway prevention using SFR protection register These are set in EMCCR0 to EMCCR2 registers.
Page 39 TMP92CF30 (2) Reduced drivability for low-frequency oscillator circuit (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) XT1 pin Enable oscillation Resonator EMCCR0<DRVOSCL> XT2 pin (Setting method) drivability oscillator reduced writing “0” EMCCR0<DRVOSCL> register. At Reset, <DRVOSCL> is initialized to “1”. (3) Single drive for high-frequency oscillator circuit (Purpose) Remove the need for twin-drives and protect prevent operational errors caused by...
Page 40 TMP92CF30 (4) Runaway prevention using SFR protection register (Purpose) Prevention of program runaway caused by introduction of noise. Write operations to a specified SFR are prohibited so that the program is protected from runaway caused by stopping of the clock or by changes to the memory control register (Memory controller, MMU) which prevent fetch operations.
Page 41 TMP92CF30 3.4.6 Standby controller (1) HALT Modes and Port Drive register When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP Mode, depending on the contents of the SYSCR2<HALTM1:0> register and each pin-status is set according to the PxDR register, as shown below. PxDR bit symbol Px7D...
Page 42 TMP92CF30 The operation of each of the different Halt Modes is described in Table 3.4.4. Table 3.4.4 I/O operation during Halt Modes HALT Mode IDLE2 IDLE1 STOP SYSCR2 <HALTM1:0> Stop CPU, MAC I/O ports Depends on PxDR register setting TMRA, TMRB Available to select SIO,SBI Operation block...
Page 43 TMP92CF30 Table 3.4.5 Source of Halt state clearance and Halt clearance operation Interrupt Enabled Interrupt Disabled Status of Received Interrupt (interrupt level) ≥ (interrupt mask) (interrupt level) < (interrupt mask) HALT mode IDLE2 IDLE1 STOP IDLE2 IDLE1 STOP × × −...
Page 44 TMP92CF30 (Example - releasing IDLE1 Mode) An INT0 interrupt clears the Halt state when the device is in IDLE1 Mode. Address 8200H (PCFC), 02H ; Sets PC1 to INT0 interrupt. 8203H (IIMC0), 00H ; Select INT0 interrupt rising edge. 8206H (INTE0), 06H ;...
Page 45: Idle2 Mode
TMP92CF30 (3) Operation a. IDLE2 Mode In IDLE2 Mode, only specific internal I/O operations, as designated by the IDLE2 Setting Register, can take place. Instruction execution by the CPU stops. Figure 3.4.7 illustrates an example of the timing for clearance of the IDLE2 Mode Halt state by an interrupt.
Page 46 TMP92CF30 STOP Mode When STOP Mode is selected, all internal circuits stop, including the internal oscillator. After STOP Mode has been cleared system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. Figure 3.4.9 illustrates the timing for clearance of the STOP Mode Halt state by an interrupt.
Page 47 TMP92CF30 Table 3.4.7 Input Buffer State Table Input Buffer State In HALT mode (IDLE2/1/STOP) Input Function When the CPU is operating <PxDR> = 1 <PxDR> = 0 Port Name Name During Reset When Used as When Used as When Used as When Used as When Used as When Used as...
Page 48 TMP92CF30 Table 3.4.8 Output buffer State Table (1/2) Output Buffer State In HALT mode (IDLE2/1/STOP) Output Function When the CPU is operating <PxDR> = 1 <PxDR> = 0 Port Name Name During Reset When Used as When Used as When Used as When Used as When Used as When Used as...
Page 49 TMP92CF30 Table 3.4.9 Output buffer state table (2/2) Output Buffer State In HALT mode (IDLE2/1/STOP) Output Function When the CPU is operating <PxDR> = 1 <PxDR> = 0 Port Name During Name Reset When Used as When Used as When Used as When Used as When Used as When Used as...
Page 50 TMP92CF30 Interrupts Interrupts are controlled by the CPU Interrupt Mask Register <IFF2:0> (bits 12 to 14 of the Status Register) and by the built-in interrupt controller. TMP92CF30 has a total of 58 interrupts divided into the following five types: Interrupts generated by CPU: 9 sources •...
Page 51 TMP92CF30 DMA soft start Interrupt processing request Interrupt specified by DMA start vector ? Clear interrupt request flag Interrupt vector calue “V” to HDMA processing flow Start specified read interrupt request F/F clear by HDMA General-purpose interrupt PUSH Data transfer by micro processing PUSH SR<IFF2:0>...
Page 52 TMP92CF30 3.5.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. However, in the case of software interrupts and illegal instruction interrupts generated by the CPU, the CPU skips steps (1) and (3), and executes only steps (2), (4), and (5).
Page 53 TMP92CF30 Table 3.5.1 TMP92CF30 Interrupt Vectors and Micro DMA/HDMA Start Vectors Micro DMA Default Interrupt Source and Source of Vector Address Refer Type /HDMA Start Priority Micro DMA Request Value to Vector Vector Reset or [SWI0] instruction 0000H FFFF00H [SWI1] instruction 0004H FFFF04H Illegal instruction or [SWI2] instruction...
Page 54 TMP92CF30 Micro DMA Default Interrupt Source and Source of Vector Address Refer Type /HDMA Start Priority Micro DMA Request Value to Vector Vector INTADHP: AD most priority conversion end 00C8H FFFFC8H INTAD: AD conversion end 00CCH FFFFCCH INTTC0/INTDMA0: Micro DMA0 /HDMA0 end 00D0H FFFFD0H INTTC1/INTDMA1: Micro DMA1 /HDMA1 end...
Page 55 TMP92CF30 3.5.2 Micro DMA processing In addition to general-purpose interrupt processing, the TMP92CF30 also includes a micro DMA function and HDMA function. This section explains about Micro DMA function. For the HDMA function, please refer 3.7 DMA controller. Micro DMA processing for interrupt requests set by micro DMA is performed at the highest priority level for maskable interrupts (Level 6), regardless of the priority level of the interrupt source.
Page 56 TMP92CF30 (1) Micro DMA operation When an interrupt request is generated by an interrupt source that specified by the micro DMA /HDMA start vector register, and Micro DMA start is specified by DMA selection register, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request.
Page 57 TMP92CF30 Although the control registers used for setting the transfer source and transfer destination addresses are 32 bits wide, this type of register can only output 24-bit addresses. Accordingly, micro DMA can only access 16 Mbytes (The upper 8 bits of a 32-bit address are not valid).
Page 58 TMP92CF30 (2) Soft start function The TMP92CF30 can initiate micro DMA/HDMA either with an interrupt or by using the micro DMA /HDMA soft start function, in which micro DMA or HDMA is initiated by a Write cycle which writes to the register DMAR. Writing “1”...
Page 59: Mode Description
TMP92CF30 (4) Detailed description of the transfer mode register Mode DMAM0 to DMAM7 DMAMn[4:0] Mode Description Execution Time 0 0 0 z z Destination INC mode (DMADn +) ← (DMASn) 5 states ← DMACn - 1 DMACn If DMACn = 0 then INTTCn 0 0 1 z z Destination DEC mode (DMADn -) ←...
Page 60 TMP92CF30 3.5.3 Interrupt Controller Operation The block diagram in Figure 3.5.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 59 interrupts channels there is an interrupt request flag (consisting of a flip-flop), an interrupt priority setting register and a micro DMA /HDMA start vector register.
Page 61 TMP92CF30 Figure 3.5.3 Block Diagram of Interrupt Controller 2009-06-12 92CF30-59...
Page 62 TMP92CF30 (1) Interrupt priority setting registers Symbol Name Address − INT0 − − − − INT0 I0M2 I0M1 I0M0 INTE0 − − enable Always write “0”. INT2 INT1 INT1 & INT2 I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INTE12 enable INT4 INT3 INT3 &...
Page 63 TMP92CF30 Symbol Name Address INTTB01 (TMRB0) INTTB00 (TMRB0) INTTB00 & ITB01C ITB01M2 ITB01M1 ITB01M0 ITB00C ITB00M2 ITB00M1 ITB00M0 INTETB0 INTTB01 enable INTTB11 (TMRB1) INTTB10 (TMRB1) INTTB10 & ITB11C ITB11M2 ITB11M1 ITB11M0 ITB10C ITB10M2 ITB10M1 ITB10M0 INTETB1 INTTB11 enable INTTX0 INTRX0 INTRX0 &...
Page 64 TMP92CF30 Symbol Name Address − INTKEY − − − − INTKEY IKM2 IKM1 IKM0 INTEKEY − − enable Always write “0”. − INTI2S0 − − − − INTI2S0 I I2S0C II2S0M2 II2S0M1 II2S0M0 INTEI2S0 − − enable Always write “0”. INTRSC INTRDY INTRSC &...
Page 65 TMP92CF30 Symbol Name Address INTTC1/INTDMA1 INTTC0/INTDMA0 INTTC0/INTDMA0 & ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 INTETC01 INTTC1/INTDMA1 /IDMA1C /IDMA1M2 /IDMA1M1 /IDMA1M0 /IDMA0C /IDMA0M2 /IDMA0M1 /IDMA0M0 /INTEDMA01 enable INTTC3/INTDMA3 INTTC2/INTDMA2 INTTC2/INTDMA2 & ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0 INTETC23 INTTC3/INTDMA3 /IDMA3C...
Page 66: External Interrupt Control
TMP92CF30 (2) External interrupt control Symbol Name Address I5EDGE I4EDGE I3EDGE I2EDGE I1EDGE I0EDGE I0LE NMIREE Interrupt INT5EDGE INT4EDGE INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 NMI EDGE IIMC0 input mode (Prohibit 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 0: Rising 0:Edge 0: Falling...
Page 67 TMP92CF30 (3) SIO receive interrupt control Symbol Name Address − − IR1LE IR0LE Always Always 0:INTRX1 0:INTRX0 interrupt SIMC (Prohibit write “0” write “0” edge edge mode RMW) (Note) mode mode control 1:INTRX1 1:INTRX0 level level mode mode Note: When using the micro DMA transfer end interrupt, always write “1”. INTRX edge enable Edge detect INTRX “H”...
Page 68 TMP92CF30 (4) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA /HDMA start vector, as given in Table 3.5.1 to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction.
Page 69 TMP92CF30 Symbol Name Address DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA0 DMA0V start 100H vector DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA1 DMA1V start 101H vector DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA2 DMA2V start 102H vector...
Page 70 TMP92CF30 (7) Specification of a micro DMA burst Specifying the micro DMA burst function causes micro DMA transfer, once started, to continue until the value in the transfer counter register reaches “0”. Setting any of the bits in the register DMAB which correspond to a micro DMA channel (as shown below) to “1”...
Page 71 TMP92CF30 (8) Notes The instruction execution unit and the bus interface unit in this CPU operate independently. Therefore, if immediately before an interrupt is generated, the CPU fetches an instruction which clears the corresponding interrupt request flag, the CPU may execute this instruction in between accepting the interrupt and reading the interrupt vector.
Page 72 TMP92CF30 DMAC (DMA Controller) The TMP92CF30 incorporates a DMA controller (DMAC) having six channels. This DMAC can realize data transfer faster than the micro DMA function by the 900/H1 CPU. The DMAC has the following features: 1) Six independent channels of DMA 2) Two types of transfer start requests Hardware request (using an interrupt source connected with the INTC) or software request can be selected for each channel.
Page 73 TMP92CF30 3.6.1 Block Diagram Figure 3.6.1 shows an overall block diagram for the DMAC. Multiplexer Address Bus State SDRAM Controller Source Memory, I/O Address Bus Bus ACK INTC (Interrupt Controller) Data Bus Bus REQ State Interrupt REQ DMAnV DMASn Destination Memory, I/O →DMAC or micro DMA request →Micro DMA source address setting Address Bus...
Page 74 TMP92CF30 3.6.2 SFRs The DMAC has the following SFRs. These registers are connected to the CPU via a 16-bit data bus. (1) HDMASn (DMA Transfer Source Address Setting Register) The HDMASn register is used to set the DMA transfer source address. When the source address is updated by DMA execution, HDMASn is also updated.
Page 75 TMP92CF30 (2) HDMADn (DMA Transfer Destination Address Setting Register) The HDMADn register is used to set the DMA transfer destination address. When the destination address is updated by DMA execution, HDMADn is also updated. HDMAD0 to HDMAD5 have the same configuration. Although the bus sizing function is supported, the address alignment function is not supported.
Page 76 TMP92CF30 (3) HDMACAn (DMA Transfer Count A Setting Register) The HDMACAn register is used to set the number of times a DMA transfer is to be performed by one DMA request. HDMACAn contains 16 bits and can specify up to 65536 transfers (0001H = one transfer, FFFFH = 65535 transfers, 0000H = 65536 transfers).
Page 77 TMP92CF30 (4) HDMACBn (DMA Transfer Count B Setting Register) The HDMACBn register is used to set the number of times a DMA request is to be made. HDMACBn contains 16 bits and can specify up to 65536 requests (0001H = one request, FFFFH = 65535 requests, 0000H = 65536 requests).
Page 78 TMP92CF30 (5) HDMAMn (DMA Transfer Mode Setting Register) The HDMAMn register is used to set the DMA transfer mode. HDMAM0 to HDMAM5 have the same configuration. HDMAMn Register HDMAMn bit Symbol DnM4 DnM3 DnM2 DnM1 DnM0 Read/Write Reset State Function DMA transfer mode Transfer data size 000: Destination INC (I/O →...
Page 79 TMP92CF30 (6) HDMAE (DMA Operation Enable Register) The HDMAE register is used to enable or disable the DMAC operation. Bits 0 to 5 correspond to channels 0 to 5. Unused channels should be set to “0”. HDMAE Register HDMAE bit Symbol DMAE5 DMAE4 DMAE3...
Page 80: Overall Flowchart
TMP92CF30 3.6.3 DMAC Operation Description (1) Overall flowchart Figure 3.6.9 shows a flowchart for DMAC operation when an interrupt (DMA) is requested. Interrupt (DMA) request To general-purpose interrupt or micro DMA processing flow Interrupt specified by DMA start vector? Interrupt request F/F clear &...
Page 81: Operation Timing
TMP92CF30 (2) Bus arbitration The TMP92CF30 includes two controllers (DMA controller and SDRAM controller) that function as bus masters apart from the CPU. These controllers operate independently and assert a bus request as required. The controller that receives a bus acknowledgement acts as the bus master.
Page 82 TMP92CF30 3.6.4 Setting Example This section explains how to set the DMAC using an example. (1) Transferring music data from internal RAM to I S by DMA transfer The 32 Kbytes of data stored in the internal RAM at addresses 2000H to 9FFFH shall be transferred to FIFO-RAM via I S.
Page 83 TMP92CF30 3.6.5 Note In case of using S/W start with HDMA, transmission start is to set to “1” DMAR register. However DMAR register can't be used to confirm flag of transmission end. DMAR register reset to “0” when HDMA release bus occupation once with HDMATR function. We recommend to use HDMACBn register (counter value) to confirm flag of transmission end.
Page 84 TMP92CF30 3.6.6 Considerations for Using More Than One Bus Master In the TMP92CF30, the SDRAM controller and DMA controller may act as the bus master apart from the CPU. Therefore, care must be exercised to enable each of these functions to operate smoothly. To facilitate explanation of DMA operation performed by each bus master, the DMA transfer operation performed by the DMA controller is defined as “HDMA”...
Page 85 TMP92CF30 Sample 1: Calculation example for CPU + HDMA Conditions: CPU operation speed (f : 60 MHz S sampling frequency : 48 kHz (60 MHz/25/50 = 48 kHz) S data transfer bit length : 16 bits DMAC channel 0 used to transfer 5 Kbytes from internal RAM to I Calculation example: DMAC source data read time: Internal RAM data read time...
Page 86 TMP92CF30 Function of ports The TMP92CF30 I/O port pins are shown in Table 3.7.1. In addition to functioning as general-purpose I/O ports, these pins are also used by the internal CPU and I/O functions. Table 3.7.2 lists the I/O registers and their specifications. Table 3.7.1 Port Functions (1/2) (R: PD= with programmable pull-down resistor, U= with pull-up resistor) Number Pin Name for built-in...
Page 87 TMP92CF30 Table 3.7.1 Port Functions (2/2) Number Pin Name for built-in Port Name Pin Name I/O Setting of Pins function − SDRAS , SRLLB Port J Output (Fixed) − SDCAS , SRLUB Output (Fixed) − SDWE , SRWR Output (Fixed) −...
Page 88: Specification
TMP92CF30 Table 3.7.2 I/O Port and Specifications (1/5) X: Don’t care I/O register Port Pin name Specification PnCR PnFC PnFC2 Port 1 P10 toP17 Input port None Output port D8 to D15 bus Port 4 P40 to P47 Output port None None A0 to A7 Output...
Page 89 TMP92CF30 Table3.7.2 I I/O Port and Specifications (2/5) X: Don’t care I/O register Port Pin name Specification PnCR PnFC PnFC2 Port 9 P90, P92 Input port None Input port, RXD0 Input None None Input port None None Input port None None None P90 to P92...
Page 90 TMP92CF30 Table3.7.2 I/O Port and Specifications (3/5) X: Don’t care I/O register Port Pin name Specification PnCR PnFC PnFC2 Port G PG0 to PG5 Input port None AN0 to AN5 Input ADTRG Input None None MX Output Note: None MY Output Note: Port J PJ5 to PJ6...
Page 91 TMP92CF30 Table 3.7.2 I/O Port and Specifications (4/5) X: Don’t care I/O register Port Pin name Specification PnCR PnFC PnFC2 <PP1F2:3F2>=0 Port P PP3 to PP5 Input port <PP1F2:3F2>=0 Output port None None Output port <PP1F2>=0 INT5 input <PP1F2>=0 TA7OUT Output TXD0 Output <PP0F2>=0 <PP1F2>=1...
Page 92 TMP92CF30 Table 3.7.2 I/O Port and Specifications (5/5) X: Don’t care I/O register Port Pin name Specification PnCR PnFC PnFC2 Port X Input port Output port None Output port CLKOUT Output None X1USB Input None X1D4 Output (Output clock = × 1/8) <PX5F2:4F2>=00 X1D4 Output (Output clock = ×...
Page 93 TMP92CF30 3.7.1 Port 1 (P10 to P17) Port1 is an 8-bit general-purpose I/O port. Bits can be individually set as either inputs or outputs by control register P1CR and function register P1FC. In addition to functioning as a general-purpose I/O port, port1 can also function as a data bus (D8 to D15).
Page 94 TMP92CF30 Port 1 register bit Symbol (0004H) Read/Write System Data from external port (Output latch register is cleared to “0”) Reset State Port 1 Control register P1CR bit Symbol P17C P16C P15C P14C P13C P12C P11C P10C (0006H) Read/Write System Reset State Function 0: Input 1: Output...
Page 95 TMP92CF30 3.7.2 Port 4 (P40 to P47) Port4 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose Output port, port4 can also function as an address bus (A0 to A7). Each bit can be set individually for function. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 4 to the following function pins: Function Setting after reset is released Don’t use this setting...
Page 96 TMP92CF30 Port 4 register bit Symbol (0010H) Read/Write System Reset State Port 4 Function register P4FC bit Symbol P47F P46F P45F P44F P43F P42F P41F P40F (0013H) Read/Write System Reset State Function 0:Port 1:Address bus (A0 to A7) Port 4 Drive register P4DR bit Symbol P47D...
Page 97 TMP92CF30 3.7.3 Port 5 (P50 to P57) Port5 is an 8-bit general-purpose Output ports. In addition to functioning as a general-purpose I/O port, port5 can also function as an address bus (A8 to A15). Each bit can be set individually for function. Setting the AM1 and AM0 pins as shown below and resetting the device initialize port 5 to the following function pins: Function Setting after reset is released Don’t use this setting...
Page 98 TMP92CF30 Port 5 register bit Symbol (0014H) Read/Write System Reset State Port 5 Function register P5FC bit Symbol P57F P56F P55F P54F P53F P52F P51F P50F (0017H) Read/Write System Reset State Function 0:Port 1:Address bus (A8 to A15) Port 5 Drive register P5DR bit Symbol P57D...
Page 99 TMP92CF30 3.7.4 Port 6 (P60 to P67) Port6 is an 8-bit general-purpose I/O ports. Bits can be individually set as either inputs or outputs and function by control register P6CR and function register P6FC. In addition to functioning as a general-purpose I/O port, port6 can also function as an address bus (A16 to A23).
Page 100 TMP92CF30 Port 6 register bit Symbol (0018H) Read/Write System Data from external port (Output latch register is cleared to “0”) Reset State Port 6 Control register P6CR bit Symbol P67C P66C P65C P64C P63C P62C P61C P60C (001AH) Read/Write System Reset State Function 0:Input 1:Output...
Page 101 TMP92CF30 3.7.5 Port 7 (P70 to P76) Port7 is a 7-bit general-purpose I/O port (P70 is used for output only). Bits can be individually set as either inputs or outputs by control register P7CR and function register P7FC. In addition to functioning as a general-purpose I/O port, P70 to P76 pins can also function as interface-pins for external memory.
Page 102 TMP92CF30 P7CR register P7FC register P73 (EA24) P7 register P74 (EA25) EA24, EA25 Selector Read data Selector P7CR register P7FC register P7 register P75(R/W, Selector Port read data Selector NDR/ B P7CR register P7FC register P76 ( WAIT P7 register Port read data WAIT Figure 3.7.10 Port7...
Page 103 TMP92CF30 Port 7 register bit Symbol (001CH) Read/Write Data from external port Data from external port Data from external port System (Output latch register is (Output latch register is (Output latch register is Reset State set to “1”) cleared to “0”) set to “1”) Port 7 Control register P7CR...
Page 104 TMP92CF30 3.7.6 Port 8 (P80 to P83, P86, P87) Port 8 is 6-bit output ports. Resetting sets the output latch of P82 to “0” and the output latches of P80 to P81, P83, P86 and P87 to “1”. Port 8 can also be set to function as an interface-pin for external memory using function register P8FC.
Page 105 TMP92CF30 Port 8 register bit Symbol (0020H) Read/Write System 0 (Note3) Reset State Port 8 Function register P8FC bit Symbol P87F P86F P83F P82F P81F P80F (0023H) Read/Write System Reset State 0: Port 0: Port Refer to following table 0: Port 0: Port Function 1: <P87F2>...
Page 106 TMP92CF30 3.7.7 Port 9 (P90 to P92, P96, P97) P90 to P92 are 3-bit general-purpose I/O port. I/O can be set on a bit basis using the control register. Each bit can be set individually for input or output. Resetting sets P90 to P92 to input port and all bits of output latch to”1”.
Page 107 TMP92CF30 Reset Direction control (on bit basis) P9CRwrite Function control (on bit basis) P9FCwrite Output latch Selector P91 (RXD0, RXD1) P9 write P92 (SCLK0, CTS , SCLK1, CTS ) SCLK0 Selector output SCLK1 output P9FC2<P95F2> Selector P9 read RXD0 input (to PP4,PP5) SCLK0 input P91/RXD1, P92/SCLKI1...
Page 108 TMP92CF30 Port 9 register bit Symbol (0024H) Read/Write System Data from external Data from external port (Output Reset State port latch register is set to “1”) Port 9 control register P9CR bit Symbol P92C P91C P90C (0026H) Read/Write System Reset State Function Refer to following table Port 9 function register...
Page 109 TMP92CF30 Port 9 drive register P9DR bit Symbol P97D P96D P92D P91D P90D (0089H) Read/Write System Reset State Function Input/Output buffer drive register for standby mode P92 setting P90 setting P91 setting <P92C> <P91C> <P90C> <P92F> <P90F> Input port, Input port Output port Input port/ Output port...
Page 110 TMP92CF30 3.7.8 Port A (PA0 to PA7) Ports A0 to A7 are 8-bit general-purpose input ports with pull-up resistor. In addition to functioning as general-purpose I/O ports, ports A0 to A7 can also, as a Keyboard interface, operate a Key-on wake-up function. The various functions can each be enabled by writing a “1”...
Page 111 TMP92CF30 Port A register bit Symbol (0028H) Read/Write System Data from external port Reset State Port A Function register PAFC bit Symbol PA7F PA6F PA5F PA4F PA3F PA2F PA1F PA0F (002BH) Read/Write System Reset State 0: KEY IN disable 1: KEY IN enable Function Port A Drive register PADR...
Page 112 TMP92CF30 3.7.9 Port C (PC0 to PC7) PC0 to PC7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port C to an input port. It also sets all bits of the output latch register to “1”.
Page 113 TMP92CF30 (2) PC1 (INT1, TA0IN), PC3 (INT3, TA2IN) Reset Direction control PCCR write Function control PCFCwrite PC1 (INT1,TA0IN) Output latch PC3 (INT3, TA2IN) PCwrite Selector PC read Level/edge selection INT1 INT3 Rising/Falling selection IIMC<I1LE, I1EDGE> <I3LE, I3EDGE> TA0IN TA2IN Figure 3.7.21 Port C1,C3 2009-06-12 92CF30-111...
Page 114 TMP92CF30 (3) PC4 (EA26, SPDI) Reset Direction control (on bit basis) PCCR write Function control (on bit basis) PCFC write PC4 (EA26, SPDI) Output latch Selector EA26 PC write Selector PC read SPDI input Selector (from PR0) SPDI PCFC2<PC4F2> Figure 3.7.22 Port C4 (4) PC5 (EA27), PC6 (EA28) Reset Direction...
Page 115 TMP92CF30 (5) PC7 (KO8) Reset Direction control PCCR write Function control PCFC write PC7(KO8) Output latch Open-drain enable PC write Selector PC read Figure 3.7.24 Port C7 2009-06-12 92CF30-113...
Page 116 TMP92CF30 Port C register bit Symbol Read/Write (0030H) System Data from external port (Output latch register is set to “1”) Reset State Port C control register bit Symbol PCCR PC7C PC6C PC5C PC4C PC3C PC2C PC1C PC0C Read/Write (0032H) System Reset State Function 0: Input 1: Output...
Page 117 TMP92CF30 Port C drive register PCDR bit Symbol PC7D PC6D PC5D PC4D PC3D PC2D PC1D PC0D (008CH) Read/Write System Reset State Function Input/Output buffer drive register for standby mode PC2 setting PC1 setting PC0 setting <PC2C> <PC1C> <PC0C> <PC2F> <PC1F> <PC0F>...
Page 118 TMP92CF30 3.7.10 Port F (PF0 to PF2, PF7) Ports F0 to F2 are 3-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PF0 to PF2 to be input ports. It also sets all bits of the output latch register to “1”.
Page 119 TMP92CF30 Reset Direction control (on bit basis) PFCR write Function control (on bit basis) PFFC write Output latch Selector PF0 (I2S0CKO) PF write PF1 (I2S0DO) PF2 (I2S0WS) I2S0CKO output I2S0DO output I2S0WS output Selector PF read Figure 3.7.26 Port F0, F1, F2 (2) Port F7 (SDCLK) Port F7 is general-purpose output port.
Page 120 TMP92CF30 Port F register bit Symbol Read/Write (003CH) System Data from external port (Output latch Reset State register is set to “1”) Port F control register PFCR bit Symbol PF2C PF1C PF0C (003EH) Read/Write System Reset State Function Refer to following table Port F function register PFFC bit Symbol...
Page 121 TMP92CF30 3.7.11 Port G (PG0 to PG5) PG0 to PG5 are 6-bit input ports and can also be used as the analog input pins for the internal AD converter. PG3 can also be used as the ADTRG pin for the AD converter. PG2 and PG3 can also be used as the MX and MY pins for a Touch screen interface.
Page 122 TMP92CF30 Port G register Bit Symbol (0040H) Read/Write System Data from external port Reset State Hot Reset − State Note: The input channel selection of the AD converter and the permission of for ADTRG input are set by AD converter mode register ADMOD1. Port G Function register PGFC Bit Symbol...
Page 123 TMP92CF30 3.7.12 Port J (PJ0 to PJ7) PJ0 to PJ4 and PJ7 are 6-bit output port. Resetting sets the output latch PJ to “1”, and they output “1”. PJ5 to PJ6 are 2-bit input/output port. In addition to functioning as a port, Port J also functions as output pins for SDRAM ( , SDLLDQM, SDCAS...
Page 124 TMP92CF30 Reset Direction control PJCR write Function control PJFC write Output latch Selector PJ5 (NDALE, SRULB PJ write PJ6 (NDCLE, SRUUB NDALE, NDCLE output output SRULB SRUUB Selector PJ read Figure 3.7.32 Port J5,J6 2009-06-12 92CF30-122...
Page 125 TMP92CF30 Port J register bit Symbol (004CH) Read/Write System Data from external port Reset State (Output latch register is set to “1”) Port J control register PJCR bit Symbol PJ6C PJ5C (004EH) Read/Write System Reset State Function 0: Input, 1: Output Port J function register bit Symbol PJFC...
Page 126 TMP92CF30 3.7.13 Port K (PK0 to PK7) PK0 to PK7 are 8-bit output ports. Resetting sets the output latch PK to “0”, and PK0 to PK7 pins output “0”. Reset Output latch PK0 ∼ PK7 Output buffer PK write PK read Figure 3.7.34 Port K0 to K7 2009-06-12 92CF30-124...
Page 127 TMP92CF30 Port K register bit Symbol (0050H) Read/Write System Reset State Port K drive register PKDR bit Symbol PK7D PK6D PK5D PK4D PK3D PK2D PK1D PK0D (0094H) Read/Write System Reset State Function Input/Output buffer drive register for standby mode Figure 3.7.35 Register for Port K 2009-06-12 92CF30-125...
Page 128 TMP92CF30 3.7.14 Port L (PL0 to PL7) PL0 to PL7 are 8-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to PL7 pins output “0”. In addition to functioning as a general-purpose output port, port L can also function as a data bus for 32-bit memory connection (D16 to D23).
Page 129 TMP92CF30 Port L register bit Symbol (0054H) Read/Write System Reset State Port L control register PLCR bit Symbol PL7C PL6C PL5C PL4C PL3C PL2C PL1C PL0C (0056H) Read/Write System Reset State Function 0: Input 1: Output Port L function register PLFC bit Symbol PL7F...
Page 130 TMP92CF30 3.7.15 Port M (PM1, PM2, PM7) PM1, PM2 and PM7 are 3-bit output ports. Resetting sets the output latch PM to “1”, and PM1, PM2 and PM7 pins output “1”. In addition to functioning as an output ports, port M also functions as output pin for the timers (TA1OUT), output pins for the RTC alarm ( ALARM ), and as the output pin for the melody/alarm generator (MLDALM, MLDALM ).
Page 131 TMP92CF30 Reset Function control (on bit basis) PMFC write Output latch Selector ALARM MLDALM PM write PM read MLDALM Selector ALARM Figure 3.7.39 Port M2 Reset Function control (on bit basis) PMFC write Output latch Selector PM write PM read Figure 3.7.40 Port M7 2009-06-12 92CF30-129...
Page 132 TMP92CF30 Port M register bit Symbol (0058H) Read/Write System Reset State Port M function register bit Symbol PMFC PM7F PM2F PM1F Read/Write (005BH) System Reset State 0: Port 0: Port Function 0: Port ALARM 1: MLDALM 1: Don’t <PM2>=1, setting MLDALM <PM1>=1, TA1OUT...
Page 133 TMP92CF30 3.7.16 Port N (PN0 to PN7) PN0 to PN7 are 8-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets Port N to an input port. In addition to functioning as a general-purpose I/O port, Port N can also function as key-board interface pin (KO0 to KO7) which can be set to open-drain output buffer.
Page 134 TMP92CF30 Port N register bit Symbol (005CH) Read/Write System Data from external port (Output latch register is set to “1”) Reset State Port N control register PNCR bit Symbol PN7C PN6C PN5C PN4C PN3C PN2C PN1C PN0C (005EH) Read/Write System Reset State Function 0: Input...
Page 135 TMP92CF30 3.7.17 Port P (PP3 to PP7) Ports P3 to P5 are 3-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port P3 to P5 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port, P3 to P5 can also function as an output pin for timer (TA7OUT), as an input pin for timers (TB0IN0, TB1IN0), and as an input pin for external interruption (INT5 to INT7), serial transfer SIO0 (TXD0, RXD0,...
Page 136 TMP92CF30 Reset Direction control (on bit basis) PPCR write Function control (on bit basis) PPFC write PP4 (INT6,TB0IN0, RXD0, RXD1) Output latch PP write Selector PP read Rising/Falling selection INT6 (from TMRB0) INT6 IIMC0<I6EDGE> <PP2F2> TB0IN0 (to P91) PP4RXD0 <PP2F2> Selector RXD1 input P91RXD1...
Page 137 TMP92CF30 Reset Direction control <PP3F2> (on bit basis) PPCR write Function control (on bit basis) <PP3F2> <PP6F2> PPFC write SCLK1 Selector PP5 (INT7, TB1IN0, SCLK0 Output latch Selector SCLK1, CTS , CTS ) SCLK0 PP write Selector PP read Rising/Falling selection IINT7 (from TMRB1) INT7 IIMC<I7EDGE>...
Page 138 TMP92CF30 Reset Function control (on bit basis) PPFC write Output latch Selector PP6 (TB0OUT0) PP write TB0OUT0 output Figure 3.7.47 Port P6 2009-06-12 92CF30-136...
Page 139 TMP92CF30 Port P register bit Symbol (0060H) Read/Write System Data from external port (Output latch Reset State register is cleared to “0”) Port P control register PPCR bit Symbol PP5C PP4C PP3C (0062H) Read/Write System Reset State Function 0: Input 1: Output Port P function register PPFC bit Symbol...
Page 140 TMP92CF30 Port P Function register 2 PPFC2 bit Symbol PP6F2 PP5F2 PP4F2 PP3F2 PP2F2 PP1F2 PP0F2 (0061H) Read/Write System Reset State Function SIO1 SCLK selection selection selection selection selection output selection 0: TXD1 0: Others 0: Others 0: Others 0: CMOS 0: SCLK1 0: PP4 1: TXD0...
Page 141 TMP92CF30 3.7.18 Port R (R0 to R3) Ports R0 to R3 are 4-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port R0 to R3 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port, PR0 to PR3 can also function as the SPI controller pin (SPCLK, SPCS , SPDO and SPDI).
Page 142 TMP92CF30 Reset Direction control (on bit basis) PRCR write Function control (on bit basis) PRFC write PR1 (SPDO), PR2 ( SPCS ), Output latch Selector PR3 (SPCLK) PR write SPDO, SPCS , SPCLK Selector PR read Figure 3.7.50 Port R1 to R3 2009-06-12 92CF30-140...
Page 143 TMP92CF30 Port R register bit Symbol (0064H) Read/Write System Data from external port Reset State (Output latch register is cleared to “0”) Port R control register PRCR bit Symbol PR3C PR2C PR1C PR0C (0066H) Read/Write System Reset State Function 0: Input, 1: Output Port R function register PRFC bit Symbol...
Page 144 TMP92CF30 3.7.19 Port T (PT0 to PT7) Ports T0 to T7 are 8-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets ports T0 to T7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port, PT0 to PT7 can also function as data bus for 32-bit memory connection (D24 to D31).
Page 145 TMP92CF30 Port T register bit Symbol (00A0H) Read/Write System Data from external port (Output latch register is cleared to “0”) Reset State Port T control register PTCR bit Symbol PT7C PT6C PT5C PT4C PT3C PT2C PT1C PT0C (00A2H) Read/Write System Reset State Function 0: Input 1: Output...
Page 146 TMP92CF30 3.7.20 Port V (PV6, PV7) Ports V6 and V7 are 2-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets port V6 and V7 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port, PV can also function as a input or output pin for SBI (SDA, SCL).
Page 147 TMP92CF30 Port V register bit Symbol (00A8H) Read/Write Data from external port System (Output latch register is Reset State cleared to “0”) Port V control register PVCR bit Symbol PV7C PV6C (00AAH) Read/Write System Reset State Function 0: Input 1: Output Port V function register PVFC bit Symbol...
Page 148 TMP92CF30 3.7.21 Port X (PX4, PX5) Port X5 is 1-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets ports X5 to input port and output latch to “0”. In addition to functioning as general-purpose I/O port, PX5 can also function as the USB clock input pin (X1USB) and dividing clock output of X1 and X2 oscillation clock (X1D4).
Page 149 TMP92CF30 Reset Direction control (on bit basis) PXCR write Function control (on bit basis) PXFC write Function control 2 (on bit basis) PXFC2 write Output latch PX5 (X1USB, X1D4) Selector PX write X1pin ×1/8 Selector X1D4 output X1 pin ×1/4 Selector X1 pin ×1/2 X1 pin ×1/1...
Page 150 TMP92CF30 Port X register bit Symbol Note3) Note2) (00B0H) Read/Write System Data from external port Reset State (Output latch register is cleared to “0”) Port X control register PXCR bit Symbol PX5C (00B2H) Read/Write System Reset State 0: Input Function 1: Output Port X function register PXFC...
Page 151 TMP92CF30 Port X drive register PXDR bit Symbol PXD5 PXD4 (009FH) Read/Write System Reset State Input/Output buffer Function drive register for standby mode Note 1: A read-modify-write operation cannot be performed for the registers PXCR, PXFC and PXFC2. Note 2: When PX4 is used as CLKOUT output pin, PX<PX4> must be set to “0”. Refer to following PX4 setting table. Note 3: When PX5 is used as X1D4 pin, PX<PX5>...
Page 152 TMP92CF30 Memory Controller (MEMC) 3.8.1 Functional Overview The TMP92CF30 has a memory controller with the following features to control four programmable address spaces: (1) Four programmable address spaces The MEMC can specify a start address and a block size for each of the four memory spaces (CS0 to CS3 spaces).
Page 153 TMP92CF30 3.8.2 Control Registers and Memory Access Operations After Reset This section describes the registers to control the memory controller, their reset states and the necessary settings after reset. (1) Control Registers The control registers of the memory controller are listed below. ･...
Page 154 TMP92CF30 Table 3.8.1 Control Registers B0CSL Bit Symbol B0WW3 B0WW2 B0WW1 B0WW0 B0WR3 B0WR2 B0WR1 B0WR0 (0140H) Read/Write Reset State B0CSH Bit Symbol B0REC B0OM1 B0OM0 B0BUS1 B0BUS0 (0141H) Read/Write Reset State MAMR0 Bit Symbol M0V20 M0V19 M0V18 M0V17 M0V16 M0V15 M0V14-V9 M0V8...
Page 155 TMP92CF30 Table 3.8.2 Control Registers BEXCSL Bit Symbol BEXWW3 BEXWW2 BEXWW1 BEXWW0 BEXWR3 BEXWR2 BEXWR1 BEXWR0 (0158H) Read/Write Reset State BEXCSH Bit Symbol BEXREC BEXOM1 BEXOM0 BEXBUS1 BEXBUS0 (0159H) Read/Write Reset State PMEMCR Bit Symbol OPGE OPWR1 OPWR0 (0166H) Read/Write Reset State CSTMGCR Bit Symbol...
Page 156 TMP92CF30 (2) Memory Access Operations After Reset After reset, external memory is accessed using the initial data bus width that is determined by the AM1 and AM0 pins. The settings of the AM1 and AM0 pins and their corresponding operation modes are as follows: Start Mode Don’t use this setting 16-bit external bus starting (Note)
Page 157 TMP92CF30 3.8.3 Basic Functions and Register Settings This section describes some of the memory controller functions, such as setting the address range for each address space, associating memory to the selected space and setting the number of wait states to be inserted. (1) Programming chip select spaces The address ranges of CS0 to CS3 are specified by MSAR0 to MSAR3 and MAMR0 to MAMR3.
Page 158 TMP92CF30 (b) Memory Address Mask Registers Figure 3.8.3 shows the Memory Address Mask registers. MAMR0 to MAMR3 are used to determine the sizes of the CS0 to CS3 spaces by setting particular bits in MAMR0 to MAMR3 to mask the corresponding start address bits. The address compare logic uses only the address bits that are not masked (i.e., mask bit cleared to 0) to detect an address match in the CS0 to CS3 spaces.
Page 159 TMP92CF30 (c) Setting the start addresses and address ranges An example of specifying a 64-Kbyte address space starting from 010000H for the CS0 space: Set 01H in the MSAR0<S23:S16> bits that corresponds to the upper 8 bits of the start address. Then, calculate the difference between the start address and the anticipated end address (01FFFFH) based on the size of the CS0 space.
Page 160 TMP92CF30 Table 3.8.3 Valid Block Sizes for Each CS Space Size (Byte) 32 K 64 K 128 K 256 K 512 K CS space ○ ○ ○ ○ Δ Δ Δ Δ Δ ○ ○ ○ Δ Δ Δ Δ Δ...
Page 161 TMP92CF30 (2) Memory specification Setting the BnCSH<BnOM1:BnOM0> bits specifies the memory type that is associated with each address spaces. The interface signal that corresponds to the specified memory type is generated. The memory type is specified as follows: BnCSH<BnOM1:0> BnOM1 BnOM0 Memory Type SRAM/ROM (Default)
Page 162 TMP92CF30 Operand Start Mem ory Bus W idth CPU Data Operand Data CPU Address Size (bit) Address (bit) D31 to D24 D23 to D16 D15 to D8 D7 to D0 4n + 0 4n + 0 8/16/32 xxxxx xxxxx xxxxx b7 to b0 4n + 1 xxxxx...
Page 163 TMP92CF30 (4) Wait control The external bus cycle completes in two states at minimum (25 ns at f = 80 MHz) without inserting a wait state. Setting up the BnCSL<BnWW3:BnWW0> bits specifies the number of wait states to be inserted in a write cycle, and setting the BnCSL<BnWR3:BnWR0> bits specifies the number of wait states to be inserted in a read cycle.
Page 164 TMP92CF30 (5) Recovery cycle (data hold time) control For some memory, the data hold time after when the signal is asserted in a read cycle is defined by the AC specification. This may lead to data conflicts. Thus, to avoid this problem, a single dummy cycle can be inserted immediately after an access cycle for the CSm space by setting the BmCSH<BmREC>...
Page 165 TMP92CF30 (6) Timing adjustment function for control signals This function allows for the timing adjustment of the rising and falling edges of the , R/ signals based on the setup and hold CSZx CSXx WRxx SRWR SRxxB time requirements of memories. As for the and R/ signals, and also for the...
Page 166 TMP92CF30 RDTMGCR0/1<BnTCRS1:BnTCRS0> TCRS = 0.5 × 1/f (Default) TCRS = 1.5 × 1/f TCRS = 2.5 × 1/f TCRS = 3.5 × 1/f TCRS:The delay from CSn to RD,SRxxB. Tn-2 Tn-1 SDCLK (80MHz) A23 to A0 TCRS SRxxB Read TCRH cycle D31 to D0 Input...
Page 167 TMP92CF30 (7) Basic bus timing (a) External bus read/write cycle (0 wait state) SDCLK (80 MHz) A23 to A0 SRxxB Read D31to D0 Input SRWR SRxxB Write WRxx D31 to D0 Output Note: Above diagram shows case of 32-bit bus access. (b) External bus read/write cycle (1 wait state) SDCLK (80 MHz)
Page 168 TMP92CF30 (c) External bus read cycle (1 wait state + TAC: 1×1/f + TCRS: 1.5×1/f + TCRH: 1×1/ f External bus write cycle (1 wait state + TAC: 1×1/f + TCWS/H: 1.5×1/f SDCLK (80 MHz) A23 to A0 RD SRxxB TCRS TCRH Read...
Page 169 TMP92CF30 (e) External bus read/write cycle (4 wait states + pin input mode) WAIT SDCLK (80 MHz) A23 to A0 RD SRxxB Read D31 to D0 Input SRWR , SRxxB Write WRxx D31 to D0 Output WAIT Sampling Sampling Note: Above diagram shows case of 32-bit bus access. External bus read cycle (4 wait states + pin input mode +TAC: 1×1/f WAIT...
Page 170 TMP92CF30 (8) External memory connections Figure 3.8.4 shows an example of how to connect external 16-bit SRAM and 16-bit NOR flash to the TMP92CF30. 16-bit SRAM SRLLB SRLUB SRWR D [15:0] I/O [16:1] Not connect 16-bit NOR flash DQ [15:0] Figure 3.8.4 Example of External 16-Bit SRAM and NOR Flash Connection 2009-06-15 92CF30-168...
Page 171 TMP92CF30 3.8.4 Controlling the Page Mode Access to ROM This section describes page mode access operations to ROM and the required register settings. The page mode operation to ROM is specified by PMEMCR. (1) Operations and register settings The TMP92CF30 supports page mode accesses to ROM. Only the CS2 space can be configured for this mode of access.
Page 172 TMP92CF30 3.8.5 Notes (1) Timing for the signals If the load capacitance of the (Read) signal line is greater than that of the (Chip Select) signal line, the deassertion timing of the read signal is delayed, which may lead to an unintentional extension of a read cycle.
Page 173 TMP92CF30 (2) Setting up the NAND flash area Figure 3.8.8 shows a memory map for the NAND flash memory. Since it is recommended that the CS3 space be located in the memory area from 000000H to 3FFFFFH, the following description is provided for such condition.In this case, the NAND flash area overlaps with the CS3 space.
Page 174 TMP92CF30 (3) Setting up the NAND flash area In case of using SDRAM (SDCS) and NAND flash together, the BROMCR<CSDIS> bit cannot be used. This section provides an example of such cases. It is recommended that the memory area from 000000H to 3FFFFFH be assigned to the CS2 or CS1 (SDCS) space.
Page 175 TMP92CF30 External Memory Extension (MMU) The MMU allows for memory expansion by providing three local memory areas, the MMU function allows for the expansion of the program/data area to 2.1Gbytes. For recommended address memory maps, refer to Figure 3.9.1. However, when the amount of memory being used is less than 16 Mbytes, it is not necessary to configure the MMU register.
Page 176 TMP92CF30 Memory controller setting pin (512 MB) Address memory map pin (512 MB) 000000H On-chip I/O, RAM CSXA CSXB 512 MB (2 MB × 256) 512 MB (2 MB × 256) COMMON-X (2 MB) CS3-space 200000H 4 MB LOCAL-X ・・・ 255 256 ・・...
Page 177 TMP92CF30 LOCAL-X LOCAL-Y LOCAL-Z 92CF30 SDCS or CSXA to CSXB , CSZA to CSZD 64 MB (Note) EA24 to EA28 EA24 to EA28 512 MB × 2 = 1024 MB 512 MB × 2 = 1024 MB CSXA CSZA CSZD 000000H Bank 0 Bank 0...
Page 178 TMP92CF30 3.9.2 Control registers The TMP92CF30 MMU has 21 registers. These registers are used for storing seven types of data (program, read data, write data, source data for DMA channels of odd/even number, destination-data for DMA channels of odd/even number) for each of three-LOCAL areas (LOCAL-X through LOCAL-Z).
Page 179 TMP92CF30 3.9.2.1 Program bank registers These registers should be loaded with bank number values to specify the bank to be used as program memory. As described above, the program execution cannot be directly branched to a different bank in the same LOCAL area. The bank switching within the same LOCAL area is prohibited.
Page 180 TMP92CF30 3.9.2.2 Read-Data Bank Registers These registers should be loaded with bank number values to specify the banks to be used as read-data memory. The following example shows how to specify bank 1 for storing read data in the LOCAL-X area. The instruction, “ldw wa, (xix),”reads the data from the memory location at the address xix and stores it into the wa register of the CPU.
Page 181 TMP92CF30 LOCAL-Z Register for Read Data LOCALRZ Bit Symbol (0894H) Read/Write Reset State Specify the bank number for the LOCAL-Z area Function (Since bank 3 is overlapping with the COMMON area, this filed must not be specified as 3.) (0895H) Bit Symbol Read/Write Reset State...
Page 182 TMP92CF30 3.9.2.3 Write-Data Bank Registers These registers should be loaded with bank number values to specify the banks to be used as write data memory. The following example shows how to specify bank 1 for storing write data in the LOCAL-X area. The instruction, “ldw (xix), wa,” writes the wa register value of the CPU into the memory location at the address xix.
Page 183 TMP92CF30 LOCAL-Z Register for Write Data LOCALWZ Bit Symbol (089CH) Read/Write Reset State Specify the bank number for the LOCAL-Z area Function (Since bank 3 is overlapping with the COMMON area, this filed must not be specified as 3.) (089DH) Bit Symbol Read/Write Reset State...
Page 184 TMP92CF30 3.9.2.4 DMA-Function Bank Registers The TMP92CF30 supports not only the read and write operations of the CPU, but also the high-speed data transfer by enabling the internal DMAC to become the bus master. (Please refer to Section 3.7, “DMA Controller”.) These registers are provided specially for the DMA operation, separately from the bank registers for the CPU.
Page 185 TMP92CF30 LOCAL-X Register for the E-group DMA Source LOCALESX Bit Symbol (08A0H) Read/Write Reset State Specify the bank number for the LOCAL-X area Function (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) (08A1H) Bit Symbol Read/Write...
Page 186 TMP92CF30 LOCAL-X Register for the E-group DMA Destination LOCALEDX Bit Symbol (08A8H) Read/Write Reset State Specify the bank number for the LOCAL-X area Function (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) (08A9H) Bit Symbol Read/Write...
Page 187 TMP92CF30 LOCAL-X Register for the O-group DMA Source LOCALOSX Bit Symbol (08B0H) Read/Write Reset State Function Specify the bank number for the LOCAL-X area (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) (08B1H) Bit Symbol Read/Write...
Page 188 TMP92CF30 LOCAL-X Register for the O-group DMA Destination LOCALODX Bit Symbol (08B8H) Read/Write Reset State Specify the bank number for the LOCAL-X area Function (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) (08B9H) Bit Symbol Read/Write...
Page 189 TMP92CF30 3.9.3 Programming example The conditions listed in this table apply the following programming examples. Logical Physical Used as Memory Setting MMU area address address Main NOR-Flash COMMON-Z C00000H to CSZA , Routine (16 MB, 1 pcs) FFFFFFH 32 bit, Character- Bank 0 in 800000H to...
Page 190 TMP92CF30 (b) Subroutine (Bank 0 in LOCAL-Y) Logical Physical Instruction Instruction Comment address address 400000H ; Bank 0 in LOCAL-Z is configured as 400000H 000000H (localrz), 8001H read-data memory for Character-RAM ; Index address register for reading 4000xxH 0000xxH xiy,800000H Character-ROM ;...
Page 191: Data Bus Width
TMP92CF30 3.10 SDRAM Controller (SDRAMC) The TMP92CF30 incorporates an SDRAM controller (SDRAMC) for accessing SDRAM that can be used as data memory, program memory, or display memory. The SDRAMC has the following features: (1) Supported SDRAM Data rate type : SDR (single data rate) type only Memory capacity : 16 / 64 / 128 / 256 / 512 Mbits Number of banks...
Page 192 TMP92CF30 3.10.1 Control Registers The SDRAMC has the following control registers. SDRAM Access Control Register − SDACR Bit symbol SRDS SMUXW1 SMUXW0 SPRE SMAC (0250H) Read/Write Reset State Function Read data Always Address multiplex Read/Write SDRAM shift write “0” type commands controller function...
Page 193 TMP92CF30 SDRAM Command Register SDCMM Bit symbol SCMM2 SCMM1 SCMM0 (0253H) Read/Write Reset State Function Command issue (Note 1) (Note 2) 000: Don’t care 001: Initialization sequence a. Precharge All command b. Eight Auto Refresh commands c. Mode Register Set command 010: Precharge All command 100: Reserved 101: Self Refresh Entry command...
Page 194 TMP92CF30 3.10.2 Operation Description (1) Memory access control The SDRAMC is enabled by setting SDACR<SMAC> to “1”. When one of the bus masters (CPU, DMAC) generates a cycle to access the SDRAM address area, the SDRAMC outputs SDRAM control signals. Figure 3.10.2 to Figure3.10.5 shows the timing for accessing the SDRAM.
Page 195: Burst Length
TMP92CF30 Address multiplex function In access cycles, the A0 to A15 pins output low/column multiplexed addresses. The multiplex width is set by SDACR<SMUXW1:0>. Table 3.10.2 shows the relationship between the multiplex width and low/column addresses. Table 3.10.2 Address Multiplex SDRAM Access Cycle Address 92CF30 Row Address Pin Name...
Page 196 TMP92CF30 4CLK 3CLK 3CLK SDCLK SDCKE SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A15-A0 CA (n) CA (n+2) CA (n+4) D15-D0 D (n) D (n+2) D (n+4) CAS Latency=2CLK CAS Latency=2CLK CAS Latency=2CLK 1CLK Bank Read Read Read Active Figure 3.10.2 1-Word Read Cycle Timing 4CLK 1CLK 1CLK...
Page 197 TMP92CF30 3CLK 2CLK 2CLK SDCLK SDCKE SDLUDQM SDLLDQM SDCS SDRAS SDCAS SDWE A15-A0 CA (n) CA (n+2) CA (n+4) D15-D0 D (n) D (n+2) D (n+4) 1CLK 1CLK 1CLK 1CLK Bank Write Write Write Active Figure 3.10.4 Single Write Cycle Timing 2CLK 1CLK 1CLK...
Page 198 TMP92CF30 (2) Execution of instructions on SDRAM The CPU can execute instructions that are stored in the SDRAM. However, the following operations cannot be performed. a) Executing the HALT instruction b) Changing the clock gear setting c) Changing the settings in the SDACR, SDCMM, and SDCISR registers These operations, if needed, must be executed by branching to other memory such as internal RAM.
Page 199 TMP92CF30 (d) Precharge command SDCLK Next PRECHARGE Command COMMAND *TRP=2CLK (SDCISR<STRP>= “1”) (e) Read cycle SDCLK ACTIVE READ ACTIVE COMMAND Non MUX-address Row Address Column Address Row Address A15-A0 D15-D0 TRCD *TRCD=2CLK (SDCISR<STRCD>= “1”) *TRC=6CLK (SDCISR<STRC2:0>= “101”) Write cycle SDCLK ACTIVE COMMAND WRITE...
Page 200 TMP92CF30 (4) Read data shift function If the AC specifications of the SDRAM cannot be satisfied when data is read from the SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in the next state.
Page 201 TMP92CF30 (c) Full-page read, the read data shift function enabled (SDACR<SRDS> = “1”, <SRDSCK> = “0”) SDCLK ACTIVE READ COMMAND Row Address ColumnAddress A15-A0 DIN1 DIN2 DIN3 D15-D0 Internal system clock DIN1 DIN2 DIN3 Internal data bus External data latch CPU data read (5) Read/Write commands The Read/Write commands to be used in 1-word read/single write mode can be specified by...
Page 202: Refresh Control
TMP92CF30 (6) Refresh control The TMP92CF30 supports two kinds of refresh commands: Auto Refresh and Self Refresh. (a) Auto Refresh When SDRCR<SRC> is set to “1”, the Auto Refresh command is automatically issued at intervals specified by SDRCR<SRS2:0>. The Auto Refresh interval can be specified in a range of 47 states to 1248 states (0.78 μs to 20.8 μs at f = 60 MHz).
Page 203 TMP92CF30 (b) Self Refresh The Self Refresh Entry command is issued by setting SDCMM<SCMM2:0> to “101”. Figure 3.10.7 shows the Self Refresh cycle timing. Before entering Self-refresh mode, issue the all Bank Pre-charge Command. Once Self Refresh is started, the SDRAM is refreshed internally without the need to issue the Auto Refresh command.
Page 204 TMP92CF30 The Self Refresh state can be exited by the Self Refresh Exit command. The Self Refresh Exit command is executed when SDCMM<SCMM2:0> is set to “110”. It is also executed automatically in synchronization with HALT mode release. In either of these two cases, Auto Refresh is performed immediately after the Self Refresh state is exited.
Page 205 TMP92CF30 (7) SDRAM initialization sequence After reset release, the following sequence of commands can be executed to initialize the SDRAM. Precharge All command Eight Auto Refresh commands Mode Register Set command The above commands are issued by setting SDCMM<SCMM2:0> to “001”. While these commands are issued, the CPU operation (instruction fetch, execution) is halted.
Page 206 TMP92CF30 (8) Connection example Figure 3.10.10 shows an example of connections between the TMP92CF30 and SDRAM. Table 3.10.4 Pin Connections SDRAM Pin Name 92CF30 Data Bus Width 16 bits Pin Name 128M 256M 512M − − − − − − −...
Page 207 TMP92CF30 3.10.3 An Example of Calculating HDMA Transfer Time The following shows an example of calculating the HDMA transfer time when SDRAM is used as the transfer source. • Transfer from SDRAM to internal SRAM Conditions: System clock (f : 60 MHz SDRAM read cycle : Full page (5-1-1-1), 16-bit data bus 16-bit data bus...
Page 208 TMP92CF30 3.10.4 Considerations for Using the SDRAMC This section describes the points that must be taken into account when using the SDRAMC. Please carefully read the following to ensure proper use of the SDRAMC. 1) WAIT access When SDRAM is used, the following restriction applies to memory access to other than the SDRAM.
Page 209 TMP92CF30 3.11 NAND Flash Controller (NDFC) 3.11.1 Features The NAND Flash Controller (NDFC) is provided with dedicated pins for connecting with NAND Flash memory. The NDFC also has an ECC calculation function for error correction and supports two types of ECC calculation methods. The ECC calculation method using Hamming codes can be used for NAND Flash memory of SLC (Single Level Cell) type and is capable of detecting a single-bit error for every 256 bytes.
Page 210: Block Diagram
TMP92CF30 3.11.2 Block Diagram NAND Flash Controller Channel 0 (NDFC0) ND_CE* Hamming ND_ALE Generator NDCLE, ND_CLE NDALE, ND_RE* NDRE , Code NDWE , ND WE* Timing D15~ D0 Generator ND_RB* RS ECC Write Control Reed-Solomon Register Generator DATA_OUT[15:0] D15~D0, DATA_IN[15:0] F/F 80-bit NDR/B Address...
Page 211 TMP92CF30 3.11.3 Operation Description 3.11.3.1 Accessing NAND Flash Memory The NDFC accesses data on NAND Flash memory indirectly through its internal registers. This section explains the operations for accessing the NAND Flash. Since no dedicated sequencer is provided for generating commands to the NAND Flash, the levels of the NDCLE, NDALE, and pins must be controlled by software.
Page 212 TMP92CF30 signals are explained next. Write and read operations to and from NDRE NDWE the NAND Flash are performed through the ND0FDTR register. The actual write operation completes not when the ND0FDTR register is written to but when the data is written to the external NAND Flash.
Page 213 TMP92CF30 3.11.4 ECC Control NAND Flash memory devices may inherently include error bits. It is therefore necessary to implement the error correction processing using ECC (Error Correction Code). Figure3.11.4 shows a basic flowchart for ECC control. Data Write Data Read Valid data write to Valid data read from NAND Flash...
Page 214 TMP92CF30 3.11.4.1 Differences between Hamming Codes and Reed-Solomon Codes The NDFC includes an ECC generator supporting NAND Flash memory devices of SLC (or 2LC: two states) type and MLC (or 4LC: four states) type. The ECC calculation using Hamming codes (supporting SLC) generates 22 bits of ECC for every 256 bytes of valid data and is capable of detecting and correcting a single-bit error for every 256 bytes.
Page 215 TMP92CF30 3.11.4.2 Error Correction Methods Hamming ECC • The ECC generator generates 44 bits of ECC for a page containing 512 bytes of valid data. The error correction process must be performed in units of 256 bytes (22 bits of ECC). The following explains how to implement error correction on 256 bytes of valid data using 22 bits of ECC.
Page 216 TMP92CF30 Reed-Solomon ECC • The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data. If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes), the error correction process must be repeated several times to cover the entire page.
Page 217: Description Of Registers
TMP92CF30 3.11.5 Description of Registers NAND Flash Control 0 Register ECCE BUSY ECCRST NDFMCR0 bit Symbol (08C0H) Read/Write Reset State Function NAND read-modify enable control control circuit Flash reset control control -write 0: Disable 0: “L” out 0: “L” out control state control...
Page 218 TMP92CF30 (c) <ECCE> The <ECCE> bit is used for both Hamming and Reed-Solomon codes. This bit is used to enable or disable the ECC generator. To reset the ECC in the ECC generator (to set <ECCRST> to “1”), the ECC generator must be enabled (<ECCE> = “1”). (d) <CE1:0>, <CLE>, <ALE>...
Page 219 TMP92CF30 <RSECCL> The <RSECCL> bit is used only for Reed-Solomon codes. When using Hamming codes, this bit should be set to “0”. The Reed-Solomon processing unit is comprised of two elements: an ECC generator and an ECC calculator. The latter is used to calculate the error address and error bit position. The error address and error bit position are calculated using an intermediate code generated from the ECC for written data and the ECC for read data.
Page 220 TMP92CF30 NAND Flash Control 1 Register INTERDY INTRSC BUSW ECCS SYSCKE NDFMCR1 bit Symbol (08C2H) Read/Write Reset State Function Ready Reed- Data bus Clock interrupt Solomon width calculation control calculation 0: Disable 0: 8-bit 0:Hamming 0: Disable 1: Enable interrupt 1: 16-bit 1: Reed- 1: Enable...
Page 221 TMP92CF30 (d) <INTRSC> The <INTRSC> bit is used only for Reed-Solomon codes. When using Hamming codes, this bit should be set to “0”. This bit is used to enable or disable the interrupt to be generated when the calculation of error address and error bit position has ended.
Page 222 TMP92CF30 NAND Flash Data Register 0 NDFDTR0 bit Symbol (1FF0H) Read/Write Reset State Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined NAND Flash Data Register (7-0) Function (1FF1H) bit Symbol Read/Write Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Reset State NAND Flash Data Register (15-8) Function NAND Flash Data Register 1...
Page 223 TMP92CF30 Table3.11.3 How to Access the NAND Flash Data Register Write Example of Access Data Size 8-bit NAND Flash 16-bit NAND Flash instruction 1-byte access ld (0x1FF0),a Supported Not supported 2-byte access ld (0x1FF0),wa Supported Supported 4-byte access ld (0x1FF0),xwa Supported Supported Read...
Page 224 TMP92CF30 NAND Flash ECC Register 0 ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 NDECCRD0 bit Symbol (08C4H) Read/Write Reset State NAND Flash ECC Register (7-0) Function ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10 ECCD9 ECCD8 (08C5H) bit Symbol Read/Write Reset State NAND Flash ECC Register (15-8) Function NAND Flash ECC Register 1...
Page 225 TMP92CF30 NAND Flash ECC Register 4 ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 NDECCRD4 bit Symbol (08CCH) Read/Write Reset State NAND Flash ECC Register (7-0) Function ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10 ECCD9 ECCD8 (08CDH) bit Symbol Read/Write Reset State Function NAND Flash ECC Register (15-8) Figure3.11.7 NAND Flash ECC Registers...
Page 226 TMP92CF30 The table below shows an example of how ECC is written to the redundant area in the NAND Flash memory when using Reed-Solomon codes. When using Hamming codes with SmartMedia™, the addresses of the redundant area are specified by the physical format of SmartMedia™. For details, refer to the SmartMedia™...
Page 227 TMP92CF30 NAND Flash Reed-Solomon Calculation Result Address Register RS0A7 RS0A6 RS0A5 RS0A4 RS0A3 RS0A2 RS0A1 RS0A0 NDRSCA0 bit Symbol (08D0H) Read/Write Reset State NAND Flash Reed-Solomon Calculation Result Address Register (7-0) Function (08D1H) bit Symbol RS0A9 RS0A8 Read/Write Reset State NAND Flash Function Reed-Solomon...
Page 228 TMP92CF30 If error is found at only one address, the error address is stored in the NDRSCA0 register. If error is found at two addresses, the NDRSCA0 and NDRSCA1 registers are used to store the error addresses. In this manner, up to four error addresses can be stored in the NDRSCA0 to NDRSCA3 registers.
Page 229 TMP92CF30 3.11.6 An Example of Accessing NAND Flash of SLC Type Initialization ; ***** Initialize NDFC ***** Conditions: 8-bit bus, CE0, SLC, 512 (528) bytes/page, Hamming codes (ndfmcr1),0001h ; 8-bit bus, Hamming ECC, SYSCK-ON (ndfmcr0),2000h ; SPLW1:0=0, SPHW1:0=2 Write Writing valid data ;...
Page 230 TMP92CF30 Executing page program ; ***** Set auto page program***** (ndfmcr0),20B0h ; WE enable, CLE enable (ndfdtr0),10h ; Auto page program command (ndfmcr0),2010h ; WE disable, CLE disable Wait setup time (from Busy to Ready) 1. Flag polling 2. Interrupt Reading status ;...
Page 231 TMP92CF30 Read Reading valid data ; ***** Read valid data***** (ndfmcr0),2010h ; CE0 enable (ndfmcr0),20B0h ; WE enable, CLE enable (ndfdtr0),00h ; Read command (ndfmcr0),20D0h ; ALE enable (ndfdtr0),xxh ; Address write (3 or 4 times) Wait setup time (from Busy to Ready) 1.
Page 232 TMP92CF30 ID Read The ID read routine is as follows: (ndfmcr0),20B0h ; WE Enable, CLE enable (ndfdtr0),90h ; Write ID read command (ndfmcr0),20D0h ; ALE enable, CLE disable (ndfdtr0),00h ; Write 00 (ndfmcr0),2010h ; WE disable, CLE disable xx,(ndfdtr0) ; Read 1'st ID maker code xx,(ndfdtr0) ;...
Page 233 TMP92CF30 3.11.7 An Example of Accessing NAND Flash of MLC Type (When the valid data is processed as 518byte) Initialization ; ***** Initialize NDFC ***** Conditions: 16-bit bus, CE1, MLC, 2048 (2112) bytes/page, Reed-Solomon codes (ndfmcr1),0007h ; 16-bit bus, Reed-Solomon ECC, SYSCK-ON (ndfmcr0),5000h ;...
Page 234 TMP92CF30 Writing ECC to NAND Flash ; ***** Write dummy data & ECC ***** (ndfmcr0),5088h ; ECC circuit disable, data write mode (ndfdtr0),xxxxh ; Redundancy area data write Write to 207-206hex address: > D79-64 (ndfdtr1),xxxxh ; Redundancy area data write Write to 209-208hex address: >...
Page 235 TMP92CF30 Read (including ECC data read) Reading valid data ; ***** Read valid data***** (ndfmcr0),5008h ; CE1 enable (ndfmcr0),50A8h ; WE enable, CLE enable (ndfdtr0),0000h ; Read command 1 (ndfmcr0),50C8h ; ALE enable (ndfdtr0),00xxh ; Address write (4 or 5 times) (ndfmcr0),50A8h ;...
Page 236 TMP92CF30 ID Read The ID read routine is as follows: (ndfmcr0),50A8h ; WE enable, CLE enable (ndfdtr0),0090h ; Write ID read command (ndfmcr0),50C8h ; ALE enable, CLE disable (ndfdtr0),0000h ; Write 00 (ndfmcr0),5008h ; WE disable, CLE disable xxxx,(ndfdtr0) ; Read 1'st ID maker code xxxx,(ndfdtr1) ;...
Page 237 TMP92CF30 3.11.8 An Example of Connections with NAND Flash TMP92CF30 NAND-Flash-0 100k Ω NAND-Flash-1 NDCLE NDALE NDRE NDWE 2k Ω NDR/B R/B (open drain) R/B (open drain) D[15:0] I/O[15:0] I/O[7:0] External circuits for Write-protect Note 1: A reset sets the pins as input ports, so pull-up resistors are needed.
Page 238 TMP92CF30 3.12 8 Bit Timer (TMRA) The TMP92CF30 features 8 channel built-in 8-bit timers (TMRA0 to TMRA7). These timers are paired into 4 modules: TMRA01, TMRA23, TMRA45 and TMRA67. Each module consists of 2 channels and can operate in any of the following 4 operating modes. •...
Page 239 TMP92CF30 3.12.1 Block Diagram Figure 3.12.1 TMRA01 Block Diagram 2009-06-12 92CF30-237...
Page 240 TMP92CF30 Figure 3.12.2 TMRA23 Block Diagram 2009-06-12 92CF30-238...
Page 241 TMP92CF30 Figure 3.12.3 TMRA45 Block Diagram 2009-06-12 92CF30-239...
Page 242 TMP92CF30 Figure 3.12.4 TMRA67 Block Diagram 2009-06-12 92CF30-240...
Page 243 TMP92CF30 3.12.2 Operation of Each Circuit Prescaler A 9-bit prescaler generates the input clock to TMRA01.The clock φT0TMR is selected using the prescaler clock selection register SYSCR0<PRCK>. The prescaler operation can be controlled using TA01RUN<TA0PRUN> in the timer control register. Setting <TA01PRUN> to “1” starts the count; setting <TA01PRUN>...
Page 244 TMP92CF30 Timer registers (TA0REG and TA1REG) These are 8-bit registers, which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows.
Page 245 TMP92CF30 Comparator (CP0, CP1) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to “0” and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time.
Page 246 TMP92CF30 3.12.3 TMRA01 RUN Register TA01RUN Bit symbol TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN (1100H) Read/Write Reset State Function Double In IDLE2 TMRA01 Up counter Up counter buffer mode prescaler (UC1) (UC0) 0: Disable 0: Stop 0: Stop and clear 1: Enable 1: Operate 1: Run (Count up) TA0REG double buffer control...
Page 247 TMP92CF30 TMRA45 RUN Register TA45RUN Bit symbol TA4RDE I2TA45 TA45PRUN TA5RUN TA4RUN (1110H) Read/Write Reset State Function Double In IDLE2 TMRA45 Up counter Up counter buffer mode prescaler (UC5) (UC4) 0: Disable 0: Stop 0: Stop and clear 1: Enable 1: Operate 1: Run (Count up) TA4REG double buffer control...
Page 248 TMP92CF30 TMRA01 Mode Register TA01MOD Bit symbol TA01M1 TA01M0 PWM01 PWM00 TA1CLK1 TA1CLK0 TA0CLK1 TA0CLK0 (1104H) Read/Write Reset State Function Operation mode PWM cycle Source clock for TMRA1 Source clock for TMRA0 00: 8-bit timer mode 00: Reserved 00: TA0TRG 00: TA0IN pin 01: φT1 01: φT1...
Page 249 TMP92CF30 TMRA23 Mode Register TA23MOD Bit symbol TA23M1 TA23M0 PWM21 PWM20 TA3CLK1 TA3CLK0 TA2CLK1 TA2CLK0 (110CH) Read/Write Reset State Function Operation mode PWM cycle TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 00: 8-bit timer mode 00: Reserved 00: TA2TRG 00: TA2IN pin 01: φT1 01: φT1...
Page 250 TMP92CF30 TMRA45 Mode Register TA45MOD Bit symbol TA45M1 TA45M0 PWM41 PWM40 TA5CLK1 TA5CLK0 TA4CLK1 TA4CLK0 (1114H) Read/Write Reset State Function Operation mode PWM cycle TMRA5 clock for TMRA5 TMRA4 clock for TMRA4 00: 8-bit timer mode 00: Reserved 00: TA4TRG 00: low-frequency clock 01: φT1 01: φT1...
Page 251 TMP92CF30 TMRA67 Mode Register TA67MOD Bit symbol TA67M1 TA67M0 PWM61 PWM60 TA7CLK1 TA7CLK0 TA6CLK1 TA6CLK0 (111CH) Read/Write Reset State Function Operation mode PWM cycle TMRA7 clock for TMRA7 TMRA6 clock for TMRA6 00: 8-bit timer mode 00: Reserved 00: TA6TRG 00: low-frequency clock 01: φT1 01: φT1...
Page 252 TMP92CF30 TMRA1 Flip-Flop Control Register TA1FFCR Bit symbol TA1FFC1 TA1FFC0 TA1FFIE TA1FFIS (1105H) Read/Write A read- Reset State modify-write Function 00: Invert TA1FF TA1FF TA1FF operation 01: Set TA1FF control for inversion cannot be 10: Clear TA1FF inversion select performed 11: Don’t care 0: Disable 0: TMRA0...
Page 253 TMP92CF30 TMRA3 Flip-Flop Control Register TA3FFCR Bit symbol TA3FFC1 TA3FFC0 TA3FFIE TA3FFIS (110DH) Read/Write A read- Reset State modify-write Function 00: Invert TA3FF TA3FF TA3FF operation 01: Set TA3FF control for inversion cannot be 10: Clear TA3FF inversion select performed 11: Don’t care 0: Disable 0: TMRA2...
Page 254 TMP92CF30 TMRA7 Flip-Flop Control Register TA7FFCR Bit symbol TA7FFC1 TA7FFC0 TA7FFIE TA7FFIS (111DH) Read/Write A read- Reset State modify-write Function 00: Invert TA7FF TA7FF TA7FF operation 01: Set TA7FF control for inversion cannot be 10: Clear TA7FF inversion select performed 11: Don’t care 0: Disable 0: TMRA6...
Page 255 TMP92CF30 Timer Registers − TA0REG bit Symbol (1102H) Read/Write Reset State − TA1REG bit Symbol (1103H) Read/Write Reset State − TA2REG bit Symbol (110AH) Read/Write Reset State − TA3REG bit Symbol (110BH) Read/Write Reset State − TA4REG bit Symbol (1112H) Read/Write Reset State −...
Page 256 TMP92CF30 3.12.4 Operation in Each Mode 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. a. Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register respectively.
Page 257 TMP92CF30 Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). = 50 MHz, use the following procedure to Example: To output a 3.2μs square wave pulse from the TA1OUT pin at f make the appropriate register settings.
Page 258 TMP92CF30 Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) TMRA1 match output...
Page 259 TMP92CF30 The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not cleared. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match.
Page 260 TMP92CF30 In this mode a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN<TA1RUN>...
Page 261 TMP92CF30 = 50 MHz) Example: To generate 1/4 duty 31.25 kHz pulses (at f 32 μs * Clock state Clcok gear : Prescaler of clock gear : 1/2 Calculate the value which should be set in the timer register. To obtain a frequency of 31.25 kHz, the pulse cycle t should be: t = 1/31.25kHz = 32 μs φT1 = 0.16 μs (at 50 MHz);...
Page 262 TMP92CF30 (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin (Shared with PM1).
Page 263 TMP92CF30 In this mode the value of the register buffer will be shifted into TA0REG if 2 overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q Up counter = Q...
Page 264 TMP92CF30 Table 3.12.3 PWM Cycle Clock gear Prescaler of PWM cycle TAxxMOD<PWMx1:0> selection clock gear SYSCR1 SYSCR0 (x64) (x128) (x256) <GEAR2:0> <PRCK> TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> TAxxMOD<TAxCLK1:0> φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32) φT1(x2) φT4(x8) φT16(x32) 000(x1) 512/fc 2048/fc 8192/fc 1024/fc 4096/fc 16384/fc 2048/fc 8192/fc...
Page 265 TMP92CF30 3.13 16 bit timer / Event counter (TMRB) The TMP92CF30 incorporates two multifunctional 16-bit timer/event counter (TMRB0, TMRB1) which have the following operation modes: • 16 bit interval timer mode • 16 bit event counter mode • 16 bit programmable pulse generation mode (PPG) Can be used following operation modes by capture function.
Page 266 TMP92CF30 3.13.1 Block diagram Figure 3.13.1 Block diagram of TMRB0 2009-06-12 92CF30-264...
Page 267 TMP92CF30 Figure 3.13.2 Block diagram of TMRB1 2009-06-12 92CF30-265...
Page 268 TMP92CF30 3.13.2 Operation (1) Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (φT0TMR) is selected by the register SYSCR0<PRCK> of clock gear. This prescaler can be started or stopped using TB0RUN<TB0PRUN>. Counting starts when <TB0RUN> is set to “1”;...
Page 269 TMP92CF30 (3) Timer registers (TB0RG0H/L, TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC10 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower timer registers is always needed.
Page 270 TMP92CF30 TB0RG0H/L and the register buffer 10 both have the same memory addresses (1188H and 1189H) allocated to them. If <TB0RDE> = “0”, the value is written to both the timer register and the register buffer 10. If <TB0RDE> = “1”, the value is written to the register buffer 10 only.
Page 271 TMP92CF30 (4) Capture registers (TB0CP0H/L, TB0CP1H/L) These 16-bit registers are used to latch the values in the up counter (UC10). All 16 bits of data in the capture registers should be read. For example, using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte.
Page 272 TMP92CF30 (6) Comparators (CP10, CP11) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively).
Page 273 TMP92CF30 3.13.3 TMRB0 RUN Register − TB0RUN Bit symbol TB0RDE I2TB0 TB0PRUN TB0RUN (1180H) Read/Write Reset State Function Double Always write In IDLE2 TMRB0 Up counter buffer “0” mode prescaler (UC10) 0: disable 0: Stop 0: Stop and clear 1: enable 1: Operate 1: Run (Count up) Count operation...
Page 274 TMP92CF30 TMRB0 Mode Register − − TB0MOD Bit symbol TB0CP0I TB0CPM1 TB0CPM0 TB0CLE TB0CLK1 TB0CLK0 (1182H) Read/Write A read- Reset State modify-write Function Always write “0”. Software Capture timing Control TMRB0 source clock operation capture 00:Disable Up counter 00: TB0IN0 input INT6 occurs at 01: φT1 cannot be...
Page 275 TMP92CF30 TMRB1 Mode Register − − TB1MOD Bit symbol TB1CP0I TB1CPM1 TB1CPM0 TB1CLE TB1CLK1 TB1CLK0 (1192H) Read/Write A read- Reset State modify-write Function Always write “0”. Software Capture timing Control TMRB1 source clock operation capture 00:Disable Up counter 00: TB1IN0 input cannot be INT7 occurs at 01: φT1...
Page 276 TMP92CF30 TMRB0 Flip-Flop Control Register − − TB0FFCR Bit symbol TB0C1T1 TB0C0T1 TB0E1T1 TB0E0T1 TB0FF0C1 TB0FF0C0 (1183H) Read/Write A read Reset State -modify-write Function Always write “11” TB0FF0 inversion trigger Control TB0FF0 operation 0: Disable trigger 00: Invert cannot be *Always read as “11”.
Page 277 TMP92CF30 TMRB0 register − TB0RG0L bit Symbol (1188H) Read/Write Reset State − TB0RG0H bit Symbol (1189H) Read/Write Reset State − TB0RG1L bit Symbol (118AH) Read/Write Reset State − TB0RG1H bit Symbol (118BH) Read/Write Reset State − TB1RG0L bit Symbol (1198H) Read/Write Reset State −...
Page 278 TMP92CF30 3.13.4 Operation in Each Mode (1) 16 bit timer mode Generating interrupts at fixed intervals In this example, the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1H/L. ←...
Page 279 TMP92CF30 (3) 16-bit programmable pulse generation (PPG) output mode Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either low active or high active. The PPG mode is obtained by inversion of the timer flip-flop TB0FF0 that is enabled by the match of the up counter UC10 with timer register TB0RG0H/L or TB0RG1H/L and is output to TB0OUT0.
Page 280 TMP92CF30 The following block diagram illustrates this mode. TB0RUN<TB0RUN> TB0OUT0 (PPG output) Selector TB0IN0 φT1 16-bit up counter φT4 Clear (TB0FF0) UC10 φT16 Match 16-bit comparator 16-bit comparator Selector TB0RG0H/L TB0RG0H/L-WR Register buffer 0 TB0RG1H/L TB0RUN<TB0RDE> Internal data bus Figure 3.13.10 Block Diagram of 16-Bit Mode The following example shows how to set 16-bit PPG output mode: ←...
Page 281 TMP92CF30 (4) Application examples of capture function Used capture function, they can be applied in many ways, for example; One-shot pulse output from external trigger pulse Frequency measurement Pulse width measurement One-shot pulse output from external trigger pulse Set the up counter UC10 in free-running mode with the internal input clock, input the external trigger pulse from TB0IN0 pin, and load the value of up counter into capture register TB0CP0H/L at the rising edge of the TB0IN0 pin.
Page 282 TMP92CF30 Example: To output 2ms one-shot pulse with 3ms delay to the external trigger pulse to TB0IN0 pin *Clock state System clock : Prescaler clock : Main setting Free-running Count with φT1 ← X TB0MOD Load to TB0CP0H/L at the rising edge of TB0IN0 ←...
Page 283 TMP92CF30 Count clock (Prescaler output clock ) c + p TB0IN0 iput Load into capture register 0 (TB0CP0H/L) (External trigger pulse) INT6 occured Load into capture register 1 (TB0CP1H/L) INTTB01 occured Match with TB0RG1H/L Inversion enable Timer output pin TB0OUT0 Pulse width Enable inversioncaused by Disable inversion caused by loading into...
Page 284: Pulse Width Measurement
TMP92CF30 Pulse width measurement This mode allows measuring the H level width of an external pulse. While keeping the 16 bit timer/event counter counting (free-running) with the internal clock input, the external pulse is input through the TB0IN0 pin. Then the capture function is used to load the UC10 values into TB0CP0H/L and TB0CP1H/L at the rising edge and falling edge of the external trigger pulse respectively.
Page 285 TMP92CF30 3.14 Serial Channels (SIO) The TMP92CF30 include 2 serials I/O channel (SIO0 and SIO1). For channels either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. And, SIO0 and SIO1 include data modulator that supports the IrDA 1.0 infrared data communication specification.
Page 286 TMP92CF30 • Mode 0 (I/O interface mode) Bit0 Transfer direction • Mode 1 (7-bit UART mode) No parity Start Bit0 Stop Parity Start Bit0 Parity Stop • Mode 2 (8-bit UART mode) No parity Start Bit0 Stop Parity Start Bit0 Parity Stop •...
Page 287: Block Diagram
TMP92CF30 3.14.1 Block Diagram Prescaler φT0 4 8 16 32 φT2 φT8 φT32 Serial clock generation circuit BR0CR<BR0CK1:0> TA0TRG (from TMRA0) BR0CR BR0ADD <BR0S3:0> <BR0K3:0> φT0 φT2 UART φT8 mode SIOCLK φT32 BR0CR <BR0ADDE> SC0MOD0 SC0MOD0 Baud rate generator <SC1:0> <SM1:0>...
Page 288 TMP92CF30 Prescaler φT0 4 8 16 32 φT2 φT8 φT32 Serial clock generation circuit BR1CR<BR1CK1:0> TA1TRG (from TMRA0) BR1CR BR1ADD <BR1S3:0> <BR1K3:0> φT0 φT2 UART φT8 mode SIOCLK φT32 BR1CR <BR1ADDE> SC1MOD0 SC1MOD0 Baud rate generator <SC1:0> <SM1:0> ÷2 SCLK1 input I/O interface mode SC1CR <IOC>...
Page 289 TMP92CF30 3.14.1.1 Block Diagram Figure 3.14.4 shows the connection image for SIO circuits in TMP92CF30. SIO circuit are built-in 2ch, it can set each signal to P90, P91, P92 or PP3, PP4, PP5. φT0 INTRX0 (to INTC) INTTX0 (to INTC) SIO0 SCLK0 input SCLK0 output...
Page 290 TMP92CF30 3.14.2 Operation of Each Circuit (1) Prescaler There is a 6-bit prescaler for generating a clock to SIO0. The prescaler can be run by selecting the baud rate generator as the serial transfer clock. Table 3.14.2 shows prescaler clock resolution into the baud rate generator. Table 3.14.2 Prescaler Clock Resolution to Baud Rate Generator Baud Rate Generator input clock Clock gear...
Page 291 TMP92CF30 (2) Baud rate generator The baud rate generator is the circuit which generates transmission/receiving clock and determines the transfer rate of the serial channels. The input clock to the baud rate generator, φT0, φT2, φT8 or φT32, is generated by the 6-bit prescaler which is shared by the timers.
Page 292 TMP92CF30 <Integer divider (N divider)> For example, when the source clock frequency (f ) is 19.6608 MHz, the input clock is φT2, the frequency divider N (BR0CR<BR0S3:0>) = 8, and BR0CR<BR0ADDE> = “0”, the baud rate in UART Mode is as follows: *Clock state Clock gear : 1/1...
Page 293 TMP92CF30 Table 3.14.3 Transfer Rate Selection Unit (kbps) (When baud rate generator is used and BR0CR<BR0ADDE> = “0”) φT0 φT2 φT8 φT32 Input Clock [MHz] Frequency Divider N /16) /64) /256) 7.3728 115.200 28.800 7.200 1.800 ↑ 38.400 9.600 2.400 0.600 ↑...
Page 294 TMP92CF30 (3) Serial clock generation circuit This circuit generates the basic clock for transmitting and receiving data. • In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = “0”, the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously.
Page 295 TMP92CF30 (6) The Receiving Buffers To prevent Overrun errors, the Receiving Buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in Receiving Buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in Receiving Buffer 1, the stored data is transferred to Receiving Buffer 2 (SC0BUF);...
Page 296 TMP92CF30 (9) Transmission controller • In I/O Interface Mode In SCLK Output Mode with the setting SC0CR<IOC> = “0”, the data in the Transmission Buffer is output one bit at a time to the TXD0 pin on the rising edge or falling of the shift clock which is output on the SCLK0 pin, according to the SC0CR<SCLKS>...
Page 297: Handshake Function
TMP92CF30 Handshake function Use of pin allows data can to be sent in units of one frame; thus, overrun CTS0 errors can be avoided. The handshake functions is enabled or disabled by the SC0MOD<CTSE> setting. When the pin goes high on completion of the current data send, data CTS0 transmission is halted until the pin goes low again.
Page 298 TMP92CF30 (10) Transmission buffer The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU in order from the least significant bit (LSB). When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt.
Page 299 TMP92CF30 Parity error <PERR> The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated. Note: The parity error flag is cleared every time it is read. However, if a parity error is detected w¥twice in succession and the parity error flag is read between the two parity errors, it may seem as if the flag had not been cleared.
Page 300 TMP92CF30 3.14.3 CTSE SC0MOD0 Bit symbol (1202H) Read/Write Reset State Function Transfer Hand shake Receive Wake up Serial Transmission Serial transmission clock data bit 8 0: CTS function function Mode (UART) disable 0: Receive 0: disable 00: I/O interface Mode 00: TMRA0 trigger 1: CTS disable...
Page 301 TMP92CF30 CTSE SC1MOD0 Bit symbol (120AH) Read/Write Reset State Function Transfer Hand shake Receive Wake up Serial Transmission Serial transmission clock data bit 8 0: CTS function function Mode (UART) disable 0: Receive 0: disable 00: I/O interface Mode 00: *TMRA0 trigger 1: CTS disable 1: enable...
Page 302 TMP92CF30 SC0CR bit Symbol EVEN OERR PERR FERR SCLKS (1201H) Read/Write R (cleared to 0 when read) Reset State Undefined A read Function Received Parity Parity 0: SCLK0 0: baud rate -modify-write data bit 8 0: odd addition generator 1: error operation 1: even 0: disable...
Page 303 TMP92CF30 SC1CR bit Symbol EVEN OERR PERR FERR SCLKS (1209H) Read/Write R (cleared to 0 when read) Reset State Undefined A read Function Received Parity Parity 0: SCLK1 0: baud rate -modify-write data bit 8 0: odd addition generator 1: error operation 1: even 0: disable...
Page 304: Uart Mode
TMP92CF30 − BR0CR Bit symbol BR0ADDE BR0CK1 BR0CK0 BR0S3 BR0S2 BR0S1 BR0S0 (1203H) Read/Write Reset State + (16 − K)/16 00: φ T0 Function Always Divided frequency setting 01: φ T2 write “0” division 10: φ T8 0: Disable 11: φ T32 1: Enable + (16 −...
Page 305 TMP92CF30 − BR1CR Bit symbol BR1ADDE BR1CK1 BR1CK0 BR1S3 BR1S2 BR1S1 BR1S0 (120BH) Read/Write Reset State + (16 − K)/16 00: φ T0 Function Always Divided frequency setting 01: φ T2 write “0” division 10: φ T8 0: Disable 11: φ T32 1: Enable + (16 −...
Page 306 TMP92CF30 (Transmission) SC0BUF (1200H) (Receiving) Note: Prohibit read-modify-write for SC0BUF. Figure 3.14.14 Serial Transmission/Receiving Buffer Registers (channel 0, SC0BUF) SC0MOD1 Bit symbol I2S0 FDPX0 (1205H) Read/Write Reset State Function IDLE2 duplex 0: Stop 0: half 1: Run 1: full Figure 3.14.15 Serial Mode Control Register 1 (channel 0, SC0MOD1) (Transmission) SC1BUF (1208H)
Page 307 TMP92CF30 3.14.4 Operation in each mode (1) Mode 0 (I/O Interface Mode) This mode allows an increase in the number of I/O pins available for transmitting data to or receiving data from an external shift register. This mode includes the SCLK output mode to output synchronous clock SCLK and SCLK input mode to input external synchronous clock SCLK.
Page 308 TMP92CF30 Transmission In SCLK output mode 8-bit data and a synchronous clock are output on the TXD0 and SCLK0 pins respectively each time the CPU writes the data to the Transmission Buffer. When all data is output, INTES0 <ITX0C> will be set to generate the INTTX0 interrupt.
Page 309 TMP92CF30 Receiving In SCLK Output Mode the synchronous clock is output on the SCLK0 pin and the data is shifted to Receiving Buffer 1. This is initiated when the Receive Interrupt flag INTES0<IRX0C> is cleared as the received data is read. When 8-bit data is received, the data is transferred to Receiving Buffer 2 (SC0BUF) following the timing shown below and INTES0<IRX0C>...
Page 310 TMP92CF30 Transmission and Receiving (Full Duplex Mode) When Full Duplex Mode is used, set the Receive Interrupt Level to 0, and only set the interrupt level (from 1 to 6) of the transmit interrupt. Ensure that the program which transmits the interrupt reads the receiving buffer before setting the next transmit data.
Page 311 TMP92CF30 (2) Mode 1 (7-bit UART Mode) 7-Bit UART Mode is selected by setting the Serial Channel Mode Register SC0MOD0<SM1:0> field to “01”. In this mode a parity bit can be added. Use of a parity bit is enabled or disabled by the setting of the Serial Channel Control Register SC0CR<PE>...
Page 312 TMP92CF30 Main routine ← X − − P9CR Set P91 to function as the RXD0 pin. ← − − − − P9FC ← − − − SC0MOD0 Enable receiving in 8-bit UART mode. ← − − − − − − SC0CR Add odd parity.
Page 313 TMP92CF30 Protocol Select 9-Bit UART Mode on the master and slave controllers. Set the SC0MOD0<WU> bit on each slave controller to “1” to enable data receiving. The master controller transmits data one frame at a time. Each frame includes an 8-bit select code which identifies a slave controller.
Page 314 TMP92CF30 Setting example: To link two slave controllers serially with the master controller using the internal clock f as the transfer clock. Master Slave1 Slave 2 Select code Select code 00001010 00000001 Setting the master controller Main routine ← X X X X X − 0 1 P9CR Set P90 and P91 to function as the TXD0 and RXD0 pins ←...
Page 315 TMP92CF30 3.14.5 Support for IrDA SIO0 and SIO1 include support for the IrDA 1.0 infrared data communication specification. Figure 3.14.25 shows the block diagram. TXD0 Transmission IR modulator IR transmitter & LED data IR output SIO0 Modem RXD0 Receive IR receiver IR demodulator data IR input...
Page 316 TMP92CF30 (4) SFR Figure 3.14.28 shows the control register SIR0CR. Set SIR0CR data while SIO0 is stopped. The following example describes how to set this register: 1) SIO setting ; Set the SIO to UART Mode. ↓ ; Set the receive data pulse width to 16 × . 2) LD (SIR0CR), 07H 3) LD (SIR0CR), 37H ;...
Page 317 TMP92CF30 SIR0CR Bit symbol PLSEL RXSEL TXEN RXEN SIR0WD3 SIR0WD2 SIR0WD1 SIR0WD0 (1207H) Read/Write Reset State Function Select Receive Transmit Receive Select receive pulse width transmit data 0: disable 0: disable Set effective pulse width to equal to more than 2x ×...
Page 318 TMP92CF30 SIR1CR Bit symbol PLSEL RXSEL TXEN RXEN SIR1WD3 SIR1WD2 SIR1WD1 SIR1WD0 (120FH) Read/Write Reset State Function Select Receive Transmit Receive Select receive pulse width transmit data 0: disable 0: disable Set effective pulse width to equal to more than 2x ×...
Page 319 TMP92CF30 3.15 Serial Bus Interface (SBI) The TMP92CF30 has a 1-channel serial bus interface which an I C bus mode. This circuit supports only I C bus mode (Multi master). The serial bus interface is connected to an external device through PV6 (SDA) and PV7 (SCL) in the I C bus mode.
Page 320: Bus Mode
TMP92CF30 3.15.2 Serial Bus Interface (SBI) Control The following registers are used to control the serial bus interface and monitor the operation status. • Serial bus interface control register 0 (SBICR0) • Serial bus interface control register 1 (SBICR1) • Serial bus interface control register 2 (SBICR2) •...
Page 321 TMP92CF30 3.15.4 C Bus Mode Control Register The following registers are used to control and monitor the operation status when using the serial bus interface (SBI) in the I C bus mode. Serial Bus Interface Control Register 0 − − −...
Page 322 TMP92CF30 Serial Bus Interface Control Register 1 SCK0/ SBICR1 − SCK2 SCK1 Bit symbol SWRMON (1240H) Read/Write A read- Reset State (Note2) modify-write Function Number of transferred bits Always Internal serial clock selection and Acknowledge operation (Note 1) read as software reset monitor mode cannot be...
Page 323 TMP92CF30 Serial Bus Interface Control Register 2 SBICR2 Bit symbol SBIM1 SBIM0 SWRST1 SWRST0 (1243H) Read/Write W (Note 1) W (Note 1) A read- Reset State modify-write Function Master/Slave Transmitter Start/Stop Cancel Serial bus interface Software reset generate operation selection /Receiver condition INTSBI...
Page 324 TMP92CF30 Serial Bus Interface Status Register SBISR Bit symbol (1243H) Read/Write Reset State A read- Function Master/ Slave Transmitter/ C bus status INTSBI Arbitration Slave GENERAL Last modify-write status Receiver monitor interrupt lost detection address CALL received bit operation monitor status 0:Free request...
Page 325 TMP92CF30 Serial Bus Interface Baud Rate Register 0 − − − − − − − SBIBR0 Bit symbol I2SBI (1244H) Read/Write A read- Reset State modify-write Function Always IDLE2 Always read as “1” Always operation read “0” 0: Stop write “0”. cannot be 1: Run performed...
Page 326 TMP92CF30 3.15.5 Control in I C Bus Mode Acknowledge Mode Specification When slave address is matched or detecting GENERAL CALL, and set the SBICR1<ACK> to “1”, TMP92CF30 operates in the acknowledge mode. The TMP92CF30 generates an additional clock pulse for an Acknowledge signal when operating in Master Mode.
Page 327 TMP92CF30 Clock synchronization In the I C bus mode, in order to wired-AND a bus, a master device which pulls down a clock line to low-level, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The master device with a high-level clock pulse needs to detect the situation and implement the following procedure.
Page 328 TMP92CF30 Transmitter/Receiver selection Set the SBICR2<TRX> to “1” for operating the TMP92CF30 as a transmitter. Clear the <TRX> to “0” for operation as a receiver. In Slave Mode, • Data with an addressing format is transferred • A slave address with the same value that an I2CAR •...
Page 329 TMP92CF30 Interrupt service requests and interrupt cancellation When a serial bus interface interrupt request (INTSBI) occurs, the SBICR2 <PIN> is cleared to “0”. During the time that the SBICR2<PIN> is “0”, the SCL line is pulled down to the Low level. The <PIN>...
Page 330 TMP92CF30 The TMP92CF30 compares the levels on the bus’s SDA line with those of the internal SDA output on the rising edge of the SCL line. If the levels do not match, arbitration is lost and SBISR<AL> is set to “1”. When SBISR<AL>...
Page 331 TMP92CF30 (14) Software Reset function The software Reset function is used to initialize the SBI circuit, when SBI is rocked by external noises, etc. An internal Reset signal pulse can be generated by setting SBICR2<SWRST1:0> to “10” and “01”. This initializes the SBI circuit internally. All command registers and status registers are initialized as well.
Page 332 TMP92CF30 3.15.6 Data Transfer in I C Bus Mode (1) Device initialization Set the SBICR1<ACK, SCK2:0>, Set SBIBR1 to “1” and clear bits 7 to 5 and 3 in the SBICR1 to “0”. Set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing format) to the I2CAR.
Page 333 TMP92CF30 Slave Mode In the Slave Mode, the start condition and the slave address are received. After the start condition is received from the master device, while eight clocks are output from the SCL pin, the slave address and the direction bit that are output from the master device are received.
Page 334 TMP92CF30 (3) 1-word Data Transfer Check the <MST> by the INTSBI interrupt process after the 1-word data transfer is completed, and determine whether the mode is a master or slave. If <MST> = “1” (Master Mode) Check the <TRX> and determine whether the mode is a transmitter or receiver. When the <TRX>...
Page 335 TMP92CF30 When the <TRX> is “0” (Receiver mode) When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and read the received data from SBIDBR to release the SCL line (data which is read immediately after a slave address is sent is undefined). After the data is read, <PIN>...
Page 336 TMP92CF30 Example: In case receive data N times INTSBI interrupt (After transmitting data) 7 6 5 4 3 2 1 0 SBICR1 ← X X X X X X X X Set the bit number of receive data and ACK. ←...
Page 337 TMP92CF30 If <MST> = 0 (Slave Mode) In the slave mode the TMP92CF30 operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, an INTSBI interrupt request occurs when the TMP92CF30 receives a slave address or a GENERAL CALL from the master device, or when a GENERAL CALL is received and data transfer is complete, or after matching received address.
Page 338 TMP92CF30 Table 3.15.2 Operation in the slave mode <TRX> <AL> <AAS> <AD0> Conditions Process The TMP92CF30 loses arbitration when Set the number of bits a word in transmitting a slave address and <BC2:0> and write the transmitted data receives a slave address for which the to SBIDBR value of the direction bit sent from another master is “1”.
Page 339 TMP92CF30 (4) Stop condition generation When SBISR<BB> = “1”, the sequence for generating a stop condition start by writing “1” to SBICR2<MST, TRX, PIN> and “0” to SBICR2<BB>. Do not modify the contents of SBICR2<MST, TRX, PIN, BB> until a stop condition has been generated on the bus.
Page 340 TMP92CF30 (5) Restart Restart is used during data transfer between a master device and a slave device to change the data transfer direction. The following description explains how to restart when the TMP92CF30 is in Master Mode. Clear SBICR2<MST, TRX, and BB> to “0” and set SBICR2<PIN> to “1” to release the bus.
Page 341: Usb Controller
TMP92CF30 3.16 USB Controller 3.16.1 Outline This USB controller (UDC) is designed to support a variety of serial links in the construction of a USB system. The outline is as follows: (1) Compliant with USB rev1.1 (2) Full-speed: 12 Mbps (low-speed (1.5 Mbps) not supported) (3) Auto bus enumeration with 384-byte descriptor RAM (4) Supports 3 kinds of transfer type: Control, interrupt and bulk •...
Page 342 TMP92CF30 3.16.1.1 System Configuration The USB controller (UDC) consists of the following 3 blocks. 900/H1 CPU I/F (details given in Section 3.16.2, below). UDC core block (DPLL, SIE, IFM and PWM), request controller, descriptor RAM and 4 endpoint FIFO (details given in Section 3.16.3, below). USB transceiver Descriptor RAM 384 bytes...
Page 343 TMP92CF30 3.16.1.2 Example USB host USB device USB host TMP92CF30 Connector Connector VBUS INTx (detect rising) 10MHz PorTXX cable X1USB 48MHz D− OFF at OFF at “H” "H" The above setting is required If when using the TMP92CF30’s USB controller. 1) Pull-up of D ・...
Page 344 TMP92CF30 5) HOST side pull-down resistor ・ In the USB standard, set pull-down D pin and D signal at USB_HOST side. Recommended value: R8=15kΩ, R9=15kΩ Note: The above connections and resistor values, etc, are given as examples only. Operation is not guaranteed.
Page 345: Usb Control
TMP92CF30 3.16.2 900/H1 CPU I/F The 900/H1 CPU I/F is a bridge between the 900/H1 CPU and the UDC. Its main functions are as follow. • INTUSB (interrupt from UDC) generation • A bridge for SFR • USB clock control (48 MHz) 3.16.2.1 SFRs The 900/H1 CPU I/F incorporates the following SFRs to control the UDC and USB transceiver.
Page 346 TMP92CF30 3.16.2.2 USBCR1 Register This register is used to set USB clock enables, transceiver enable etc. TRNS_USE WAKEUP SPEED USBCLKE USBCR1 bit Symbol (07F8H) Read/Write Reset State Function • TRNS_USE (Bit7) 0: Disable USB transceiver 1: Enable USB transceiver Always set to “1” on the application using USB. •...
Page 347 TMP92CF30 3.16.2.3 USBINTFRn, MRn Register These SFRs control the INTUSB (only one interrupt to CPU) using the 23 interrupt sources output by the UDC. The USBINTMRn are mask registers and the USBINTFRn are flag registers. In the INTUSB routine, execute operations according to generated interrupt source after checking USBINTFRn.
Page 348 TMP92CF30 INT_URST_STR bit Symbol INT_URST_END INT_SUS INT_RESUME INT_CLKSTOP INT_CLKON USBINTFR1 (07F0H) Read/Write Prohibit to Reset State read- When read 0: Not generate interrupt When write 0: Clear flag Function 1: − modify- 1: Generate interrupt write Note: The above interrupts can release Halt state from IDLE2 and IDLE1 mode. (STOP mode cannot be released) *Those 6 interrupts of all 24 INTUSB sources can release Halt state from IDLE1 mode.
Page 349 TMP92CF30 bit Symbol EP1_FULL_A EP1_Empty_A EP1_FULL_B EP1_Empty_B EP2_FULL_A EP2_Empty_A EP2_FULL_B EP2_Empty_B USBINTFR2 (07F1H) Read/Write Prohibit to Reset State read When read 0: Not generate interrupt When write 0: Clear flag Function 1: − -modify 1: Generate interrupt -write Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.) bit Symbol EP3_FULL_A EP3_Empty_A...
Page 350 TMP92CF30 bit Symbol INT_SETUP INT_EP0 INT_STAS INT_STASN INT_EP1N INT_EP2N INT_EP3N USBINTFR4 Read/Write (07F3H) Prohibit to Reset State read Function When read 0: Not generate interrupt When write 0: Clear flag -modify 1: − 1: Generate interrupt -write Note: The above interrupt can release Halt state from IDLE2 mode. (IDLE1 and STOP mode cannot be released.) •...
Page 351 TMP92CF30 • INT_STASN (Bit4) This is the flag register for INT_STASN (change host status stage - interrupt). This is set to “1” when the USB host changes to status stage at the Control read transfer. This interrupt is needed if data length is less than wLength (specified by the host).
Page 352 TMP92CF30 bit Symbol MSK_URST_STR MSK_URST_END MSK_SUS MSK_RESUME MSK_CLKSTOP MSK_CLKON USBINTMR1 (07F4H) Read/Write Reset State When read 0: not masked When write 0: Clear flag Function 1: − 1: masked • MSK_URST_STR (Bit7) This is the mask register for USBINTFR1<INT_URST_STR>. • MSK_URST_END (Bit6) This is the mask register for USBINTFR1<INT_URST_END>.
Page 353 TMP92CF30 bit Symbol EP1_MSK_FA EP1_MSK_EA EP1_MSK_FB EP1_MSK_EB EP2_MSK_FA EP2_MSK_EA EP2_MSK_FB EP2_MSK_EB USBINTMR2 (07F5H) Read/Write Reset State Function When read 0: not masked When write 0: Clear flag 1: − 1: masked • EP1/2_MSK_FA/FB/EA/EB This mask register USBINTFR2<EPx_FULL_A/B> <EPx_Empty_A/B>. bit Symbol EP3_MSK_FA EP3_MSK_EA USBINTMR3...
Page 354 TMP92CF30 bit Symbol MSK_SETUP MSK_EP0 MSK_STAS MSK_STASN MSK_EP1N MSK_EP2N MSK_EP3N USBINTMR4 (07F7H) Read/Write Reset State Function When read 0: Be not masked When write 0: Clear flag 1: − 1: Be masked • MSK_SETUP (Bit7) This is the mask register for USBINTFR4<INT_SETUP>. •...
Page 355 TMP92CF30 3.16.3 UDC CORE 3.16.3.1 SFRs The UDC CORE has the following SFRs to control the UDC and USB transceiver. FIFO Endpoint 0 to 3 FIFO register Device request bmRequestType register bRequest register wValue_L register wValue_H register wIndex_L register wIndex_H register wLength_L register...
Page 356 TMP92CF30 Table 3.16.2 UDC CORE SFRs (1/3) Address Read/Write SFR Symbol 0500H Descriptor RAM0 0501H Descriptor RAM1 0502H Descriptor RAM2 0503H Descriptor RAM3 067DH Descriptor RAM381 067EH Descriptor RAM382 067FH Descriptor RAM383 0780H ENDPOINT0 0781H ENDPOINT1 0782H ENDPOINT2 0783H ENDPOINT3 *0784H ENDPOINT4 *0785H...
Page 357 TMP92CF30 Table 3.16.3 UDC CORE SFRs (2/3) Address Read/Write SFR Symbol 07A9H EP1_SIZE_H_A 07AAH EP2_SIZE_H_A 07ABH EP3_SIZE_H_A *07ACH EP4_SIZE_H_A *07ADH EP5_SIZE_H_A *07AEH EP6_SIZE_H_A *07AFH EP7_SIZE_H_A 07B1H EP1_SIZE_H_B 07B2H EP2_SIZE_H_B 07B3H EP3_SIZE_H_B *07B4H EP4_SIZE_H_B *07B5H EP5_SIZE_H_B *07B6H EP6_SIZE_H_B *07B7H EP7_SIZE_H_B 07C0H bmRequestType 07C1H bRequest...
Page 358 TMP92CF30 Table 3.16.4 UDC CORE SFRs (3/3) Address Read/Write SFR Symbol 07E0H Port_Status 07E1H FRAME_L 07E2H FRAME_H 07E3H ADDRESS – *07E4H Reserved – *07E5H Reserved 07E6H USBREADY – *07E7H Reserved 07E8H Set Descriptor STALL Note: “*” is not used in the TMP92CF30. 2009-06-12 92CF30-356...
Page 359 TMP92CF30 3.16.3.2 EPx_FIFO Register (x: 0 to 3) This register is prepared for each endpoint independently. This is the window register from or to FIFO RAM. In the auto bus enumeration, the request controller in UDC sets the mode, which is defined by the endpoint descriptor for each endpoint automatically.
Page 360 TMP92CF30 3.16.3.3 bmRequestType Register This register shows the bmRequestType field of the device request. bit Symbol bmRequestType DIRECTION REQ_TYPE1 REQ_TYPE0 RECIPIENT4 RECIPIENT3 RECIPIENT2 RECIPIENT1 RECIPIENT0 (07C0H) Read/Write Reset State DIRECTION (Bit7) 0: from host to device 1: from device to host REQ_TYPE [1:0] (Bit6 to bit5) 00: Standard 01: Class...
Page 361 TMP92CF30 3.16.3.5 wValue Register There are 2 registers; the wValue_L register and wValue_H register. wValue_L shows the lower-byte of the wValue field of the device request, and wValue_H register shows the upper byte. wValue_L bit Symbol VALUE_L7 VALUE_L6 VALUE_L5 VALUE_L4 VALUE_L3 VALUE_L2 VALUE_L1...
Page 362 TMP92CF30 3.16.3.8 Setup Received Register This register informs the UDC that an application program has recognized the INT_SETUP interrupt. bit Symbol SetupReceived (07C8H) Read/Write Reset State If this register is accessed by an application program, the UDC disables access to the EP0’s FIFO RAM because the UDC recognizes the device request has been received.
Page 363 TMP92CF30 3.16.3.10 Standard Request Register This register shows the standard request currently being executed. Any bit which is set to “1” shows a request currently being executed. bit Symbol S_CONFIG G_CONFIG G_DESCRIPT S_FEATURE C_FEATURE G_STATUS Standard Request S_INTERFACE G_INTERFACE (07CAH) Read/Write Reset State S_INTERFACE...
Page 364 TMP92CF30 3.16.3.12 DATASET Register This register shows whether FIFO contains data or not. The application program can access this register to check whether FIFO contains data or not. In the receiving status, when valid data transfer from the USB host has finished, the bit which corresponds to the corresponding endpoint is set to “1”...
Page 365 TMP92CF30 Note1: In receive mode, if the endpoint bits corresponding to packet-A or paclet-B are “1”, read the required packet-number data after checking EPx_SIXE<PKT_ACTIVE>. Note2: In transmit mode, if both A and B bits are not “1”, this means there is space in FIFO. So, write data of payload or less to FIFO.
Page 366 TMP92CF30 3.16.3.13 EPx_STATUS Register (x: 0 to 7) These registers are status registers for each endpoint. The <SUSPEND> is common to all endpoints. EP0_STATUS bit Symbol TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR (0790H) Read/Write Reset State EP1_STATUS bit Symbol TOGGLE SUSPEND STATUS[2]...
Page 367 TMP92CF30 STATUS [2:0] These bits show status of UDC endpoint. (Bit4 to bit2) The status shows whether transfer is possible or not, and the result of the transfer. These depend on transfer type. (For the Isochronous transfer type, refer to 3.16.9.) 000: READY Receiving: Device can be received.
Page 368 TMP92CF30 FIFO_DISABLE (Bit1) This bit symbol shows FIFO status except for EP0. If the FIFO is set to disabled, the UDC transmits NAK 0: FIFO enabled 1: FIFO disabled handshake for all transfers. Disabled or enabled status is set the COMMAND register.
Page 369 TMP92CF30 3.16.3.14 EPx_SIZE Register (x: 0 to 7) These registers have the following functions. a) In receive mode, showing the 1-packet data number which has been received correctly. b) In the transmit mode, showing payload size. Showing length value when short packet is transferred.
Page 370 TMP92CF30 bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 EP1_SIZE_L_B (07A1H) Read/Write Reset State bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 EP2_SIZE_L_B (07A2H) Read/Write Reset State bit Symbol PKT_ACTIVE DATASIZE6 DATASIZE5 DATASIZE4 DATASIZE3 DATASIZE2 DATASIZE1 DATASIZE0 EP3_SIZE_L_B (07A3H) Read/Write...
Page 371 TMP92CF30 bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 EP1_SIZE_H_A (07A9H) Read/Write Reset State bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 EP2_SIZE_H_A (07AAH) Read/Write Reset State bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 EP3_SIZE_H_A (07ABH) Read/Write Reset State bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 EP4_SIZE_H_A (07ACH) Read/Write Reset State bit Symbol DATASIZE9 DATASIZE8 DATASIZE7 EP5_SIZE_H_A...
Page 372 TMP92CF30 bit Symbol EP1_SIZE_H_B DATASIZE9 DATASIZE8 DATASIZE7 (07B1H) Read/Write Reset State bit Symbol EP2_SIZE_H_B DATASIZE9 DATASIZE8 DATASIZE7 (07B2H) Read/Write Reset State bit Symbol EP3_SIZE_H_B DATASIZE9 DATASIZE8 DATASIZE7 (07B3H) Read/Write Reset State bit Symbol EP4_SIZE_H_B DATASIZE9 DATASIZE8 DATASIZE7 (07B4H) Read/Write Reset State bit Symbol EP5_SIZE_H_B DATASIZE9...
Page 373 TMP92CF30 3.16.3.15 FRAME Register This register shows the frame number which is issued with SOF token from the host and is used for Isochronous transfer type. Each HIGH and LOW register shows upper and lower bits. − FRAME_L bit Symbol T[6] T[5] T[4]...
Page 374 TMP92CF30 3.16.3.17 EOP Register This register is used when a control transfer type dataphase terminates or when a short packet is transmitting bulk-IN or interrupt-IN. EP7_EOPB EP6_EOPB EP5_EOPB EP4_EOPB EP3_EOPB EP2_EOPB EP1_EOPB EP0_EOPB bit Symbol (07CFH) Read/Write Reset State Note1: EOP<EP7_EOPB, EP6_EOPB, EP5_EOPB, EP4_EOPB> registers are not used in the TMP92CF30. Note2: When writing to this register, a recovery time of 5clocks at 12MHz is needed.
Page 375 TMP92CF30 3.16.3.18 Port Status Register This register is used when a request of printer class request is received. In the case of a GET_PORT_STATUS request, the UDC operates automatically using this data. Port Status bit Symbol Reserved7 Reserved6 PaperError Select NotError Reserved2 Reserved1...
Page 376 TMP92CF30 3.16.3.20 Request Mode Register This register sets the answer for Class Request either automatically in hardware or by control through software. Each bit represents a kind of request. When relevant bit in this register is set to “0”, the answer is executed automatically by hardware.
Page 377 TMP92CF30 3.16.3.21 COMMAND Register This register sets COMMAND at each endpoint. This register can be set to select of endpoint in bit6 to bit4 and kind of COMMAND in bit3 to bit0. COMMAND for endpoint that is supported is ignored. COMMAND bit Symbol EP[2]...
Page 378 TMP92CF30 1000: FIFO_ENABLE This COMMAND sets FIFO of corresponding endpoint to enable (EP1 to EP3). If FIFO is set to disable by FIFO_DISABLE COMMAND, this command is used for release of disable condition. If set while receiving packet, this becomes valid from next token.
Page 379 TMP92CF30 3.16.3.22 INT_Control Register INT_STASN interrupt is disabled and enabled by the value that is written to this register. This is initialized to disable by external reset. When setup packet is received, it becomes disabled. INT_Control bit Symbol Status_nak (07D6H) Read/Write Reset State In control read transfer, if the host terminates a dataphase with small data length...
Page 380 TMP92CF30 3.16.3.24 EPx_MODE Register (x: 1 to 3) This register sets transfer mode of endpoint (EP1 to EP3). If SET_CONFIG and SET_INTERFACE processing is set to software control, this control must use appointed config or interface. Access this register to set mode. EP1_MODE bit Symbol Payload[2]...
Page 381 TMP92CF30 3.16.3.25 EPx_SINGLE Register This register sets mode of FIFO in each endpoint (SINGLE/DUAL). EPx_SINGLE1 bit Symbol EP3_SELECT EP2_SELECT EP1_SELECT EP3_SINGLE EP2_SINGLE EP1_SINGLE (07D1H) Read/Write Reset State Note: Endpoint 3 support only SINGLE mode in the TMP92CF30. Bit number 0: No use 1: EP1_SINGLE 2: EP2_SINGLE 3: EP3_SINGLE...
Page 382 TMP92CF30 3.16.3.27 USBREADY Register This register informs finishing writing data to descriptor RAM on UDC. After assigned data to descriptor RAM, write “0” to bit0. USBREADY bit Symbol USBREADY (07E6H) Read/Write Reset State USBREADY (Bit0) 0: Writing to descriptor RAM has finished. 1: Writing to descriptor RAM is enabled.
Page 383 TMP92CF30 3.16.3.28 Set Descriptor STALL Register This register sets whether returns STALL automatically in data stage or status stage for Set Descriptor Request. bit Symbol S_D_STALL Set Descriptor STALL Read/Write (07E8H) Reset State Bit0: S_D_STALL 0: Software control (Default) 1: Automatically STALL 3.16.3.29 Descriptor RAM Register This register is used for store descriptor to RAM.
Page 384 TMP92CF30 3.16.4 Descriptor RAM This area stores the descriptor that is defined in USB. Device, Config, Interface, Endpoint and String descriptor must set to RAM using the following format. Device descriptor 18 bytes Config 1 descriptor (Interfaces, endpoints) 255 bytes or less Config 2 descriptor (Interfaces, ENDPOINT) 255 bytes or less...
Page 385 USB Spec 1.00 503H bcdUSB (H) IFC’s specify own 504H bDeviceClass 505H bDeviceSubClass 506H bDeviceProtocol 507H bMaxPacketSize0 508H bVendor (L) Toshiba 509H bVendor (H) 50AH IdProduct (L) 50BH IdProduct (H) 50CH bcdDevice (L) Release 1.00 50DH bcdDevice (H) 50EH bManufacture...
Page 386 TMP92CF30 Address Data Description Description Interface0 Descriptor AlternateSetting1 52BH bLength 52CH bDescriptorType Interface Descriptor 52DH bInterfaceNumber 52EH bAlternateSetting AlternateSetting1 52FH bNumEndpoints 530H bInterfaceClass 531H bInterfaceSubClass 532H bInterfaceProtocol 533H iInterface Endoint1 Descriptor 534H bLength 535H bDescriptorType Endpoint Descriptor 536H bEndpointAddress 537H bmAttributes BULK 538H...
Page 387 565H bDescriptorType String Descriptor 566H bString Language ID 0x0409 567H bString String Descriptor1 568H bLength 569H bDescriptorType String Descriptor 56AH bString (Toshiba) 56BH bString 56CH bString 56DH bString 56EH bString 56FH bString 570H bString 571H bString 572H bString 573H...
Page 388 TMP92CF30 3.16.5 Device Request 3.16.5.1 Standard request UDC support automatically answer in standard request. (1) GET_STATUS Request This request automatically returns to status that is determined by receive side. bmRequestType bRequest wValue wIndex wLength Data 10000000B GET_STATUS Device, interface or endpoint status 10000001B Interface...
Page 389 TMP92CF30 (2) CLEAR_FEATURE request This request clears or disables the relevant function. bmRequestType bRequest wValue wIndex wLength Data 00000000B CLEAR_ Feature None FEATURE selector Interface 00000001B endpoint 00000010B • Reception side device Feature selector: 1 Present remote wakeup setting is disabled. Feature selector: except 1 STALL state •...
Page 390 TMP92CF30 (4) SET_ADDRESS request This request sets the device address. Answer subsequent requests using this device address. Answer requests using the current device address until the status stage of this request is terminated normally. bmRequestType bRequest wValue wIndex wLength Data 00000000B SET_ADDRESS Device Address...
Page 391 TMP92CF30 (6) SET_DESCRIPTOR request This request sets or enables the relevant function. bmRequestType bRequest wValue wIndex wLength Data 00000000B SET_ Descriptor type Descriptor Descriptor Descriptor length Descriptor index Language ID Automatic answer of this request is not supported. According to INT_SETUP interrupt, if the receiving requested has been identified as a SET_DESCRIPTOR request, take back data after confirming EP0_DSET_A bit of DATASET register is “1”.
Page 392 TMP92CF30 (9) GET_INTERFACE request This request returns AlternateSetting value that is set by specified interface. bmRequestType bRequest wValue wIndex wLength Data 10000001B GET_ Interface Alternate INTERFACE setting If there is no specified interface, it enters to STALL state. (10) SET_INTERFACE request This request selects AlternateSetting in specified interface.
Page 393 TMP92CF30 3.16.5.2 Printer Class Request UDC does not support “Automatic answer” of printer class request. Processing of Class requests is the same as for vendor requests when answering INT_SETUP interrupt. 3.16.5.3 Vendor request (Class request) UDC does not support “Automatic answer” of Vendor requests. According to INT_SETUP interrupt, access the register in which the device request is stored, and identify the request.
Page 394 TMP92CF30 (b) Control write/request There is no dataphase bmRequestType bRequest wValue wIndex wLength Data 010000xxB Vendor specific Vendor specific Vendor specific None When INT_SETUP is received, identify contents of request by bmRequestType, bRequest, wValue, wIndex, wLength registers and process each request. According to application, access Setup_Received register after request has been identified.
Page 395 TMP92CF30 Below is control flow in UDC as seen from application. Start up Setting each EP mode in Set_Config (Interface) IDLE Standard request Printerclass request Enumeration Identify request RD Access to SetupReceived register Control RD transfer Control WR transfer Get_Vendor_Request Set_Vendor_Request process process...
Page 396 TMP92CF30 3.16.6 Transfer mode and Protocol Transaction The UDC performs the following automatically in hardware; • Receive packet • Determine address endpoint transfer mode • Error process • Confirm toggle bit CRC of data receiving packet • Generate toggle bit CRC of data transmitting packet, etc •...
Page 397 TMP92CF30 (2) Transfer mode UDC supports FULL speed transfer mode. • FULL speed device Control transfer type Interrupt transfer type Bulk transfer type Isochronous transfer type The following is an explanation of UDC operation in each transfer mode. The explanation is of data flow up until FIFO. (a) Bulk transfer type Bulk transfer type warrants transferring no error between host and function by using detect error and retry.
Page 398 TMP92CF30 (a-1) Transmission bulk mode Below is the transaction format for bulk transfer during transmitting. • Token: IN • Data: DATA0/DATA1, NAK, STALL • Handshake: ACK Control flow Below is the control-flow when the UDC receive an IN token. The token packet is received and the address endpoint number error is confirmed, and it checks whether the relevant endpoint transfer mode corresponds with the IN token.
Page 399 TMP92CF30 IDLE Receive IN token Error ConfirmToken packet • PID • Address • Endpoint • Transfer mode • Error Invalid Confirm Handshake answer Stall • Confirm STATUS register (Status) • Confirm DATASET register FIFO empty More than MAX Generate DATA PID Transmit NAK Transmit STALL payload...
Page 400 TMP92CF30 (a-2) Receiving bulk mode Below is the transaction format for receiving bulk transfer type. • Token: OUT • Data: DATA0/DATA1 • Handshake: ACK, NAK, STALL Control flow Below is the control-flow when the UDC receive an IN token. The token packet is received and the address endpoint number error is confirmed, and it checks whether the relevant endpoint transfer mode corresponds with the OUT token.
Page 401 TMP92CF30 IDLE Receive OUT token Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Invalid Confirm Status Stall • Confirm STATUS register (status) • Confirm FIFO’s condition FIFO empty,FIFO_DISABLE Generate DATA PID Generate DATA PID Generate DATA PID •...
Page 402 TMP92CF30 (b) Interrupt transfer type Interrupt transfer type uses the same transaction format as transmission bulk transfer. For transmission using toggle bit, hardware setting and answer in the UDC are the same as for transmission bulk transfer. Interrupt transfer can be transferred without using toggle bit.
Page 403 TMP92CF30 (c) Control transfer type Control transfer type is configured in the three stages below. • Setup stage • Data stage • Status stage Data stage is sometimes skipped. Each stage is configured in one or several transactions. The UDC executes each transaction while managing three stages in hardware.
Page 404 TMP92CF30 3. Data packet is received. Device request of 8 bytes from SIE in UDC is transferred to the request register below. • bmRequestType register • bmRequest register • wValue register • wIndex register • wLength register 4. After last data is transferred, counted CRC is compared with transferred CRC. If they do not correspond, STATUS is set to RX_ERR and the state returns to IDLE.
Page 405 TMP92CF30 IDLE Receive SETUP token Error Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Invalid Error transaction • Set STATUS to RX_ERR • Put back FIFO address point Confirm Status • Confirmation STATUS register (Status) Except DATA0 PID Confirm DATA PID •...
Page 406 TMP92CF30 (c-2) Data stage Data stage is configured by one or several transactions based on toggle sequence. The transaction is the same as for format transmission or receiving bulk transaction except for the following differences; • Toggle bit starts from “1” by SETUP stage. •...
Page 407 TMP92CF30 If ACK handshake from host is received, • Set STATU to READY. • Assert INT_STATUS interrupt. It finishes normally by the above transaction. If a time out occurs without receiving ACK from host, • Set STATUS register to TX_ERR and state returns to IDLE and wait for restring status stage.
Page 408 TMP92CF30 (c-4) Stage management The UDC manages each stage of control transfer by hardware. Each stage is changed by receiving token from USB host, or CPU accesses register. Each stage in control transfer type has to process combination software. UDC detects the following contents from 8-byte data in SETUP stage.
Page 409 TMP92CF30 Stage change condition of control read transfer type Receive SETUP token from host • Start setup stage in UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt externally. • Change data stage in the UDC. Receive IN token from host •...
Page 410 TMP92CF30 Stage change condition of control write transfer type Receive SETUP token from host. • Start setup stage in the UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt externally. • Change data stage in the UDC. Receive OUT token from host.
Page 411 TMP92CF30 Stage change condition of control write (no data stage) transfer type Receive SETUP token from host • Start setup stage in the UDC. • Receive data in request normally and judge. And assert INT_SETUP interrupt externally. • Change data stage in the UDC. Receive IN token from host •...
Page 412 TMP92CF30 (d) Isochronous transfer type Isochronous transfer type is guaranteed transfer by data number that is limited to each frame. However, this transfer does not retry when an error occurs. Therefore, Isochronous transfer type transfer only 2 phases (token, data) and it does not use handshake phase.
Page 413 TMP92CF30 5. Below is transaction when SOF token is received from host. • Change the packet A’s FIFO from X Condition to Y Condition and clear data. • Change the packet B from Y Condition to X Condition. • Set frame number to frame register. •...
Page 414 TMP92CF30 IDLE Receive SOF Clear X condition (A) Receive IN token without transmitting data Set FULL to STATUS Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Confirm Status Invalid • Confirm STATUS register (status) Generate DATA PID •...
Page 415 TMP92CF30 (d-2) Isochronous receiving mode Transaction format for Isochronous transfer type in receiving is given below. • Token :OUT • Data : DATA0 Control flow Isochronous transfer type is frame management. And data that is written to FIFO by OUT token is received to the CPU in the next frame. Below are two conditions in FIFO of Isochronous receiving mode transferring X.
Page 416 TMP92CF30 In renewed frame, Packet A’s FIFO interchanges with packet B’s FIFO, and the transaction uses the same flow. If SOF token is not received by error and so on, this data is lost because the frame is not renewed. There is no problem in receiving PID and if frame data is received with CRC error, USB sets LOST to STATUS on FRAME register, and exact frame number is unknown.
Page 417 TMP92CF30 IDLE Receive SOF Clear X Condition (A) Receive OUT token without transmitting data Set FULL to STATUS Confirm Token packet • PID • Address • Endpoint • Transfer mode • Error Invalid Confirm Status Confirming STATUS register (status) Confirm DATA PID Error, time out exept data PID •...
Page 418 TMP92CF30 3.16.7 Bus Interface and Access to FIFO (1) CPU bus interface The UDC prepares two types of FIFO access, single packet and dual packet. In single packet mode, FIFO capacity that is implemented by hardware is used as large FIFO.
Page 419 TMP92CF30 (a) Single packet mode This is data sequence of single packet mode when CPU bus interface is used. Figure 3.16.13 is receiving sequence. Figure 3.16.14 is transmitting sequence. This chapter focuses on access to FIFO. For Data sequence with USB host refer to chapter 5.
Page 420 TMP92CF30 Below is the transmitting sequence in single packet mode. Wait transmission event IDLE Transmission event DATASET register • Check bit of EPx_DSET_A Distinction transmitting number Transmitting number ≤ payload Transmitting number > payload • Write payload number in relevant endpoint •...
Page 421 TMP92CF30 (b) Dual packet mode In dual packet mode, FIFO is divided into A and B packet, and is controlled according to priority in hardware. It can be performed at once, transmitting and receiving data to USB host and exchanges to external of UDC. When it reads out data from FIFO for receiving, confirm condition of two packets, and consider the order of priority.
Page 422 TMP92CF30 Data can be set to available FIFO when transmitting regardless of packet A or B. Below is the Transmitting Sequence in Dual Packet Mode. Wait transmitting event IDLE Transmitting event DATASETregister • Check bit of EPx_DSET_A • Check bit of EPx_DSET_B Transmittind data distinction Transmitting number <...
Page 423: Interrupt Control
TMP92CF30 (c) Issuance of NULL packet If transmitting NULL packet, by input L pulse from EPx_EOPB signal, data of 0 length is set to FIFO, and NULL packet can be transferred to IN token. But if NULL data is set to FIFO, it is valid only in the case whole SET signal is L level condition (where FIFO is empty).
Page 424 TMP92CF30 3.16.8 USB Device answer The USB controller (UDC) sets various register and initialization in the UDC in detecting of hardware reset, detecting of USB bus reset, and enumeration answer. Each condition is explained below. (1) bus reset detect condition. When the UDC detects a bus reset on the USB signal line, it initializes internal register, and it prepares enumeration operation from USB host.
Page 425 TMP92CF30 ISO transfer mode Below is the transfer condition for the previous frame. Receiving SOF renews this. OUT (RX) IN (TX) Initial READY READY Not transfer READY FULL Finish normally DATAIN READY Detect an error RXERR TXERR Transfer modes other than ISO transfer This is the result of the previous transfer.
Page 426 TMP92CF30 3.16.9 Power Management USB controller (UDC) can be switched from optional resume condition (turn on the power supply condition) to suspend (Suspension) condition, and it can be returned from suspend condition to turn on the power supply condition. This function can be set to low electricity consumption by operating CLK supplying for UDC.
Page 427 TMP92CF30 (4) Low power consumption by control of CLK input signal When the UDC switches to suspend condition, it stops CLK and switches to low power consumption condition. But as system, this function enables low power consumption by stopping source of CLK. CLK that is supplied to the UDC can be controlled using USBINTFR1<INT_SUS>,...
Page 428 TMP92CF30 • Return from suspend condition by USB reset (by INT_CLKON interrupt) When UDC stops CLK in suspend condition, UDC can not detect USB reset and control CLK in suspend condition as above mentioned. In case CLK is stopped in suspend condition, UDC can detect USB reset and return from suspend condition by supplying CLK (USBCR1<USBCLKE>=1) after detecting INT_CLKON interrupt.
Page 429 TMP92CF30 3.16.10 Supplement (1) External access flow to USB communication Normal movement SETUP DATA0 ACK DATA1 DATA0 DATA1 INT_SETUP INT_ ENDPOINT0 INT_STATUS REQUEST FLAG EP0 FIFO access Request access Setup Received access EOP register access Stage error SETUP DATA0 ACK DATA1 DATA0 SETUP...
Page 430 TMP92CF30 (2) Register Initial value Initial Value Initial Value Register Name Initial Value Register Name Initial Value OUTSIDE Reset USB_RESET OUTSIDE Reset USB_RESET bmRequestType 0x00 0x00 INT control 0x00 0x00 bRequest 0x00 0x00 USBBUFF_TEST 0x00 Hold wValue_L 0x00 0x00 USB state 0x01 0x01 wValue_H...
Page 431 TMP92CF30 (3) USB control flow chart (a) Transaction for standard request (Outline flowchart (Example)) USB interrupt Call USBINT0 function Evaluate Interrupt SETUP ENDPOINT 0 STATUS STATUS NAK ENDPOINT 1 transaction transaction transaction transaction transaction 2009-06-12 92CF30-429...
Page 432 TMP92CF30 (b) Condition change Turn on power supply Initialization transaction Normal finish/No transaction Waiting USB interrupt condition Transmit Request error/Transmit STALL Receive USB token Transaction error/ Transmit STALL Request transaction condition 2009-06-12 92CF30-430...
Page 433 TMP92CF30 (c) Device request and evaluation of various requests Start Get request data Evaluate Request Standard request Class request Vendor request Error transaction * Error for not CLEAR_FEATURE * Error for not support support SET_FEATURE GET_STATUS SET_ADDRESS SET_CONFIGURATION GET_CONFIGURATION SET_INTERFACE GET_INTERFACE SYNCH_FRAME GET_DESCRIPTOR...
Page 434 TMP92CF30 (c-1) CLEAR_FEATURE request transaction Start Is request right？ Evaluate Recipient Device Endpoint Error transaction Disable remote Clear stall setting wakeup setting Finish transaction 2009-06-12 92CF30-432...
Page 435 TMP92CF30 (c-2) SET_FEATURE request transaction Start Is request right? Evaluate Recipient Device Endpoint Error transaction Enable remote Set stall wakeup setting Finish transaction 2009-06-12 92CF30-433...
Page 436 TMP92CF30 (c-3) GET_STATUS request transaction Start Is request right? Evaluate Recipient Device Interface Endpoint Error transaction Set self power Set 0 x 0 0 data of Set stall information supply information 2 bytes Finish transaction 2009-06-12 92CF30-434...
Page 437 TMP92CF30 (c-4) SET_CONFIGRATION request transaction Start Is request right？ Is EP0 stall？ Is assignment value valid？ Is state valid？ Set assigned configuration Error transaction value Clear stall flag Finish transaction 2009-06-12 92CF30-435...
Page 438 TMP92CF30 (c-5) GET_CONFIGRATION request transaction Start Is request right? Is state valid? Set present configuraion Error transaction value Finish transaction 2009-06-12 92CF30-436...
Page 439 TMP92CF30 (c-6) SET_INTERFACE request transaction Start Is request right? Is EP0 stall? Is assigned value valid? Is state valid? Set each endpoint to Error transaction assigned configuration value. Finish transaction 2009-06-12 92CF30-437...
Page 440 TMP92CF30 (c-7) SYNCH_FRAME request transaction Start Is request right? Is EP0 stall? Is assigned value valid? Is state valid? Set alternate setting value Error transaction to present transmitting data. Finish transaction 2009-06-12 92CF30-438...
Page 441 TMP92CF30 (c-8) SYNCH_FRAME request transaction Start Is request right? Error transaction Finish transaction (c-9) SET_DESCRIPTOR request transaction Start Is request right? Error transaction Finish transaction 2009-06-12 92CF30-439...
Page 442 TMP92CF30 (c-10) GET_DESCRIPTOR request transaction Start Is request right? Is EP0 stall? Is assigneed value valid? Is state valid? Config String Device Error transaction Set device Set config Set string descriptor descriptor descriptor information. information. information. Write information to FIFO[EP0_fifowrite ( )] 2009-06-12 92CF30-440...
Page 443 TMP92CF30 (c-11) Data read transaction to FIFO by EP0 Start Is request right? Stage information = data stage Read data from FIFO STATUS_NAK interrupt disable STATUS_NAK interrupt enable Stage information = status stage Data read from FIFO All data number Finish transaction renew transfer address 2009-06-12...
Page 444 TMP92CF30 (c-12) Data write transaction to FIFO by EP0 Start Is request right? Set transmitting size to SIZE register Stage information = data stage Write data to FIFO STATUS_NAK interrupt enable Is data number a multiple of payload size? Set data size to SIZE register STATUS_ NAK interrupt disable Write data to FIFO Stage information = status stage...
Page 445 TMP92CF30 (c-13) Initial setting transaction of microcontroller Start Interrupt disable Set Stack point Set Various interrupts Clear vRAM UDC initialization[UDC_INIT] USB firmware initialization[USB_INIT] Interrupt enable Main transaction[main ( )] (c-14) Initial setting transaction of UDC Start USBC reset transaction 2009-06-12 92CF30-443...
Page 446 TMP92CF30 (c-15) Initial transaction of USB number changing firmware Start Renew stage information Renew current information Renew support information Invalid EP except EP0 Various flag Intialization (c-16) Set DEVICE_ID data to DEVICE_ID of UDC Start Set DEVICE_ID data to DEVICE_ID_RAM area. 2009-06-12 92CF30-444...
Page 447 TMP92CF30 (c-17) Descriptor data set transaction Start Set descriptor data to DESC_RAM area. (c-18) USB interrupt transaction Start Read INT register Evaluate Interrupt Setup interrupt Endpoint 0 interrupt Status_NAK interrupt Status_interrupt Others transaction [Proc_ ENDPOINT] [Proc_STATUSNAKINT] [Proc_STATUSINT] Error transaction [Proc_SETUPINT] Evaluate Request transaction [STATUS_judge] 2009-06-12...
Page 448 TMP92CF30 (c-19) Dummy function for not using maskable interrupts. • Transaction performs nothing, therefore outline flow is skipped. (c-20) Request evaluation transaction. If transaction result is error, it initiates STALL command. Start Is request right? Error transaction (c-21) SETUP stage transaction Start Is request right? Stage information = SETUP stage...
Page 449 TMP92CF30 (c-22) Perform endpoint 0 transaction except in SETUP stage. Start Evaluate Stage Data stage Status stage Others GET system request Finish normally Error transaction [EP0_fifowrite] SET system request [EP0_fiforead] (c-23) Status stage interrupt transaction Start Status stage? Normal finish transaction Error transaction 2009-06-12...
Page 450 TMP92CF30 (c-24) STATUS_NAK interrupt transaction Start Data stage? Normal finish Error transaction transaction (c-25) This transaction is a non-transaction for USB interrupts. Start 2009-06-12 92CF30-448...
Page 451 TMP92CF30 (c-26) Getting descriptor information (related to standard request) Start Get device information on descriptor Is config within support? Get config information on descriptor Interface is within support in config present. Get device information on descriptor Increment count to next config information 2009-06-12 92CF30-449...
Page 452 TMP92CF30 3.16.11 Notice and Restrictions 1. When using the USB device controller in the TMP92CF30, a crystal oscillator is recommended (USB standard ≤ 10 MHz±2500ppm). In this case, a maximum of 3 stages of external hub can be due to the precision of this USB device controller and the internal clock.
Page 453 TMP92CF30 3.17 SPI Controller (SPIC) The SPIC is a Serial Peripheral Interface Controller that supports only master mode. It can be connected to the SD card, MMC (Multi Media Card) etc. in SPI mode. Its features are summarized as follows: 1) On-chip 32-byte FIFOs for both transmission and reception 2) Generates the CRC-7 and CRC-16 values for transmission and reception 3) Baud Rate: 20 Mbps (max)
Page 454 TMP92CF30 3.17.1 Block Diagram Figure 3.17.1 shows a block diagram of the SPIC and its connections with a SD card. SPIC (SPI Controller) SD Card 100kΩ SPCLK Baud Rate SCLK Generator 16 bits 100kΩ SPCS 16 bits 100kΩ SPDO 16 bits 100kΩ...
Page 455: Special Function Registers (Sfrs)
TMP92CF30 3.17.2 Special Function Registers (SFRs) This section describes the SFRs of the SPIC. These are connected to the CPU with 16 bit data buses. (1) SPIMD (SPI Mode Select register) The SPIMD register specifies the operating mode, clock operation, etc. SPIMD Register SPIMD Bit Symbol...
Page 456 TMP92CF30 (b) MSB1ST This bit specifies whether to transmit/receive byte with the MSB first or with the LSB first. Data transmission or reception must not be performed while changing the state of this bit. (c) DOSTAT This bit specifies the status of the SPDO pin of when data transmission is not performed (i.e., after completing data transmission or during data reception).
Page 457 TMP92CF30 (h) SWRST This bit is used to performs a software reset of the read and write pointers for data transmission and reception. Stop the data transmission after writing a “0” to the SPICT<TXE> bit where XEN = “1”. Then, write a “1” to the SWRST bit to initialize the read and write pointers of transmit and receive FIFO buffers.
Page 458 TMP92CF30 (2) SPI Control Register (SPICT) The SPICT register specifies data length, CRC, etc. SPICT Register SPICT Bit Symbol SPCS_B UNIT16 TXMOD FDPXE RXMOD (0822H) Read/Write Reset State Function Communicati- SPCS Data Length Transmit Transmission Alignment Receive Receive Select Mode Select Enable Enable in Mode Select...
Page 459 TMP92CF30 This section describes how to calculate the CRC16 of the transmit data and to append the calculated CRC value at the end of the transmit data. Figure 3.17.7 below illustrates the flow chart of the CRC calculation procedures. (1) Program the SPICT<CRC16_7_B> bit to select the CRC algorithm from CRC7 and CRC16.
Page 460 TMP92CF30 (d) CEN This bit enables or disables the pins for the SD card and MMC connections. When the card is not inserted or when it is not powered on, a shoot through current might flow in the SPDI pin, for it enters the floating state. Also, currents may unintentionally flow into the card from the SPCS , SPCLK and SPDO pins when they generate a logic 1.
Page 461 TMP92CF30 Important Note: When in UNIT mode (TXMOD = “0”), the following restriction is imposed on the system operation. When the SPICT<TEX> bit is set to “1”, the state of any bits must not be changed until the data transmission is completed. Sample Program 1: (SPITDx), A ;...
Page 462 TMP92CF30 (k) RXE In the UNIT–mode reception, writing a “1” to this bit enables the reception of only one UNIT-size data. When reading the receive data register (SPIRD) while this bit is kept enabled, one more UNIT data is additionally received. In Sequential mode, writing a “1”...
Page 463: Important Note
TMP92CF30 Differences Between the UNIT-mode and Sequential-mode transmissions The UNIT mode for the data transmission can be selected by writing a “0” to the SPICT<TXMOD> bit. The transmit FIFO buffer is disabled in UNIT mode. The UNIT-mode transmission starts when the UNIT-size data is loaded into the SPITD register where SPICT<TXE> = “1”, or when the SPICT<TXE>...
Page 464 TMP92CF30 The state of the SPICT<TXE> bit can be changed even during the data transmission. Writing a “0” to the SPICT<TXE> bit during a transmission stops the transmission after completing the transmission of the UNIT data currently being transmitted. The TEMP interrupt is generated when the empty space size of the FIFO becomes 16 or 32 bytes.
Page 465 TMP92CF30 Differences Between the UNIT-mode and Sequential-mode Receptions The UNIT-mode reception receives only one UNIT-size data. The UNIT mode for the data reception can be selected by writing a “0” to the SPICT<RXMOD> bit. The receive FIFO is disabled in UNIT mode. Writing a “1” to the SPICT<RXE> bit initiates a receive operation of one UNIT data.
Page 466 TMP92CF30 Transmit and Receive Operation When performing a data transmission and reception simultaneously, the FDPXE bit must be set to “1”. Write a “1” to the SPICT<RXE> bit after writing a “1” to the FDPXE bit to put the receiver into standby mode for the UNIT-mode reception. Writing a “1” to the SPICT<RXE> bit after writing a “1”...
Page 467 TMP92CF30 (3) Interrupts The SPIC generates two types of interrupt requests to the Interrupt Controller (INTC), which are the transmit interrupt (INTSPITX) and receive interrupt (INTSPIRX) requests. Also, the SPIC has four types of interrupts; two for transmission and two for reception. (a) Transmit interrupts TEMP (Transmit FIFO Empty interrupt) and TEND (Transmit End interrupt) As for the TEMP interrupt, the timing of the interrupt generation differs depending on...
Page 468 TMP92CF30 (3-1) SPI Status Register (SPIST) The SPIST register contains three bits that indicates the status of data communication. SPIST Register SPIST Bit Symbol TEMP TEND REND (0824H) Read/Write Reset State Function Transmit Transmission Reception FIFO Status Status Status 0: Reception 0: No empty Transmission in progress...
Page 469 TMP92CF30 (3-2) SPI Interrupt Enable Register (SPIE) The SPIIE register enables or disables the generation of four types of interrupts. SPIIE Register SPIIE Bit Symbol TEMPIE RFULIE TENDIE RENDIE (082CH) Read/Write Reset State Function TEMP RFUL TEND REND interrupt interrupt interrupt interrupt 0:Disable...
Page 470 TMP92CF30 (4) SPI CRC Register (SPICR) The SPICR register contains the CRC calculation result for transmit/receive data. SPICR Register SPICR Bit Symbol CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0 (0826H) Read/Write Reset State Function CRC result bits [7:0] (0827H) Bit Symbol CRCD15 CRCD14...
Page 471 TMP92CF30 (5) SPI Transmit Data Register (SPITD) The SPITD0 and SPITD1 registers are used for writing the transmit data. SPITD0 Register SPITD0 Bit Symbol TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0 (0830H) Read/Write Reset State Function Transmit data bits [7:0] (0831H) Bit Symbol TXD15...
Page 472 TMP92CF30 (6) SPI Receive Data Register (SPIRD) The SPIRD0 and SPIRD1 registers are used for reading the received data. SPIRD0 Register SPIRD0 Bit Symbol RXD7 RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 (0834H) Read/Write Reset State Function Receive data bits [7:0] (0835H) Bit Symbol RXD15...
Page 473 TMP92CF30 3.17.3 Notes on the Operations Using the FIFO Buffers Things to be noted when using the SPIC are as follows: 1) Transmission The transmit FIFO buffer is overwritten if the new data is written with the transmit FIFO buffer being full. Also, since the FIFO write pointer does not point to the correct write position, interrupts and transmissions are not properly executed.
Page 474: Operation Features
TMP92CF30 3.18 I S (Inter-IC Sound) The TMP92CF30 incorporates serial output circuitry that is compliant with the I S format. This function enables the TMP92CF30 to be used for digital audio systems by connecting an LSI for audio output such as a DA converter. The I S unit has the following features: Table 3.18.1 I...
Page 475: Block Diagram
TMP92CF30 3.18.1 Block Diagram I2S0CTL I2S0CTL <EDGE0> <CLKS0> I2SCKO Counter I2SCKO 8-bit I2S0CKO Invert Stop Stop Counter I2S0CTL I2S0CTL <CNTE0> <TXE0,CLKE0> I2SWS 6-bit I2S0WS Control Counter I2S0C <CK07:00> I2S0C I2S0CTL <WS05:00> <TXE0> Clock Generator INTI2S0 Data Selector 32bit I2S0DO Interrupt 64-byte FIFO0 64-byte FIFO1 Control...
Page 476 TMP92CF30 3.18.2 SFRs The I S unit is provided with the following registers. These registers are connected to the CPU via a 32-bit data bus. The transmission buffers I2S0BUF must be accessed using 4-byte load instructions. S0 Control Register I2S0CTL bit Symbol TXE0 *CNTE0...
Page 477 TMP92CF30 (a) <SYSCKE0> This bit controls to connect source clock to I S circuit. In case of this circuit is operated, it must enable: <SYSCKE0>= “1”. And except operating, for reduce the power consumption, we recommends to disable: <SYSCKE0>= “0”. (b) <DTFMT01:00>...
Page 478 TMP92CF30 (h) <EDGE0> This bit controls relation of phase between I2S0CKO and data. <EDGE0>=“0”: the data is changed in the falling of clock, and the data is latched in the rising edge of clock. <EDGE0>=“1”: the data is changed in the rising of clock, and the data is latched the falling edge of clock.
Page 479 TMP92CF30 3.18.3 Description of Operation (1) Settings the transfer clock generator and Word Select signal In the I S unit, the clock frequencies for the I2S0CKO and I2S0WS signals are generated using the system clock (f ) as a source clock. The system clock is divided by a prescaler and a dedicated clock generator to set the transfer clock and sampling frequency.
Page 480 TMP92CF30 Left Data Right Data I2S0WS I2S0CKO S format I2S0DO Stereo Valid data Valid Data Monaural Valid Data Left justify I2S0DO Stereo Valid Data Valid Data Monaural Valid Data Right justify I2S0DO Stereo Valid Data Valid Data Monaural Valid Data Note: When Monaural is set, Right data and Left data output the same-signal.
Page 481 TMP92CF30 (3) Setting example for the clock generator (8-bit counter/6-bit counter) The clock generator generates the reference clock for setting the data transfer speed and sampling frequency. I2S0C bit Symbol CK07 CK06 CK05 CK04 CK03 CK02 CK01 CK00 (180AH) Read/Write Reset State Function Divider value for CK signal (8-bit counter)
Page 482 TMP92CF30 • Setting the sampling frequency WS The sampling frequency is set by dividing the transfer clock (CK) described above. A 6-bit counter is provided to divide the transfer clock by 16 to 64. (The divider value cannot be set to 1 to 15.) 6-bit counter set value Divider value 000000...
Page 483 TMP92CF30 (4) FIFO buffer and data format S unit is provided with a 128-byte FIFO buffer (32-bit wide × 32-entry). The The I data written to the 4 bytes (32 bits) of the I2S0BUF register is written to this FIFO buffer.
Page 484 TMP92CF30 The following shows how written data is output under various conditions. When I2S0CTL<WLVL0> = “0” I2S0BUF register Output order MSB-first 16 bits 2’nd Data 2’nd Data LSB-first 16 bits MSB-first 8 bits 4’th Data 3’rd Data 4’th Data 3’rd Data LSB-first 8 bits MSB-first 16 bits 1’st Data...
Page 485 TMP92CF30 3.18.4 Detailed Description of Operation (1) Connection example Figure3.18.4 shows an example of connections between the TMP92CF30 and an external LSI (DA converter) using channel 0. TMP92CF30 (Transmit) (Receive) PF2/I2S0WS PF0/I2SCKO PF1/I2SDO DATA Example: DA converter Note: After reset, PF0 to PF2 are placed in a high-impedance state. Connect each pin with a pull-up or pull-down resistor as necessary.
Page 486 TMP92CF30 FIFO write <TXE> I2S0WS pin I2S0CKO pin I2S0DO pin INTI2S0 Overall Timing Diagram I2S0WS pin 400kHz I2S0CKO pin I2S0DO pin LSB MSB Bit15 Bit14 Bit0 Bit15 Bit14 Bit15 Bit0 Detailed Timing Diagram Figure3.18.5 Timing Diagrams (I S FMT/Stereo/16bit/MSB first) 2009-06-12 92CF30-484...
Page 487 TMP92CF30 (3) Considerations for using the I S unit 1) INTI2S0 generation timing Every 4bytes data trance from FIFO buffer to shift register per one time. An INTI2S0 interrupt is generated under two conditions. One is when there are 64 bytes of empty space in the FIFO (after 61- 64th byte has been transferred to the shift register).
Page 488 TMP92CF30 4) FIFO buffer The I S unit is provided with a 128-byte FIFO. Although it is not necessary to use all 128 bytes in the FIFO, data should basically be written in units of 64 bytes using an INTI2S0 interrupt as a trigger. If data is written to the FIFO without waiting for an INTI2S0 interrupt or in units other than 64 bytes, interrupts cannot be generated properly.
Page 489 TMP92CF30 3.19 Touch Screen Interface (TSI) An interface for 4-terminal resistor network touch-screen is built in. The TSI easily supports two procedures: touch detection and X/Y position measurement. Each procedure is performed by setting the TSI control register (TSICR0 and TSICR1) and using an internal AD converter.
Page 490 TMP92CF30 3.19.2 Touch Screen Interface (TSI) Control Register TSI control register TSICR0 bit Symbol TSI7 INGE PTST TWIEN PYEN PXEN MYEN MXEN (01F0H) Read/Write Reset State Function 0: Disable Input gate Detection INT4 1: Enable control of condition interrupt 0 : OFF 0 : OFF 0 : OFF 0 : OFF...
Page 491 TMP92CF30 3.19.3 Touch detection procedure The touch detection procedure includes the procedure starting from when the pen is touched onto the touch screen and until the pen-touch is detected. Touching the screen generates the interrupt (INT4) and terminates this procedure. After an X/Y position measuring procedure is terminated, return to this procedure to wait for the next touch.
Page 492 TMP92CF30 P96/INT4 pin Reset the debounce time counter Start the debounce time counter Debounce time Debounce time Debounce time INT4 The debounce time counter matches with a After the pen is released, an INT4 interrupt can specified debounce time, which generates an be received again.
Page 493 TMP92CF30 3.19.4 X/Y position measuring procedure During the routine of pen-touch and INT4 interrupt generation, execute a pen position measuring following the procedure below: <X position coordinate measurement> Make the SPX and SMX switches ON, and the SPY and SMY switches OFF. With this setting, an analog-voltage that shows the X position will be input to the PG3/MY/AN3 pin.
Page 494 TMP92CF30 3.19.5 Flow chart for TSI (2) X/Y Position (1) Touch Detection Procedure Measuring Procedure Main Routine: INT4 Routine: TSICR0←98H TSICR1←XXH (voluntary) <X position measurement> ･TSICR0←C5H ･AN3 AD conversion ･Store the AD conversion result Execute the Main Routine <Y position measurement> ･TSICR0←CAH ･AN2 AD conversion ･Store the AD conversion result...
Page 495 TMP92CF30 (a) Main routine (condition of waiting INT4 interrupt) (p9fc)<P96F>, <P97F>= “1” Set P96 to int4/PX, set P97 to PY (inte34) Set interrupt level of INT4 (tsicr0)=98h Pull-down resistor on, SPY on, Interrupt-set<TWIEN> Enable interrupt TMP92CF30 Touch screen control AVCC PXEN PYEN Dec.
Page 496 TMP92CF30 (b) INT4 routine: X-position coordinate measurement (AD conversion start) (tsicr0)=c5h Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF. (admod1)=b0h Set to AN3. (admod0)=08h Start AD conversion. TMP92CF30 Touch screen control AVCC PXEN PYEN Dec.
Page 497 TMP92CF30 (c) INT4 routine: Y-position coordinate measurement (AD conversion start) (tsicr0)=cah Set SMX, SPX to ON. Set the input gate of P97, P96 to OFF. (admod1)=a0h Set to AN2. (admod0)=08h Start AD conversion. TMP92CF30 Touch screen control AVCC PXEN PYEN Dec.
Page 498 TMP92CF30 3.19.6 Use Cautions 1. Debounce circuit The CPU system clock is used in debounce circuit. Therefore, when no clock is supplied to the CPU (during IDLE1 and STOP modes), the debounce circuit does not operate. Because of this, interrupts bypassing the debounce circuit are not generated either.
Page 499: Real Time Clock (Rtc)
TMP92CF30 3.20 Real time clock (RTC) 3.20.1 Function description for RTC 1) Clock function (hour, minute, second) 2) Calendar function (month and day, day of the week, and leap year) 3) 24 or 12-hour (AM/PM) clock function 4) +/- 30 second adjustment function (by software) 5) Alarm function (Alarm output) 6) Alarm interrupt generate 3.20.2...
Page 500: Control Registers
TMP92CF30 3.20.3 Control registers Table 3.20.1 PAGE 0 (Clock function) registers Symbol Address Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Function Read/Write SECR 1320H 40 sec 20 sec 10 sec 8 sec 4 sec 2 sec 1 sec Second column MINR 1321H 40 min...
Page 501 TMP92CF30 3.20.4 Detailed explanation of control register RTC is not initialized by system reset. Therefore, all registers must be initialized at the beginning of the program. (1) Second column register (for PAGE0 only) SECR Bit symbol (1320H) Read/Write Undefined Reset State Function "0"...
Page 502 TMP92CF30 (2) Minute column register (for PAGE0/1) MINR Bit symbol (1321H) Read/Write Undefined Reset State Function "0" is read. 40 min, 20 min, 10 min, 8 min, 4 min, 2 min, 1 min, column column column column column column column 0 min 1 min 2 min...
Page 503 TMP92CF30 (3) Hour column register (for PAGE0/1) 1. In case of 24-hour clock mode (MONTHR<MO0>= “1”) HOURR Bit symbol (1322H) Read/Write Undefined Reset State "0" is read. 20 hour 10 hour 8 hour 4 hour 2 hour 1 hour Function column column column...
Page 504 TMP92CF30 (4) Day of the week column register (for PAGE0/1) DAYR Bit symbol (1323H) Read/Write Undefined Reset State "0" is read. Function Sunday Monday Tuesday Wednesday Thursday Friday Saturday Note: Do not set data other than as shown above. (5) Day column register (PAGE0/1) DATER Bit symbol (1324H)
Page 505 TMP92CF30 (6) Month column register (for PAGE0 only) MONTHR Bit symbol (1325H) Read/Write Undefined Reset State "0" is read. 10 months 8 months 4 months 2 months 1 month Function January February March April June July August September October November December Note: Do not set data other than as shown above.
Page 506 TMP92CF30 (8) Year column register (for PAGE0 only) YEARR Bit symbol (1326H) Read/Write Undefined Reset State Function 80 Years 40 Years 20 Years 10 Years 8 Years 4 Years 2 Years 1 Year 00 years 01 years 02 years 03 years 04 years 05 years 99 years...
Page 507 TMP92CF30 (10) PAGE register (for PAGE0/1) PAGER INTENA ADJUST ENATMR ENAALM PAGE Bit symbol (1327H) Read/Write Undefined Undefined Undefined Reset State A Read- Interrupt 0: Don’t Clock ALARM “0” is read. PAGE Function “0” is read. modify- write selection 0: Disable care 0: Disable 0: Disable...
Page 508 TMP92CF30 3.20.5 Operational description (1) Reading clock data 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can read correctly if reading data after 1Hz interrupt occurred. 2. Using two times reading There is a possibility of incorrect clock data reading when the internal counter carries over.
Page 509 TMP92CF30 (2) Writing clock data When a carry over occurs during a write operation, the data cannot be written correctly. Please use the following method to ensure data is written correctly. 1. Using 1Hz interrupt 1Hz interrupt and the count up of internal data synchronize. Therefore, data can write correctly if writing data after 1Hz interrupt occurred.
Page 510 TMP92CF30 3. Disabling the clock A clock carry over is prohibited when “0” is written to PAGER<ENATMR> in order to prevent malfunction caused by the Carry hold circuit. While the clock is prohibited, the Carry hold circuit holds a one sec. carry signal from a divider. When the clock becomes enabled, the carry signal is output to the clock, the time is revised and operation continues.
Page 511 TMP92CF30 3.20.6 Explanation of the interrupt signal and alarm signal The alarm function used by setting the PAGE1 register and outputting either of the following three signals from pin by writing “1” to PAGER<PAGE>. INTRTC ALARM outputs a 1-shot pulse when the falling edge is detected. RTC is not initialized by RESET. Therefore, when the clock or alarm function is used, clear interrupt request flag in INTC (interrupt controller).
Page 512 TMP92CF30 (2) With 1Hz output clock RTC outputs a clock of 1Hz to pin by setting up PAGER<ENAALM>= “0”, ALARM RESTR<DIS1HZ>= “0”, <DIS16HZ>= “1”. RTC also generates an INTRTC interrupt on the falling edge of the clock. (3) With 16Hz output clock RTC outputs a clock of 16Hz to pin by setting up PAGER<ENAALM>= “0”, ALARM...
Page 513 TMP92CF30 3.21 Melody / Alarm generator (MLD) The TMP92CF30 contains a melody function and alarm function, both of which are output from the MLDALM pin. Five kind of fixed cycle interrupt are generated by using a 15bit counter for use as the alarm generator. The features are as follows.
Page 514 TMP92CF30 3.21.1 Block Diagram Reset [Melody Generator] Internal data bus MELFH, MELFL register MELOUT MELFH Invert <MELON> Comparator (CP0) Stop and Clear Clear Low-speed 12bit counter (UC0) clock INTALM0 (8192Hz) INTALM1 (512 Hz) Edge INTALM2 (64 Hz) detectior INTALM INTALM3 (2 Hz) INTALM4 (1 Hz) 15bit conter (UC1) ALMINT...
Page 515 TMP92CF30 3.21.2 Control registers ALM register bit Symbol (1330H) Read/Write Reset State Setting alarm pattern Function MELALMC register − − − − ALMINV MELALM MELALMC bit Symbol (1331H) Read/Write Reset State Function Free-run counter control Alarm Always write “0” Select 00: Hold Waveform Output...
Page 516: Operational Description
TMP92CF30 3.21.3 Operational Description 3.21.3.1 Melody generator The Melody function generates signals of any frequency (4Hz-5461Hz) based on a low-speed clock (32.768kHz) and outputs the signals from the MLDALM pin. The melody tone can easily be heard by connecting an external loud speaker. (Operation) MELALMC<MELALM>...
Page 517 TMP92CF30 3.21.3.2 Alarm generator The Alarm function generates eight kinds of alarm waveform having a modulation frequency of 4096Hz determined by the low-speed clock (32.768 kHz). This waveform is reversible by setting a value to a register. The alarm tone can easily be heard by connecting an external loud speaker. Five kind of fixed cycle (interrupts can be generated 1Hz, 2Hz, 64Hz, 512Hz, 8192Hz) by using a counter which is used for the alarm generator.
Page 518 TMP92CF30 Example: Waveform of alarm pattern for each setting value: not inverted) AL1 pattern Modulation frequency (4096 Hz) (Continuous output) AL2 pattern (8 times/1 sec) 31.25 ms 1 sec AL3 pattern (once) 500 ms AL4 pattern (Twice/1 sec) 62.5 ms 1 sec AL5 pattern (3 times/1 sec)
Page 519: Analog-Digital Converter (Adc)
TMP92CF30 3.22 Analog-Digital Converter (ADC) A 10-bit serial conversion analog/digital converter (AD converter) having six channels of analog input is built in. Figure 3.22.1 shows the block diagram of the AD converter. The 6-analog input channels (AN0-AN5) can be used as general-purpose inputs. Note1: To reduce the power supply current by IDLE2, IDLE1 and STOP mode, the standby state may be maintained with the internal comparator still being enabled, depending on the timing.
Page 520: Control Register
TMP92CF30 3.22.1 Control register The AD converter is controlled by the AD mode control registers (ADMOD0, ADMOD1, ADMOD2, ADMOD3, ADMOD4 and ADMOD5). AD conversion results are stored in the six registers of AD conversion result higher-order/lower-order registers ADREG0H/L to ADREG5H/L. Top-priority conversion results are stored in ADREGSPH/L. Figure 3.22.2 to Figure 3.22.11 show the registers available in the AD converter.
Page 521 TMP92CF30 AD Mode Control Register 1 (Normal conversion control) DACON ADCH2 ADCH1 ADCH0 REPEAT SCAN ADMOD1 bit Symbol (12B9H) Read/Write Reset State DAC and Analog input channel select Latency Interrupt Repeat Scan mode Function VREF 0: No Wait specification mode specification application 1:Start after...
Page 522 TMP92CF30 AD Mode Control Register 2 (Top-priority conversion control) HEOS HBUSY HADS HTSEL1 HTSEL0 ADMOD2 bit Symbol HHTRGE (12BAH) Read/Write Reset State Top-priority Top-priority Start Top-priority Select Hard ware trigger Function Top-priority 00: INTTB10 interrupt conversion conversion conversion 01: Reserved sequence BUSY Flag conversion...
Page 523 TMP92CF30 AD Mode Control Register 4 (AD Monitor function control) CMEN1 CMEN0 CMP1C CMP0C IRQEN1 IRQEN0 ADMOD4 bit Symbol CMPINT1 CMPINT0 (12BCH) Read/Write Reset State AD Monitor AD Monitor Generation Generation AD monitor AD monitor Status of Status of Function function1 function0 condition of...
Page 524 TMP92CF30 AD Conversion Result Register 0 Low ADREG0L bit Symbol ADR01 ADR00 OVR0 ADR0RF (12A0H) Read/Write Reset State Overrun Function Store Lower 2 bits of flag conversion AN0 AD conversion 0:No result store result generate flag 1: Generate 1: Stored AD Conversion Result Register 0 High ADREG0H bit Symbol...
Page 525 TMP92CF30 AD Conversion Result Register 2 Low ADREG2L bit Symbol ADR21 ADR20 OVR2 ADR2RF (12A4H) Read/Write Reset State Overrun Function Store Lower 2 bits of flag conversion AN2 AD conversion 0:No result store result generate flag 1: Generate 1: Stored AD Conversion Result Register 1 High ADREG2H bit Symbol...
Page 526 TMP92CF30 AD Conversion Result Register 4 Low ADREG4L bit Symbol ADR41 ADR40 OVR4 ADR4RF (12A8H) Read/Write Reset State Overrun Function Store Lower 2 bits of flag conversion AN4 AD conversion 0:No result store result generate flag 1: Generate 1: Stored AD Conversion Result Register 4 High ADREG4H bit Symbol...
Page 527 TMP92CF30 Top-priority AD Conversion Result Register SP Low ADREGSPL bit Symbol ADRSP1 ADRSP0 OVSRP ADRSPRF (12B0H) Read/Write Reset State Overrun Function Store Lower 2 bits of an flag conversion AD conversion result 0:No result store generate flag 1: Generate 1: Stored Top-priority AD Conversion Result Register SP High ADREGSPH bit Symbol...
Page 528 TMP92CF30 AD Conversion Result Compare Criterion Register 0 Low ADCM0REGL bit Symbol ADR21 ADR20 (12B4H) Read/Write Reset State Function Store Lower 2 bits of an AD conversion result compare criterion AD Conversion Result Compare Criterion Register 0 High ADCM0REGH bit Symbol ADR29 ADR28 ADR27...
Page 529 TMP92CF30 AD Conversion Clock Setting Register − ADCCLK bit Symbol ADCLK2 ADCLK1 ADCLK0 (12BFH) Read/Write Reset State Always Select clock for AD conversion Function write “0” 000: Reserved 100: f 001: f 101: f 010: f 110: f 011: f 111: f Note1: AD conversion is executed at the clock frequency selected in the above register.
Page 530 TMP92CF30 3.22.2 Operation 3.22.2.1 Analog Reference Voltages Apply the analog reference voltage's “H” level side to the VREFH pin and the “L” level side to the VREFL pin. 3.22.2.2 Selecting Analog Input Channels Selecting an analog input channel depends on the operation mode of the AC converter.
Page 531 TMP92CF30 3.22.2.3 Starting an AD Conversion The AD conversion has the two types of normal AD conversion and top-priority AD conversion. Normal AD conversion can be started up by setting ADMOD0<ADS> to “1.” Top-priority conversion started software setting ADMOD2<HADS> to “1.” For normal AD conversion, one operation mode is selected from the four types of operation modes specified by ADMOD1<REPEAT, SCAN>.
Page 532 TMP92CF30 <HEOS> and <EOS> are set to “1” after conversion is completed. This flag is cleared to “0” only when read. During a normal AD conversion, writing a “1” to ADMOD0<ADS> causes the ADC to abort any ongoing conversion immediately, and restart. During a normal AD conversion, if normal AD conversion starting is enabled by hard ware trigger, normal AD conversion is restarted when start condition from hard ware trigger is satisfied.
Page 533 TMP92CF30 3.22.2.4 AD Conversion Modes and AD Conversion-End Interrupts For AD conversion, the following four operation modes are provided: For normal AD conversion, selection is available by setting ADMOD1<REPEAT and SCAN>. As for top-priority AD conversion, only single conversion mode by channel-fix mode is available.
Page 534 TMP92CF30 d. Channel-scan repeat conversion mode Setting ADMOD1<REPEAT, SCAN> to “11” selects the channel-scan repeat conversion mode. This mode performs a conversion at selected scan channels repeatedly. Each time after the conversion at a final channel ends, ADMOD0<EOS> is set to “1,” generating Normal AD conversion End interrupt request.
Page 535 TMP92CF30 3.22.2.5 Top-Priority Conversion Mode The ADC can perform a Top-priority AD conversion while it is performing a normal AD conversion sequence. A Top-priority AD conversion can be started at software by setting the ADMOD2<HADS> to “1”. It is also triggered by a hardware trigger if so enabled using ADMOD2<HTSEL1:0>.
Page 536 TMP92CF30 3.22.2.8 Storing and Read of AD Conversion Results conversion results stored conversion result higher-order/lower-order registers (ADREG0H/L∼ ADRG5H/L) for the normal AD conversion (ADREG0H/L to ADREG5H/L are read-only registers) In the channel-fix repeat conversion mode, AD conversion results are stored into ADREG0H/L to ADREG3H/L one after another.
Page 537 TMP92CF30 Setting example: Convert the analog input voltage on the AN3 pin and write the result to memory address 2800H using the AD interrupt(INTAD) processing routine. Main routine ← 1 − − − − INTEAD Enable INTAD and set it to interrupt level 4. ←...
Page 538 TMP92CF30 3.23 Watchdog Timer (Runaway detection timer) The TMP92CF30 contains a watchdog timer of runaway detecting. The watchdog timer (WDT) is used to return the CPU to the normal state when it detects that the CPU has started to malfunction (runaway) due to causes such as noise. When the watchdog timer detects a malfunction, it generates a non-maskable interrupt INTWD to notify the CPU of the malfunction.
Page 539 TMP92CF30 3.23.2 Operation The watchdog timer generates an INTWD interrupt when the detection time set in the WDMOD<WDTP1:0> has elapsed. The watchdog timer must be cleared “0” in software before an INTWD interrupt will be generated. If the CPU malfunctions (e.g., if runaway occurs) due to causes such as noise, but does not execute the instruction used to clear the binary counter, the binary counter will overflow and an INTWD interrupt will be generated.
Page 540 TMP92CF30 3.23.3 Control Registers The watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR. (1) Watchdog timer mode registers (WDMOD) Setting the detection time for the watchdog timer in <WDTP1:0> This 2-bit register is used for setting the watchdog timer interrupt time used when detecting runaway.
Page 541 TMP92CF30 − WDMOD Bit symbol WDTE WDTP1 WDTP0 I2WDT RESCR (1300H) Read/Write Reset State Function WDT control Select detecting time IDLE2 1: Internally Always connects write “0” 1: Enable 00: 2 0: Stop WDT out to 01: 2 1: Operate the reset 10: 2 11: 2...
Page 542 TMP92CF30 3.24 Multiply and Accumulate Calculation Unit (MAC) The TMP92CF30 includes a multiply-accumulate unit (MAC) capable of 32-bit × 32-bit + 64-bit arithmetic operations at high speed. The MAC has the following features: ・ One-cycle execution for all MAC operations (excluding register access time) ・...
Page 543: Data Registers
TMP92CF30 3.24.1.2 Data Registers The data registers are arranged as shown below. Data Registers Bits<63:56> Bits<55:48> Bits<47:40> Bits<39:32> Bits<31:24> Bits<23:16> Bits<15:8> Bits<7:0> Multiplier A MACMA Register (1BE3H) (1BE2H) (1BE1H) (1BE0H) Multiplier B MACMB Register (1BE7H) (1BE6H) (1BE5H) (1BE4H) MACORH MACORL Register (1BEFH) (1BEEH)
Page 544 TMP92CF30 3.24.2 Description of Operation (1) Calculation mode The MAC has the following three types of calculation mode. The calculation mode to be used is specified in MACCR<MOPMD1:0>. MACCR<MSGMD> is used to select unsigned or signed mode. The operation of each calculation mode is explained below. (a) 64 + 32 ×...
Page 545 TMP92CF30 (d) Sign mode Both multiply-accumulate and multiply-subtract operations can be executed in unsigned or signed mode. In signed mode, the MACMA, MACMB, and MACOR registers become signed registers, and the most significant bit is treated as the sign bit and the data set in each register is treated as a two’s complement value.
Page 546: Operation Examples
TMP92CF30 3.24.3 Operation Examples (1) Unsigned multiply-accumulate operation The following shows a setting example for calculating “33333333 + 11111111 × 22222222”: (MACCR), 0x08 ; Unsigned multiply-accumulate mode Start calculation by write to MACMB. xde, 0x00000000 xhl, 0x33333333 xix, 0x11111111 xiy, 0x22222222 (MACORL), xhl ;...
Page 547: Electrical Characteristics
TMP92CF30 Electrical Characteristics Absolute Maximum Ratings Symbol Contents Rating Unit DVCC3A -0.3 to 3.9 DVCC1A Power Supply Voltage DVCC1B -0.3 to 3.0 DVCC1C AVCC -0.3 to 3.9 -0.3 to DVCC3A+0.3 (Note1) Input Voltage -0.3 to AVCC+0.3 (Note 2) Output Current (1pin) Output Current (1pin) Σ...
Page 548: Dc Electrical Characteristics
TMP92CF30 4.2 DC Electrical Characteristics Symbol Parameter Typ. Unit Condition General I/O Power Supply Voltage DVCC3A (DVCC=AVCC) (DVSSCOM=AVSS=0V) X1=6 to 10MHz CPU CLK XT1=30 to 34kHz DVCC1A Internal Power A (80MHz) DVCC1B Internal Power B DVCC1C High CLK oscillator and PLL Power Input Low Voltage for D0 to D7 P10 to P17 (D8 to 15), P60 to P67...
Page 549 TMP92CF30 Symbol Parameter Typ. Unit Condition Input High Voltage for D0 to D7 P10 to P17 (D8 to 15), P60 to P67 P71 to P76, P90 0.7 × DVCC3A − 3.0 ≤ DVCC3A ≤ 3.6 PC4 to PC7, PF0 to PF5 DVCC3A + 0.3 PG0 to PG5, PJ5 to PJ6 PN0 to PN7, PP1 to PP2...
Page 550 TMP92CF30 Symbol Parameter Typ. Unit Condition Output Low Voltage1 P90 to P92, PC0 to PC3, PC7 = 0.5mA, 3.0 ≤ DVCC3A PF0 to PF5, PK1 to PK7 − − PM1 to PM2, PM7 PN0 to PN7, PP3 to PP6 PV6 to PV7, PX5 Output Low Voltage2 = 2mA, 3.0 ≤...
Page 551 TMP92CF30 Symbol Parameter Typ. Unit Condition − DVCC3A= 3.6V NORMAL (note2) PLL_ON DVCC1A,1B,1C = 1.6V = 80MHz − DVCC3A = 3.6V IDLE2 DVCC1A,1B,1C = 1.6V − DVCC3A = 3.6V NORMAL (note2) PLL_ON DVCC1A,1B,1C = 1.6V = 60MHz − DVCC3A = 3.6V IDLE2 DVCC1A,1B,1C = 1.6V −...
Page 552 TMP92CF30 AC Characteristics The Following all AC regulation is the measurement result in following condition, if unless otherwise noted. AC measuring condition Clock of top column in above table shows system clock frequency, and “T” shows • system clock period [ns]. Output level: High = 0.7 ×...
Page 553 TMP92CF30 Write cycle Variable Parameter Symbol 80MHz 60MHz Unit D0 to D31 valid 1.0T − 6.0 16-1 10.6 → xx rising at 0 waits 3.0T − 6.0 D0 to D31 valid 31.5 43.8 16-2 → 5.0T − 6.0 xx rising at 2 waits/4 waits 56.5 77.0 1.0T −...
Page 554 TMP92CF30 (1) Read cycle (0 waits) SDCLK WAIT A0 to A23 D0 to D31 Data input SRxxB SRWR Note1: The phase relation between X1 input signal and the other signals is undefined. Note2: The above timing chart show an example of basic bus timing. The , R/ W , WRxx SRxxB...
Page 555 TMP92CF30 (2) Write cycle (0 waits) SDCLK WAIT A0 to A23 WRxx D0 to D31 Data output SRxxB SRWR Note1: The phase relation between X1 input signal and the other signals is undefined. Note2: The above timing chart show an example of basic bus timing. The , R/ W , WRxx SRxxB...
Page 556 TMP92CF30 (3) Read cycle (1 wait) SDCLK WAIT A0 to A23 D0 to D31 Data input (4) Write cycle (1 wait) SDCLK WAIT A0 to A23 WRxx D0 to D31 Data output 2009-06-12 92CF30-554...
Page 557 TMP92CF30 4.3.2 Page ROM Read Cycle (1) 3-2-2-2 mode Variable Parameter Symbol 80 MHz 60 MHz Unit 1 System clock period ( = T) 12.5 2666 12.5 16.6 2.0T − 18 2 A0, A1 → D0 to D31 input 15.2 3.0T −...
Page 558 TMP92CF30 4.3.3 SDRAM controller AC Characteristics Variable Parameter Symbol 80 MHz 60 MHz Unit <STRC[2:0]>= “000” Ref/Active to ref/active 12.5 16.6 command period <STRC[2:0]>= “110” 87.5 116.2 Active to precharge <STRC[2:0]>= “000” 2T (Note1) 25.0 33.2 command period <STRC[2:0]>= “110” 87.5 116.2 Active to read/write...
Page 559 TMP92CF30 (1) SDRAM read timing (1Word length read mode, <SPRE>= “1”) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A0 to A9 Column A11 to A15 D0 to D15 Data input 2009-06-12 92CF30-557...
Page 560 TMP92CF30 (2) SDRAM write timing (Single write mode, <SPRE>= “1”) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A0 to A9 Column A11 to A15 D0 to D15 Data output 2009-06-12 92CF30-558...
Page 561 TMP92CF30 (3) SDRAM burst read timing (Start burst cycle) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE Column A0 to A9 A11 to A15 Data D0 to D15 Data input Data input input 2009-06-12 92CF30-559...
Page 562 TMP92CF30 (4) SDRAM burst read timing (End burst timing) SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A0 to A9 Column A11 to A15 D0 to D15 Data input Data input 2009-06-12 92CF30-560...
Page 563 TMP92CF30 (5) SDRAM initializes timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE A0 to A9 A11 to A15 2009-06-12 92CF30-561...
Page 564 TMP92CF30 (6) SDRAM refreshes timing SDCLK SDxxDQM SDCS SDRAS SDCAS SDWE (7) SDRAM self refresh timing SDCLK SDCKE SDxxDQM SDCS SDRAS SDCAS SDWE 2009-06-12 92CF30-562...
Page 565 TMP92CF30 4.3.4 NAND Flash Controller AC Characteristics Variable 80 MHz 60 MHz No. Symbol Parameter Unit (n=3) (n=3) (m=3) (m=3) Access cycle (2 + n + m)T (1.5 + n)T − 12 low level width NDRE (1.5 + n) T − 15 data access time NDRE Read data hold time...
Page 566 TMP92CF30 4.3.5 Serial channel timing (1) SCLK input mode (I/O interface mode) Variable Parameter Symbol 80 MHz 60 MHz Unit SCLK cycle /2 − 4T − 30 Output data → SCLK rising/ falling 36.4 SCLK rising/ falling → Output data hold /2 + 2T −...
Page 567: Interrupt Operation
TMP92CF30 4.3.6 Timer input pulse (TA0IN,TA2IN,TB0IN0,TB1IN0) Variable Parameter Symbol 80 MHz 60 MHz Unit Clock cycle 8T+100 4T + 40 Low level pulse width VCKL 4T + 40 High level pulse width VCKH 4.3.7 Interrupt operation Variable Parameter Symbol 80 MHz 60 MHz Unit 2T + 40 INT0~INT7 low width INTAL...
Page 568 TMP92CF30 4.3.9 S Timing Variable Parameter Symbol 80 MHz 60 MHz Unit I2SCKO clock period − 15 0.5 t I2SCKO high width − 15 0.5 t I2SCKO low width − 15 0.5 t I2SDO, I2SWS setup time − 8 0.5 t I2SDO, I2SWS hold time I2SCKO I2SDO...
Page 569: Spi Controller
TMP92CF30 4.3.10 SPI Controller Variable Parameter Symbol 80 MHz 60 MHz Unit SPCLK frequency ( = 1/S) SPCLK rising time SPCLK falling time 0.5S − 6 SPCLK low width 0.5S − 6 SPCLK high width Output data valid 0.5S − 18 →...
Page 570: Ad Conversion Characteristics
TMP92CF30 AD Conversion Characteristics Parameter Symbol Condition Typ. Unit Analog reference voltage ( + ) AVCC − 0.2 VREFH AVCC AVCC Analog reference voltage ( − ) DVSS + 0.2 VREFL DVSS DVSS AD converter power supply AVCC DVCC3A DVCC3A DVCC3A voltage AD converter ground...
Page 571: Connection Example
TMP92CF30 Recommended Oscillation Circuit The TMP92CF30 has been evaluated by the oscillator vender below. Use this information when selecting external parts. Note: The total load value of the oscillator is the sum of external loads (C1 and C2) and the floating load of the actual assembled board.
Page 572 TMP92CF30 Table of Special function registers (SFRs) The SFRs include the I/O ports and peripheral control registers allocated to the 8-Kbyte address space from 000000H to 001FF0H. (1) I/O Port (11) Clock gear, PLL (2) Interrupt control (12) 8-bit timer (3) Memory controller (13) 16-bit timer (4) TSI(Touch screen I/F)
Page 573 TMP92CF30 Table 5.1 I/O Register Address Map [1] Port (1/2) Address Name Address Name Address Name Address Name 0000H 0010H P4 0020H P8 0030H PC 1H P8FC2 1H PCFC2 2H PCCR 3H P4FC 3H P8FC 3H PCFC 4H P1 4H P5 4H P9 5H P9FC2 6H P1CR...
Page 574 TMP92CF30 [1] Port (2/2) Address Name Address Name Address Name Address Name 0080H 0090H PGDR 00A0H PT 00B0H PX 1H P1DR 1H PTFC2 1H PXFC2 2H PTCR 2H PXCR 3H PJDR 3H PTFC 3H PXFC 4H P4DR 4H PKDR 5H P5DR 5H PLDR 6H P6DR 6H PMDR...
Page 575 TMP92CF30 [2] INTC Address Name Address Name Address Name Address Name 00D0H INTE12 00E0H INTESBIADM 00F0H INTE0 0100H DMA0V 1H INTE34 1H INTESPI 1H INTETC01 1H DMA1V /INTEDMA01 2H INTE56 2H Reserved 2H INTETC23 2H DMA2V /INTEDMA23 3H INTE7 3H INTEUSB 3H INTETC45 3H DMA3V /INTEDMA45...
Page 576 TMP92CF30 [5] SDRAMC Address Name 0250H SDACR 1H SDCISR 2H SDRCR 3H SDCMM 4H SDBLS Address Name Address Name Address Name Address Name 0280H Reserved 0290H Reserved 02A0H Reserved 02F0H Reserved 1H Reserved 1H Reserved 1H Reserved 2H Reserved 2H Reserved 2H Reserved 3H Reserved 3H Reserved...
Page 577 TMP92CF30 [6] USBC (1/2) Address Name Address Name Address Name Address Name 0500H Descriptor 0780H ENDPOINT0 0790H EP0_STATUS 07A0H 1H ENDPOINT1 1H EP1_STATUS 1H EP1_SIZE_L_B 067FH (384 byte) 2H ENDPOINT2 2H EP2_STATUS 2H EP2_SIZE_L_B 3H ENDPOINT3 3H EP3_STATUS 3H EP3_SIZE_L_B 8H Reserved 8H EP0_SIZE_L_A 8H Reserved...
Page 578 TMP92CF30 [6] USBC (2/2) Address Name Address Name 07E0H Port Status 07F0H USBINTFR1 1H FRAME_L 1H USBINTFR2 2H FRAME_H 2H USBINTFR3 3H ADDRESS 3H USBINTFR4 4H Reserved 4H USBINTMR1 5H Reserved 5H USBINTMR2 6H USBREADY 6H USBINTMR3 7H Reserved 7H USBINTMR4 8H Set Descriptor STALL 8H USBCR1 Note: Do not access no allocated name address.
Page 579 TMP92CF30 [7] SPIC Address Name Address Name 0820H SPIMD 0830H SPITD0 1H SPIMD 1H SPITD0 2H SPICT 2H SPITD1 3H SPICT 3H SPITD1 4H SPIST 4H SPIRD0 5H SPIST 5H SPIRD0 6H SPICR 6H SPIRD1 7H SPICR 7H SPIRD1 CH SPIIE DH SPIIE [8] MMU Address...
Page 580 TMP92CF30 [9] NAND-Flash controller Address Name Address Name Address Name 08C0H NDFMCR0 08D0H NDRSCA0 1FF0H NDFDTR0 1H NDFMCR0 1H NDRSCA0 1H NDFDTR0 2H NDFMCR1 2H NDRSCD0 2H NDFDTR1 3H NDFMCR1 3H NDFDTR1 4H NDECCRD0 4H NDRSCA1 5H NDECCRD0 5H NDRSCA1 6H NDECCRD1 6H NDRSCD1 7H NDECCRD1...
Page 581 TMP92CF30 [10] DMAC Address Name Address Name Address Name Address Name 0900H HDMAS0 0910H HDMAS1 0920H HDMAS2 0930H HDMAS3 1H HDMAS0 1H HDMAS1 1H HDMAS2 1H HDMAS3 2H HDMAS0 2H HDMAS1 2H HDMAS2 2H HDMAS3 4H HDMAD0 4H HDMAD1 4H HDMAD2 4H HDMAD3 5H HDMAD0 5H HDMAD1...
Page 582 TMP92CF30 [11] CGEAR, PLL [12] 8-bit timer Address Name Address Name Address Name 10E0H SYSCR0 1100H TA01RUN 1110H TA45RUN 1H SYSCR1 2H SYSCR2 2H TA0REG 2H TA4REG 3H EMCCR0 3H TA1REG 3H TA5REG 4H EMCCR1 4H TA01MOD 4H TA45MOD 5H EMCCR2 5H TA1FFCR 5H Reserved 6H Reserved...
Page 583 TMP92CF30 [16] 10-bit ADC [17] WDT Address Name Address Name Address Name 12A0H ADREG0L 12B0H ADREGSPL 1300H WDMOD 1H ADREG0H 1H ADREGSPH 1H WDCR 2H ADREG1L 2H Reserved 3H ADREG1H 3H Reserved 4H ADREG2L 4H ADCM0REGL 5H ADREG2H 5H ADCM0REGH 6H ADREG3L 6H ADCM1REGL 7H ADREG3H...
Page 584 TMP92CF30 [20] I [21] MAC Address Name Address Name Address Name Address Name 1800H I2S0BUF 1810H Reserved 1BE0H MACMA 1BF0H 1H MACMA 2H MACMA 3H MACMA 4H MACMB 5H MACMB 6H MACMB 7H MACMB 8H I2S0CTL 8H Reserved 8H MACORL 9H I2S0CTL 9H Reserved 9H MACORL...
Page 585 TMP92CF30 (1) I/O ports (1/10) Symbol Name Address PORT1 0004H Data from external port (Output latch register is cleared to “0”) PORT4 0010H PORT5 0014H PORT6 0018H Data from external port (Output latch register is cleared to “0”) PORT7 001CH Data from external Data from external port Data from external port...
Page 586 TMP92CF30 (1) I/O ports (2/10) Symbol Name Address PORTM 0058H PORTN 005CH Data from external port (Output latch register is cleared to “1”) PORTP 0060H Data from external port (Output latch register is cleared to “0”) PORTR 0064H Data from external port (Output latch register is cleared to “0”) PORTT 00A0H...
Page 587 TMP92CF30 (1) I/O ports (3/10) Symbol Name Address P17C P16C P15C P14C P13C P12C P11C P10C PORT1 0006H P1CR control (Prohibit register RMW) 0: Input 1:Output PORT1 0007H P1FC function (Prohibit 0: Port register RMW) 1: Data (D8~D15) P47F P46F P45F P44F P43F...
Page 588 TMP92CF30 (1) I/O ports (4/10) Symbol Name Address P87F P86F P83F P82F P81F P80F PORT8 0023H P8FC function (Prohibit 0: Port 0: Port 0: Port 0: Port, 0: Port 0: Port register RMW) 1: <P87F2> 1: <P86F2> CSZA CSXA SDCS P87F2 P86F2 P83F2...
Page 589 TMP92CF30 (1) I/O ports (5/10) Symbol Name Address PC7C PC6C PC5C PC4C PC3C PC2C PC1C PC0C PORTC 0: Input 0: Input 0: Input 0: Input 0: Input 0: Input 0: Input 0: Input 0032H control port, port, port, port, port, port, port, port,...
Page 590 TMP92CF30 (1) I/O ports (6/10) Symbol Name Address PJ7F PJ6F PJ5F PJ4F PJ3F PJ2F PJ1F PJ0F 004FH PORTJ PJFC function (Prohibit 0: Port 0: Port 0: Port 0: Port 0: Port 0: Port 0: Port 0: Port register RMW) 1: SDCKE SDWE SDCAS SDRAS...
Page 591 TMP92CF30 (1) I/O ports (7/10) Symbol Name Address PP6F PP5F PP4F PP3F 0063H PORTP 0: Port 0: Port 0: Port PPFC function 0: Port (Prohibit register 1:INT7, 1:INT6, 1:INT5, RMW) TB1IN0 at TB0IN0 at TA7OUT TB0OUT0 <PP3F2>= <PP2F2>= 0 at<PP1F2> PP6F2 PP5F2 PP4F2...
Page 592 TMP92CF30 (1) I/O ports (8/10) Symbol Name Address PV7C PV6C PORTV 00AAH PVCR control (Prohibit register RMW) 0: Input 1: Output PV7F PV6F PORTV 00ABH PVFC function (Prohibit register RMW) 0: Port 0: Port 1: SCL 1: SDA PV7F2 PV6F2 PORTV 00A9H PVFC2...
Page 593 TMP92CF30 (1) I/O ports (9/10) Symbol Name Address P17D P16D P15D P14D P13D P12D P11D P10D PORT1 P1DR drive 0081H register Input/Output buffer drive register for standby mode P27D P26D P25D P24D P23D P22D P21D P20D PORT2 P2DR drive 0082H register Input/Output buffer drive register for standby mode P37D...
Page 594 TMP92CF30 (1) I/O ports (10/10) Symbol Name Address PG3D PG2D PORTG PGDR drive 0090H Input/Output buffer register drive register for standby mode PJ7D PJ6D PJ5D PJ4D PJ3D PJ2D PJ1D PJ0D PORTJ PJDR drive 0093H register Input/Output buffer drive register for standby mode PK7D PK6D PK5D...
Page 595: Interrupt Control
TMP92CF30 (2) Interrupt control (1/4) Symbol Name Address − INT0 − − − − I0M2 I0M1 I0M0 INTE0 INT0 enable 00F0H − − Always write “0” INT2 INT1 INT1 & INT2 I2M2 I2M1 I2M0 I1M2 I1M1 I1M0 INTE12 00D0H enable INT4 INT3 INT3 &...
Page 596 TMP92CF30 (2) Interrupt control (2/4) Symbol Name Address INTSPITX INTSPIRX INTSPI ISPITC ISPITM2 ISPITM1 ISPITM0 ISPIRC ISPIRM2 ISPIRM1 ISPIRM0 INTESPI 00E1H enable − INTUSB − − − − IUSBC IUSBM2 IUSBM1 IUSBM0 INTUSB INTEUSB 00E3H − − enable Always write “0” −...
Page 597 TMP92CF30 (2) Interrupt control (3/4) Symbol Name Address INTTC1/INTDMA1 INTTC0/INTDMA0 ITC1C ITC1M2 ITC1M1 ITC1M0 ITC0C ITC0M2 ITC0M1 ITC0M0 INTTC0/INTDMA0 & INTETC01 /IDMA1C /IDMA1M2 /IDMA1M1 /IDMA1M0 /IDMA0C /IDMA0M2 /IDMA0M1 /IDMA0M0 INTTC1/INTDMA1 00F1H /INTEDMA01 enable INTTC3/INTDMA3 INTTC2/INTDMA2 ITC3C ITC3M2 ITC3M1 ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0...
Page 598 TMP92CF30 (2) Interrupt control (4/4) Symbol Name Address DMA0V5 DMA0V4 DMA0V3 DMA0V2 DMA0V1 DMA0V0 DMA0 DMA0V start 0100H vector DMA0 start vector DMA1V5 DMA1V4 DMA1V3 DMA1V2 DMA1V1 DMA1V0 DMA1 DMA1V start 0101H vector DMA1 start vector DMA2V5 DMA2V4 DMA2V3 DMA2V2 DMA2V1 DMA2V0 DMA2...
Page 599 TMP92CF30 (3) Memory controller (1/4) Symbol Name Address B0WW3 B0WW2 B0WW1 B0WW0 B0WR3 B0WR2 B0WR1 B0WR0 Write waits Read waits BLOCK0 0001: 0 waits 0010: 1 wait 0001: 0 waits 0010: 1 wait CS/WAIT 0101: 2 waits 0110: 3 waits 0101: 2 waits 0110: 3...
Page 600 TMP92CF30 (3) Memory controller (2/4) Symbol Name Address B3WW3 B3WW2 B3WW1 B3WW0 B3WR3 B3WR2 B3WR1 B3WR0 Write waits Read waits BLOCK3 0001: 0 waits 0010: 1 waits 0001: 0 waits 0010: 1 waits CS/WAIT 0101: 2 waits 0110: 3 waits 0101: 2 waits 0110: 3...
Page 601: Memory Controller
TMP92CF30 (3) Memory controller (3/4) Symbol Name Address Memory M0V20 M0V19 M0V18 M0V17 M0V16 M0V15 M0V14-9 M0V8 address MAMR0 0142H mask register 0 0: Compare enable 1: Compare disable M0S23 M0S22 M0S21 M0S20 M0S19 M0S18 M0S17 M0S16 Memory start MSAR0 0143H address register 0...
Page 602 TMP92CF30 (3) Memory controller (4/4) Symbol Name Address OPGE OPWR1 OPWR0 Page Wait number on page Byte number in a page PMEMCR 0166H control page 00: 64 bytes 00: 1 CLK (n-1-1-1 mode) register access 01: 32 bytes 01: 2 CLK (n-2-2-2 mode) 0: Disable 10: 16 bytes 10: 3 CLK (n-3-3-3 mode)
Page 603 TMP92CF30 (4) TSI Symbol Name Address TSI7 INGE PTST TWIEN PYEN PXEN MYEN MXEN 0: Disable Input gate Detection INT4 TSICR0 control 01F0H control of interrupt 1: Enable condition 0 : OFF 0 : OFF 0 : OFF 0 : OFF register0 Port control...
Page 604: Sdram Controller
TMP92CF30 (5) SDRAM controller Symbol Name Address − SRDS SMUXW1 SMUXW0 SPRE SMAC Read Always Address multiplex SDRAM Read/Write SDRAM data shift write “0” type commands controller access SDACR 0250H function 00: Type A (A9- ) control 0: Disable register 01: Type B (A10- ) 0: Without 0: Disable...
Page 605 TMP92CF30 (6) USB controller (1/6) Symbol Name Address Descriptor RAM 0 0500H Descriptor RAM0 register Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Descriptor RAM 1 0501H Descriptor RAM1 register Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Descriptor RAM 2 0502H Descriptor RAM2 register...
Page 606 TMP92CF30 (6) USB controller (2/6) Symbol Name Address TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR Endpoint 0 status 0790H EP0_STATUS register TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR Endpoint 1 0791H status EP1_STATUS register TOGGLE SUSPEND STATUS[2] STATUS[1] STATUS[0] FIFO_DISABLE STAGE_ERR Endpoint 2 status 0792H...
Page 607: Usb Controller
TMP92CF30 (6) USB controller (3/6) Symbol Name Address Endpoint 1 DATASIZE9 DATASIZE8 DATASIZE7 size 07B1H EP1_SIZE_H_B register High B Endpoint 2 DATASIZE9 DATASIZE8 DATASIZE7 size 07B2H EP2_SIZE_H_B register High B Endpoint 0 DATASIZE9 DATASIZE8 DATASIZE7 size 07B3H EP3_SIZE_H_B register High B DIRECTION REQ_TYPE1 REQ_TYPE0...
Page 608 TMP92CF30 (6) USB controller (4/6) Symbol Name Address SetupRecei- 07C8H SetupReceived ved register REMOTEWAKEUP ALTERNATE[1] ALTERNATE[0] INTERFACE[1] INTERFACE[0] CONFIG[1] CONFIG[0] Current_ 07C9H Current_Config Config register S_INTERFACE G_INTERFACE S_CONFIG G_CONFIG G_DESCRIPT S_FEATURE C_FEATURE G_STATUS Standard- Request 07CAH Standard Request register SOFT_RESET G_PORT_STS G_DEVICE_ID VENDOR CLASS ExSTANDARD...
Page 609 TMP92CF30 (6) USB controller (5/6) Symbol Name Address Reserved7 Reserved6 PaperError Select NotError Reserved2 Reserved1 Reserved0 Port status 07E0H Port Status register − T[6] T[5] T[4] T[3] T[2] T[1] T[0] Frame register 07E1H FRAME_L T[10] T[9] T[8] T[7] CREATE FRAME_STS1 FRAME_STS0 Frame 07E2H FRAME_H...
Page 610 TMP92CF30 (6) USB controller (6/6) Symbol Name Address MSK_URST_STR MSK_URST_END MSK_SUS MSK_RESUME MSK_CLKSTOP MSK_CLKON interrupt 07F4H USBINTMR1 mask register 1 0: Be not masked 1: Be masked EP1_MSK_FA EP1_MSK_EA EP1_MSK_FB EP1_MSK_EB EP2_MSK_FA EP2_MSK_EA EP2_MSK_FB EP2_MSK_EB interrupt 07F5H USBINTMR2 mask register 2 0: Be not masked 1: Be masked EP3_MSK_FA EP3_MSK_EA...
Page 611 TMP92CF30 SPIC (1/2) Symbol Name Address SWRST CLKSEL2 CLKSEL1 CLKSEL0 0820H (Prohibit Software SYSCK Select Baud Rate RMW) reset 0: disable 000:Reserved 100: f 0: don’t 1: enable 001: f 101: f care 010: f 110: f 1: Reset SPI Mode 011: f 111: f /256...
Page 612 TMP92CF30 (7) SPIC (2/2) Symbol Name Address CRCD7 CRCD6 CRCD5 CRCD4 CRCD3 CRCD2 CRCD1 CRCD0 0826H CRC result register [7:0] SPICR CRCD15 CRCD14 CRCD13 CRCD12 CRCD11 CRCD10 CRCD9 CRCD8 register 0827H CRC result register [15:8] TXD7 TXD6 TXD5 TXD4 TXD3 TXD2 TXD1 TXD0...
Page 613 TMP92CF30 (8) MMU (1/7) Symbol Name Address 0880H Specify the bank number for the LOCAL-X area (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) LOCALX register LOCALPX program 0881H Bank for Specify the bank number for the LOCAL-X area LOCAL-X Settings of the X8 through X0 bits and their corresponding chip select signals...
Page 614 TMP92CF30 (8) MMU (2/7) Symbol Name Address 0890H Specify the bank number for the LOCAL-X area (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) LOCALX register LOCALRX read 0891H Bank for Specify the bank number for the LOCAL-X area LOCAL-X Settings of the X8 through X0 bits and their corresponding chip select signals...
Page 615 TMP92CF30 (8) MMU (3/7) Symbol Name Address 0898H Specify the bank number for the LOCAL-X area (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) LOCALX register LOCALWX write 0899H Bank for Specify the bank number for the LOCAL-X area LOCAL-X Settings of the X8 through X0 bits and their corresponding chip select signals...
Page 616 TMP92CF30 (8) MMU (4/7) Symbol Name Address 08A0H Specify the bank number for the LOCAL-X area (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) LOCALX register LOCALESX for DMA source 08A1H Bank for Specify the bank number for the LOCAL-X area LOCAL-X Settings of the X8 through X0 bits and their corresponding chip select signals...
Page 617 TMP92CF30 (8) MMU (5/7) Symbol Name Address 08A8H Specify the bank number for the LOCAL-X area (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) LOCALX register LOCALEDX for DMA destination 08A9H Bank for Specify the bank number for the LOCAL-X area LOCAL-X Settings of the X8 through X0 bits and their corresponding chip select signals...
Page 618 TMP92CF30 (8) MMU (6/7) Symbol Name Address 08B0H Specify the bank number for the LOCAL-X area (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) LOCALX register LOCALOSX for DMA source 08B1H Bank for Specify the bank number for the LOCAL-X area LOCAL-X Settings of the X8 through X0 bits and their corresponding chip select signals...
Page 619 TMP92CF30 (10) MMU (7/7) Symbol Name Address 08B8H Specify the bank number for the LOCAL-X area (Since bank 0 is overlapping with the COMMON area, this filed must not be specified as 0.) LOCALX register LOCALODX for DMA destination 08B9H Bank for Specify the bank number for the LOCAL-X area LOCAL-X Settings of the X8 through X0 bits and their corresponding chip select signals...
Page 620 TMP92CF30 (9) NAND-Flash controller (1/4) Symbol Name Address ECCE BUSY ECCRST NAND circuit Flash 08C0H enable control control control control reset control (Prohibit state control 0: Disable 0: “L” out 0: “L” out 0: “H” out 0: “H” out RMW) 0: Disable 0: −...
Page 621 TMP92CF30 (9) NAND-Flash controller (2/4) Symbol Name Address ECCD7 ECCD6 ECCD5 ECCD4 ECCD3 ECCD2 ECCD1 ECCD0 08C8H NANDF NAND Flash ECC Register (7-0) NDECCRD2 Code ECC ECCD15 ECCD14 ECCD13 ECCD12 ECCD11 ECCD10 ECCD9 ECCD8 Register2 08C9H NAND Flash ECC Register (15-8) ECCD7 ECCD6 ECCD5...
Page 622 TMP92CF30 (9) NAND-Flash controller (3/4) Symbol Name Address RS0A7 RS0A6 RS0A5 RS0A4 RS0A3 RS0A2 RS0A1 RS0A0 08D0H NAND Flash Reed-Solomon Calculation Result Address Register (7-0) NANDF read solomon RS0A9 RS0A8 NDRSCA0 Result address Register0 08D1H NAND Flash Reed-Solomon Calculation Result Address Register (9-8) RS0D7 RS0D6...
Page 623 TMP92CF30 (9) NAND-Flash controller (4/4) Symbol Name Address RS3A7 RS3A6 RS3A5 RS3A4 RS3A3 RS3A2 RS3A1 RS3A0 08DCH NANDF NAND Flash Reed-Solomon Calculation Result Address Register (7-0) read RS3A9 RS3A8 solomon NDRSCA3 Result address Register3 08DDH NAND Flash Reed- Solomon Calculation Result Address Register (9-8) NANDF...
Page 624 TMP92CF30 (10) DMAC (1/7) Symbol Name Address D0SA7 D0SA6 D0SA5 D0SA4 D0SA3 D0SA2 D0SA1 D0SA0 0900H Source address for DMA0 (7:0) D0SA15 D0SA14 D0SA13 D0SA12 D0SA11 D0SA10 D0SA9 D0SA8 source HDMAS0 0901H address Register0 Source address for DMA0 (15:8) D0SA23 D0SA22 D0SA21 D0SA20...
Page 625 TMP92CF30 (10) DMAC (2/7) Symbol Name Address D1SA7 D1SA6 D1SA5 D1SA4 D1SA3 D1SA2 D1SA1 D1SA0 0910H Set source address for DMA1 (7:0) D1SA15 D1SA14 D1SA13 D1SA12 D1SA11 D1SA10 D1SA9 D1SA8 source HDMAS1 0911H address Register1 Set source address for DMA1 (15:8) D1SA23 D1SA22 D1SA21...
Page 626 TMP92CF30 (10) DMAC (3/7) Symbol Name Address D2SA7 D2SA6 D2SA5 D2SA4 D2SA3 D2SA2 D2SA1 D2SA0 0920H Source address for DMA2 (7:0) D2SA15 D2SA14 D2SA13 D2SA12 D2SA11 D2SA10 D2SA9 D2SA8 source HDMAS2 0921H address Register2 Source address for DMA2 (15:8) D2SA23 D2SA22 D2SA21 D2SA20...
Page 627 TMP92CF30 (10) DMAC (4/7) Symbol Name Address D3SA7 D3SA6 D3SA5 D3SA4 D3SA3 D3SA2 D3SA1 D3SA0 0930H Set source address for DMA3 (7:0) D3SA15 D3SA14 D3SA13 D3SA12 D3SA11 D3SA10 D3SA9 D3SA8 source HDMAS3 0931H address Register3 Set source address for DMA3 (15:8) D3SA23 D3SA22 D3SA21...
Page 628 TMP92CF30 (10) DMAC (5/7) Symbol Name Address D4SA7 D4SA6 D4SA5 D4SA4 D4SA3 D4SA2 D4SA1 D4SA0 0940H Source address for DMA4 (7:0) D4SA15 D4SA14 D4SA13 D4SA12 D4SA11 D4SA10 D4SA9 D4SA8 source HDMAS4 0941H address Register4 Source address for DMA4 (15:8) D4SA23 D4SA22 D4SA21 D4SA20...
Page 629 TMP92CF30 (10) DMAC (6/7) Symbol Name Address D5SA7 D5SA6 D5SA5 D5SA4 D5SA3 D5SA2 D5SA1 D5SA0 0950H Source address for DMA5 (7:0) D5SA15 D5SA14 D5SA13 D5SA12 D5SA11 D5SA10 D5SA9 D5SA8 source HDMAS5 0951H address Register5 Source address for DMA5 (15:8) D5SA23 D5SA22 D5SA21 D5SA20...
Page 630 TMP92CF30 (10) DMAC (7/7) Symbol Name Address DMAE5 DMAE4 DMAE3 DMAE2 DMAE1 DMAE0 HDMAE enable 097EH Register DMA channel operation 0: Disable 1: Enable DMATE DMATR6 DMATR5 DMATR4 DMATR3 DMATR2 DMATR1 DMATR0 HDMATR timer 097FH Timer Maximum bus occupancy time setting Register operation The value to be set in <DMATR6:0>...
Page 631 TMP92CF30 (11) Clock gear, PLL Symbol Name Address XTEN WUEF PRCK USBCLK1 USBCLK0 System Select the clock of Warm-up Select clock USB(f timer -frequency Prescaler SYSCR0 10E0H control oscillator 00: Disable clock register0 circuit (fs) 01: Reserved 0: f 0: Stop 10: X1USB 1: f 11: f...
Page 632 TMP92CF30 (12) 8-bit timer (1/2) Symbol Name Address TA0RDE I2TA01 TA01PRUN TA1RUN TA0RUN TMRA01 Double IDLE2 TMRA01 Up counter Up counter TA01RUN 1100H register buffer 0: Stop prescaler (UC1) (UC0) 0: Disable 1: Operate 0: Stop and clear 1: Enable 1: Run (Count up) −...
Page 633 TMP92CF30 (12) 8-bit timer (2/2) Symbol Name Address TA4RDE I2TA45 TA45PRUN TA5RUN TA4RUN TMRA45 Double IDLE2 TMRA45 Up counter Up counter TA45RUN 1110H register buffer 0: Stop prescaler (UC5) (UC4) 0: Disable 1: Operate 0: Stop and clear 1: Enable 1: Run (Count up) −...
Page 634 TMP92CF30 (13) 16-bit timer (1/2) Symbol Name Address − TB0RDE I2TB0 TB0PRUN TB0RUN TMRB0 Always Double TMRB0 IDLE2 TB0RUN 1180H write “0”. counter buffer prescaler 0: Stop register (UC10) 1: Operate 0: disable 1: enable 0: Stop and clear 1: Run (Count up) −...
Page 635 TMP92CF30 (15) 16-bit timer (2/2) Symbol Name Address − TB1RDE I2TB1 TB1PRUN TB1RUN TMRB1 Always Double TMRB1 IDLE2 TB1RUN 1190H write “0”. counter buffer prescaler 0: Stop register (UC12) 0: disable 1: Operate 1: enable 0: Stop and clear 1: Run (Count up) −...
Page 636 TMP92CF30 (14) UART/Serial channels (1/2) Symbol Name Address Serial 1200H channel 0 SC0BUF (Prohibit buffer R (Receive) /W (Transmission) RMW) register Undefined EVEN OERR PERR FERR SCLKS R (Cleared to 0 when read) Undefined Serial 1201H 0: SCLK0 ↑ channel 0 Received Parity Parity...
Page 637 TMP92CF30 (14) UART/Serial channels (2/2) Symbol Name Address Serial 1208H channel 1 SC1BUF (Prohibit buffer R (Receive) /W (Transmission) RMW) register Undefined EVEN OERR PERR FERR SCLKS R (Cleared to 0 when read) Undefined Serial 1209H 0: SCLK1 ↑ channel 1 Received Parity Parity...
Page 638 TMP92CF30 (15) SBI Symbol Name Address SCK0 − SCK2 SCK1 /SWRMON Serial bus 1240H interface SBICR1 (Prohibit Always Number of transfer bits Acknowledge Setting for the divisor value “n” control RMW) read as “1”. 000: 8 001: 1 010: 2 register 1 mode (When writing)
Page 639 TMP92CF30 (16) AD converter (1/3) Symbol Name Address ADR01 ADR00 OVR0 ADR0RF conversion ADREG0L 12A0H result Overrun flag AD conversion Store Lower 2 bits of register 0 low 0:No generate result store flag AN0 AD conversion 1: Generate 1: Stored result ADR09 ADR08...
Page 640 TMP92CF30 (16) AD converter (2/3) Symbol Name Address ADRSP1 ADRSP0 OVSRP ADRSPRF High priority Conversion 12B0H ADREGSPL Register SP Overrun AD conversion Store Lower 2 bits of an 1: Generate result store flag AD conversion result 1: Stored ADRSP9 ADRSP8 ADRSP7 ADRSP6 ADRSP5...
Page 641 TMP92CF30 (16) AD converter (3/3) Symbol Name Address DACON ADCH2 ADCH1 ADCH0 REPEAT SCAN AD mode DAC and VREF Analog input channel select Latency Interrupt Repeat mode Scan mode ADMOD1 control 12B9H application 0: No Wait specification specification specification control 1:Start after when 0: Single...
Page 642: Watchdog Timer
TMP92CF30 (17) Watchdog timer Symbol Name Address − WDTE WDTP1 WDTP0 I2WDT RESCR Select detecting time Always WDMOD mode 1300H 1:Internally IDLE2 control 00: 2 write “0”. register connects 0: Stop 1: Enable 01: 2 WDT out to 1: Operate 10: 2 the reset pin 11: 2...
Page 643 TMP92CF30 (18) RTC (Real-Time Clock) Symbol Name Address Second SECR 1320H register Undefined “0” is read 40 sec. 20 sec. 10 sec. 8 sec. 4 sec. 2 sec. 1 sec. Minute MINR 1321H register Undefined “0” is read 40 min. 20 min.
Page 644 TMP92CF30 (19) Melody/alarm generator Symbol Name Address Alarm- pattern 1330H register Alarm pattern setting − − − − ALMINV MELALM Melody/ Free run counter Alarm Output alarm MELALMC 1331H control frequency frequency control 00: Hold invert 0: Alarm register Always write “0”. 01: Restart 1: Invert 1: Melody...
Page 645 TMP92CF30 (20) I Symbol Name Address B015 B014 B013 B012 B011 B010 B009 B008 B007 B006 B005 B004 B003 B002 B001 B000 Undefined Transmission buffer register (FIFO) Transmi- 1800H 28 27 17 16 ssion I2S0BUF (Prohibit RMW) Buffer B031 B030 B028 B027 B026...
Page 646 TMP92CF30 (21) MAC (1/2) Symbol Name Address Data register MACMA_LL 1BE0H Multiplier Undefined A-LL Multiplier A data register [7:0] MA15 MA14 MA13 MA12 MA11 MA10 Data register MACMA_LH 1BE1H Multiplier Undefined A-LH Multiplier A data register [15:8] MA23 MA22 MA21 MA20 MA19 MA18...
Page 647 TMP92CF30 (21) MAC (2/2) Symbol Name Address OR39 OR38 OR37 OR36 OR35 OR34 OR33 OR32 Data register Multiply and 1BECH MACOR_HLL Accumulate Undefined -HLL Multiply and Accumulate data register [39:32] OR47 OR46 OR45 OR44 OR43 OR42 OR41 OR40 Data register Multiply and 1BEDH MACOR_HLH...
Page 648: Notes And Restrictions
TMP92CF30 Notes and Restrictions Notation (1) The notation for built-in I/O registers is as follows: Register symbol <Bit symbol> Example: TA01RUN<TA0RUN> denotes bit TA0RUN of register TA01RUN. (2) Read-modify-write instructions (RMW) An instruction in which the CPU reads data from memory and writes the data to the same memory location in one instruction.
Page 649 TMP92CF30 Notes (1) AM0 and AM1 pins These pins are connected to the V (Power supply level) or the V (Grand level) pin. Do not alter the level when the pin is active. (2) Reserved address areas The 144Kbyte area (022000H~045FFFH) and 16 bytes area (FFFFF0H ∼ FFFFFFH) cannot be used since it is reserved for use as internal area.
Page 650: Package Dimensions
TMP92CF30 Package Dimensions LQFP176-P-2020-0.40F TOP VIEW Detail view of A (25/1) BOTTOM VIEW 2009-06-12 92CF30-648...
Page 651: Restrictions On Product Use
• The information contained herein is presented only as guidance for Product use. No responsibility is assumed by TOSHIBA for any infringement of patents or any other intellectual property rights of third parties that may result from the use of Product. No license to any intellectual property right is granted by this document, whether express or implied, by estoppel or otherwise.
Page 652 TMP92CF30 2009-06-12 92CF30-650...

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