Sony UP-D2550S Service Manual page 42

IC
MB86604L (FUJITSU)
C-MOS SCSI-2 PROTOCOL CONTROLLER
—TOP VIEW—
76
77
78 V
DD
79 GND
80
81
82
83
84
85
86
87
88
89
90 GND
91
92
93
94
95
96
97
98
99
100
PIN PIN
I/O SIGNAL I/O
NO. NO.
WR LDS
1 I ( ) 26 I
RD W
2 I (R/ ) 27 I
3 — V 28 —
DD
4 — GND 29 —
5 I CLK 30 I
RESET
6 I 31 I/O
INT
7 O INT ( ) 32 I/O
8 I MODE 33 I/O
DBP
9 I/O 34 I/O
10 — GND 35 I/O
11 I/O DB7 36 I/O
12 I/O DB6 37 I/O
13 I/O DB5 38 I/O
14 — VDD 39 I/O
15 — GND 40 —
16 — GND 41 I/O
17 I/O DB4 42 I/O
18 I/O DB3 43 I/O
19 I/O DB2 44 I/O
20 I/O DB1 45 I/O
21 — GND 46 I/O
22 I/O DB0 47 I/O
23 I TEST1 48 I/O
24 O TMOUT 49 I/O
25 — NC 50 I
MODE
BHE
CS1
CS0
RD
WR
INT
TMOUT
A0 - A4
LDP
D0 - D7
D8 - D15
UDP
MSG
C/D
I/O
ATN
BSY
SEL
RST
REQ
ACK
DBP
DB0 DB7
-
7-2
GND
GND
V
DD
PIN PIN
SIGNAL I/O SIGNAL I/O
NO. NO.
IOWR DMLDS DACK
( ) 51 I 76 I
IORD W
(DMR/ ) 52 O DREQ 77 I
V 53 — V 78 —
DD DD
GND 54 — GND 79 —
DMA0 55 I TP 80 I
LDMDP 56 — NC 81 I/O
DMD0 57 I TEST2 82 I/O
I/O
DMD1 58 I/O 83 I/O
DMD2 59 — GND 84 I/O
REQ
DMD3 60 I/O 85 I/O
C/D
DMD4 61 I/O 86 I/O
SEL
DMD5 62 I/O 87 I/O
MSG
DMD6 63 I/O 88 I/O
DMD7 64 — V 89 I/O
DD
GND 65 — GND 90 —
DMD8 66 — GND 91 I/O
RST
DMD9 67 I/O 92 I/O
ACK
DMD10 68 I/O 93 I/O
BSY
DMD11 69 I/O 94 I/O
DMD12 70 — GND 95 I/O
ATN
DMD13 71 I/O 96 I/O
DMD14 72 I A0 97 I/O
DMD15 73 I A1 98 I/O
UDMDP 74 I A2 99 I/O
DMBHE DMUDS
( ) 75 I A3 100 I
8
100
INTERNAL
80
PROCESSOR
77
2
1
7
MPU
24
INTERFACE
72 - 76
TIMER
81
82 - 89, 91 - 98
99
PHASE
63
CONTROLLER
61
58
71
69
SCSI TRANSMISSION
62
INTERFACE CONTROLLOR
67
60
68
9
22, 20 - 17,
13 - 11
SCSI INTERFACE
INPUT/OUTPUT
ACK
: ACKNOWLEGE
ATN
: ATTENTION
50
BSY
: BUSY
49
C/D
: CONTROL/DATA
48
DB0 DB7
- : DATA BUS0 - DATA BUS7
47
DBP
: DATA BUS PARITY
46
I/O
: INPUT/OUTPUT
45
MSG
: MESSAGE
44
REQ
: REQUEST
43
RST
: RESET
42
SEL
: SELECT
41
40
MPU INTERFACE
39
INPUT
38
A0 - A4 : ADDRESS0 - ADDRESS4
37
BHE UDS
( ) : BUS HIGH ENABLE (UPPER DATA STOROBE)
36
CS0
: CHIP SELECT 0
35
CS1
: CHIP SELECT 1
34
MODE : MODE
33
RD W
(R/ ) : READ (READ/WRITE)
32
WR LDS
( ) : WRITE (LOWER DATA STOROBE)
31
30
OUTPUT
29
INT
INT ( ) : INTERRUPT REQUEST
28
TMOUT : TIME OUT
27
26
INPUT/OUTPUT
D0 - D15 : DATA0 - DATA15
LDP : LOWER DATA PARITY
UDP : UPPER DATA PARITY
DMA INTERFACE
INPUT
DACK : DMA ACKNOWLEDGE
DMA0 : DMA ADDRESS 0
SIGNAL
DMBHE (DMUDS) : DMA BUS HIGH ENABLE (DMA UPPER DATA STOROBE)
IORD (DMR/W) : I/O READ (DMA READ/WRITE)
A4
CS0
IOWR(DMLDS) : I/O WRITE (DMA LOWER DATA STOROBE)
TP : TRANSFER PERMISSION
V
DD
GND
CS1
OUTPUT
LDP DREQ : DMA REQUEST
D0
INPUT/OUTPUT
D1
DMD0 - DMD15 : DMD DATA0 - DMD DATA15
D2
LDMDP : LOWER DMA DATA PARITY
D3
D4 UDMDP : UPPER DMA DATA PARITY
D5
INPUT
D6
CLK : CLOCK
D7
RESET : RESET
GND
TEST1, 2 : TEST
D8
D9
D10 ( ) : WHEN "MODE" (8PIN) IS "L" LEVEL INPUT.
D11
D12
D13
D14
D15
UDP
BHE UDS
( )
VARIOUS
REGISTER
RECEIVE-MCS
BUFFER
(32-BYTE)
SEND-MCS
BUFFER
(32-BYTE)
COMMAND, USER
PROGRAM, MEMORY
(256-BYTE)
DATA REGISTER
(32-BYTE)
52
DREQ
51
DACK
50
DMBHE
30
DMA0
26
IOWR
27
IORD
DMA
55
INTERFACE
TP
31
LDMDP
49
UDMDP
32 - 39, 41 - 48
DMD0 - DMD7
DMD8 - DMD15
UP-D2550S (UC,CE)