Siemens A55 Repair Documentation page 35

Functions Pin
Requirements
Key click function
Audio Multiplex AUDIOA1
Matrix AUDIOA2
AUDIOB1
AUDIOB2
AUDIOC1
AUDIOC2
I2S Interface CLO,
WAO,
DAO
Audio DAC VDDDAC
PLL VDDPLL
PLLOUT
V1.20
A55/C55_Hitachi
Sequence
Pushing a key of the phone can be combined
with a key click. This function is also realized
with the audio amplifier in pulsed mode. The
ASIC creates a digital PWM signal. Frequency
of the PWM signal is 3.5 kHz.
The start-up is similar to the ringer function. If
the audio is off, the start-up is done with
KEYCLICK time constant. If audio is starting
with AUDIO start-up, the time constant is
switched to KEYCLICK mode, too. If the audio
amplifier is already up and running, the
KEYCLICK is connected to the amplifier and
audio signal is muted due to open multiplexer.
Each of the three input sources should be
switched
Furthermore a conversion can be done.
Following sources:
- Mono differential
- Mono
parallel)
- Stereo
The DAC can be switched off for using the
analog external inputs. This principle will allow
to do each combination and have different
modes for stereo and mono in parallel.
The I2S Interface is a three-wire connection
that handles
channels. The three lines are the clock (CLO),
the serial data line (DAO) and the word select
line (WAO). The master I2S also generates the
appropriate clock frequency for CLO set to 32
times the sampling rate (FS)
For digital to analog conversion a 16-bit sigma
delta converter is used. Digital input signal is
delivered with an I2S interface. The I2S
interface should be 16-bit format. To be able to
work with all possible operating modes, the
sampling frequency can vary from 8kHz to
48kHz. The performance of the audio output
signal must be guaranteed over the full range
the human ear is able to hear. This means for
FS=8kHz the noise at frequencies higher than
FS/2 must be suppressed. This is done by DSP
and a single ended 2
The clock for the I2S will be varied accordingly
to the sampling frequency. Therefore a clock
recovery based on CLO signal of the I2S can
be implemented. This clock recovery must
smooth any jitter of this clock to reduce the
noise of the DAC.
The PLL will have three frequency modes to
produce a 32xCLO clock for the DSP and the
DAC. The loop filter is realized with an external
RC circuit. This PLL also contains a lock
detector circuit.
Page 35 of 48
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to Mono and Stereo
Single Ended (both
two time multiplexed
nd
order Low Pass filter.
ICM MP CCQ GRM
outputs.
channels
data
04/03