Sharp CD-PC1881V Service Manual page 55

ICV3 VHiSDM4260C-1: DRAM (SDM4260C)
Port Name
Pin No.
1 VDD Power supply
2-10 DQ0-DQ7 Data input/output
11*,12* NC Not used
13 WE Read/write enable
14 RAS Row address strobe
15* NC Not used
16-19 A0-A3 Address input (row/refresh: A0 to A3) (Column: A0 to A3)
20 VDD Power supply
21 VSS Ground
22-26 A4-A8 Address input (row/refresh: A4 to A8) (Column: A4 to A8)
27 OE Output enable
28,29 UCAS, LCAS Column address strobe
30* NC Not used
31-34 DQ8-DQ11 Data input/output
35 VSS Ground
36-39 DQ12-DQ15 Data input/output
40 VSS Ground
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
RAS
14
29
LCAS
28
UCAS
13
WE
A0 16
A0-A8
17
A1
A2
18
19
A3
A4
22
23
A5
A0-A8
A6 24
A7
25
A8
26
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Clock generating
circuit
Coidmn decoder
I/O control circuit
Memory cell array
Figure 55 BLOCK DIAGRAM OF IC
– 55 –
Function
Lower data
Lowar
Input buffer
Upper
Lower data
Output buffer
Upper data
Input buffer
Upper data
Output buffer
CD-PC1881V
1
VDD
20
40
35
VSS
21
2 DQ0
3 DQ1
10
DQ7
31 DQ8
32
DQ9
39
DQ15
27
OE