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Memory Bus Error
The hardware is programmed to generate an SMI on single-bit data errors in the memory array if ECC memory
is installed. The SMI handler records the error and the DIMM location to the system event log. Double-bit
errors in the memory array are mapped to the SMI because the mBMC cannot determine the location of the
bad DIMM. The double-bit errors may have corrupted the contents of SMRAM. The SMI handler will log the
failing DIMM number to the mBMC if the SMRAM contents are still valid. The ability to isolate the failure down
to a single DIMM may not be available on certain platforms, and/or during early POST.
System Limit Error
The mBMC monitors system operational limits. It manages the A/D converter, defining voltage and
temperature limits as well as fan sensors and chassis intrusion. Any sensor values outside of specified limits
are fully handled by the mBMC. The BIOS does not generate an SMI to the host processor for these types of
system events.
Processor Failure
The BIOS detects any processor BIST failures and logs the event. The failed processor can be identified by
the first OEM data byte field in the log. For example, if processor 0 fails, the first OEM data byte will be 0. The
BIOS depends upon the mBMC to log the watchdog timer reset event.
If an OS device driver is using the watchdog timer to detect software or hardware failures and that timer
expires, an Asynchronous Reset (ASR) is generated, which is equivalent to a hard reset. The POST portion of
the BIOS can query the BMC for a watchdog reset event as the system reboots, and then log this event in the
SEL.
Boot Event
The BIOS downloads the system date and time to the mBMC during POST and logs a boot event. This record
does not indicate an error, and software that parses the event log should treat it as such.
Error Messages and Error Codes
The BIOS indicates the current testing phase during POST by writing a hex code to I/O location 80h. If errors
are encountered, error messages or codes will either be displayed to the video screen, or if an error has
occurred prior to video initialization, errors will be reported through a series of audio beep codes.
Post Error Messages
Message Displayed
Gate20 Error
Multi-Bit ECC Error
Parity Error
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Table 3. Memory BIOS Messages
Description
The BIOS is unable to properly control the server board's Gate
A20 function, which controls access of memory over 1 MB. This
may indicate a problem with the server board.
This message will only occur on systems using ECC enabled
memory modules. ECC memory has the ability to correct single-
bit errors that may occur from faulty memory modules.
A multiple bit corruption of memory has occurred, and the ECC
memory algorithm cannot correct it. This may indicate a
defective memory module.
Fatal Memory Parity Error. System halts after displaying this
message.
Table 4. Boot BIOS Messages
Chapter 4
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