Mitsubishi Electric DD-5000 Service Manual page 54

Table 3-5-10 (3/5) TMP94CS40AF
Pin
Name
No.
55 P B 0 Port B0: output port. (Initializes to "1" output.)
C A S 1 Column address strobe 1: CAS strobe
signal for DRAM is developed if address is
within the assigned address range.
L C A S 1 Lower column address strobe 1: lower CAS
strobe signal for DRAM is developed if
address is within the assigned address
range.
LLCAS1 Lower-lower column address strobe 1:
lower-lower CAS strobe signal for DRAM is
developed if address is within the assigned
address range.
54 P B 1 Port B1: output port. (Initializes to "1" output.)
U C A S 1 Upper column address strobe 1: upper CAS
strobe signal for DRAM is developed if
address is within the assigned address
range.
L U C A S 1 Lower-upper column address strobe 1:
lower-upper CAS strobe signal for DRAM is
developed if address is within the assigned
address range.
53 P B 2 Port B2: output port. (Initializes to "1" output.)
H L C A S 1 Upper-lower column address strobe 1:
upper lower CAS strobe signal for DRAM is
developed if address is within the assigned
address range.
52 P B 3 Port B3: output port. (Initializes to "1" output.)
H U C A S 1 Upper-upper column address strobe 1:
upper-upper CAS strobe signal for DRAM is
developed if address is within the assigned
address range.
51 P B 4 Port B4: output port. (Initializes to "1" output.)
W E 1 Write enable 1: write enable signal for
DRAM is developed.
140 P C 0 Port C0: I/O port.
TO1 Timer output 1: 8 bit timer 0 or timer 1 is
developed.
TO7 Timer output 7: 16 bit timer 7 is developed.
141 P C 1 Port C1: I/O port.
TO3 Timer output 3: 8 bit timer 2 or timer 3 is
developed.
T O B Timer output B: 16 bit timer B is developed.
17 P D 0 Port D0: I/O port.
TO4 Timer output 4: 16 bit timer 4 is developed.
18 P D 1 Port D1: I/O port.
TI4 Timer input 4: 16 bit timer 4 is entered.
INT4 Interrupt request terminal 4: programmable
at rising/falling edges.
19 P D 2 Port D2: I/O port.
TI5 Timer input 5: 16 bit timer 4 is entered.
INT5 Interrupt request terminal 5: Interrupt
request terminal at rising edge.
20 P D 4 Port D4: I/O port
TO6 Timer output 6: 16 bit timer 6 is developed.
21 P D 5 Port D5: I/O port.
TI6 Timer input 6: 16 bit timer 6 is entered.
INT6 Interrupt request terminal 6: programmable
at rising/falling edges.
22 P D 6 Port D6: I/O port.
TI7 Timer input 7: 16 bit timer 6 is entered.
INT7 Interrupt request terminal 7: Interrupt
request terminal at rising edge.
24 P E 0 Port E0: I/O port.
TO8 Timer output 8: 16 bit timer 8 is developed.
25 P E 1 Port E1: I/O port.
TI8 Timer input 8: 16 bit timer 8 is entered.
INT8 Interrupt request terminal 8: programmable
at rising/falling edges.
13 P E 2 Port E2: I/O port.
TI9 Timer input 9: 16 bit timer 8 is entered.
INT9 Interrupt request terminal 9: Interrupt
request terminal at rising edge.
Function
Table 3-5-10 (4/5) TMP94CS40AF
Pin
Name
No.
14 P E 4 Port E4: I/O port.
TOA Timer output A: 16 bit timer A is developed.
15 P E 5 Port E5: I/O port.
TIA Timer input A: 16 bit timer A is entered.
INTA Interrupt request terminal A: programmable
at rising/falling edges.
16 P E 6 Port E6: I/O port.
TIB Timer input B: 16 bit timer A is entered.
INTB Interrupt request terminal B: Interrupt
request terminal at rising edge.
24 P F 0 Port F0: I/O port.
TXD0 Serial transfer data 0 (open drain output
capability)
25 P F 1 Port F1: I/O port.
R X D 0 Serial reception data 0
26 P F 2 Port F2: I/O port.
C T S 0 Serial transfer capability 0
S C L K 0 Serial clock I/O 0
27 P F 4 Port F4: I/O port.
TXD1 Serial transfer data 1 (open drain output
capability)
28 P F 5 Port F5: I/O port.
R X D 1 Serial reception data 1
29 P F 6 Port F6: I/O port.
C T S 1 Serial transfer capability 1
S C L K 1 Serial clock I/O 1
152 AN0 – AN7 Analog input: input of 10 bit A/D converter.
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159
6 PH0 Port H0: I/O port.
TC0 Terminal count 0: Strobe output signal is
developed at "H" level when count value of
micro DMA channel 0 is 0.
7 PH1 Port H1: I/O port.
TC1 Terminal count 1: Strobe output signal is
developed at "H" level when count value of
micro DMA channel 1 is 0.
8 PH2 Port H2: I/O port.
TC2 Terminal count 2: Strobe output signal is
developed at "H" level when count value of
micro DMA channel 2 is 0.
9 PH3 Port H3: I/O port
TC3 Terminal count 3: Strobe output signal is
developed at "H" level when count value of
micro DMA channel 3 is 0.
10 PH4 Port H4: I/O port (schmitt input)
INT0 Interrupt request terminal 0: programmable
at level/rising edge. (Schmitt input)
31 N M I Nonmaskable interrupt request terminal:
interrupt request terminal at falling edge.
Available at rising edge by using a program.
32 WDTOUT Watchdog timer output terminal
4 AM0,1 Address mode: selects start-up external
5 data bus width after releasing reset.
AM1= "0" AM0= "0":
starts with 8 bit external data bus
AM1= "0" AM0= "1":
starts with 16 bit external data bus
AM1= "1" AM0= "0":
starts with 32 bit external data bus
AM1= "1" AM0= "1":
starts from internal ROM
43 TEST0,1 Test: used with "GND" fixed.
48
36 C L K Clock: develops system clock.
38 X1/X2 Oscillation connection terminal
40
3-34
Function