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Asus AAEON FWS-7840 User Manual

Asus AAEON FWS-7840 User Manual

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FWS-7840
Network Appliance
User's Manual 1
Ed
st
Last Updated: September 24, 2021

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Summary of Contents for Asus AAEON FWS-7840

  • Page 1 FWS-7840 Network Appliance User’s Manual 1 Last Updated: September 24, 2021...
  • Page 2 Copyright Notice This document is copyrighted, 2021. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgement All other products’ name or trademarks are properties of their respective owners. Microsoft Windows is a registered trademark of Microsoft Corp. ⚫ Intel® and Xeon® are registered trademarks of Intel Corporation ⚫ ITE is a trademark of Integrated Technology Express, Inc. ⚫...
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity FWS-7840 ⚫ Console Cable ⚫ Ear Brackets ⚫ SATA Cable ⚫ SATA Power Cable ⚫ HDD Kit ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. All cables and adapters supplied by AAEON are certified and in accordance with the material safety laws and regulations of the country of sale.
  • Page 7 As most electronic components are sensitive to static electrical charge, be sure to ground yourself to prevent static charge when installing the internal components. Use a grounding wrist strap and contain all electronic components in any static-shielded containers. If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii.
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A0 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯 醚(PBDE) (Pb) (Hg) (Cd) (Cr(VI)) (PBB) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 ○ ○...
  • Page 10 China RoHS Requirement (EN) Hazardous and Toxic Materials List AAEON System QO4-381 Rev.A0 Hazardous or Toxic Materials or Elements Component Name PCB and Components Wires & Connectors for Ext.Connections Chassis CPU & RAM HDD Drive LCD Module Optical Drive Touch Control Module Battery This form is prepared in compliance with the provisions of SJ/T 11364.

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions ....................... 5 2.1.1 FWS-7840 System ..................5 2.1.2 FWS-7840 Main Board ................6 2.1.3 PER-T629 NIM Two Slot Riser Card ............8 2.1.4 PER-T636 PCIe [x8] Riser Card ..............
  • Page 12 CPU and Heatsink Installation ................29 2.10 Installing NIM Modules ..................34 Chapter 3 - AMI BIOS Setup ....................36 System Test and Initialization ................37 AMI BIOS Setup ..................... 38 Setup Submenu: Main ..................39 Setup Submenu: Advanced ................. 40 3.4.1 CPU Configuration ..................41 3.4.2...
  • Page 13 3.6.1.1 Key Management ................68 Setup Submenu: Boot ..................70 Setup Submenu: Save & Exit ................71 Chapter 4 – Drivers Installation .................... 72 Drivers Download and Installation ..............73 Appendix A - Watchdog Timer Programming ..............74 Watchdog Timer Initial Program ................ 75 Appendix B –...

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Form Factor 1U Rackmount Network Platform Processor Intel® Xeon® W Processors (Comet Lake) System Memory 2 x DDR4 2666-2933 U-DIMM Chipset Intel® W480 Ethernet 8 x Intel® i350 AM4 Gigabit Ethernet Ports Bypass Two-pair Bypass BIOS AMI BIOS Serial ATA 2 x SATA III (6.0 Gbps) ports Storage...
  • Page 16 System Power Consumption MTBF Display Chipset Intel® W480 Graphic Engine HDMI from CPU Optional Resolution 3840 x 2160 Connector HDMI (Optional) Serial Port 1 x RJ-45 Console Keyboard and Mouse 2 x USB3.0 Environmental Operating Temperature 32°F ~ 104°F (0°C ~ 40°C) Storage Temperature -4°F ~ 140°F (-20°C ~ 60°C) Operating Humidity...

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Dimensions

    Dimensions 2.1.1 FWS-7840 System Chapter 2 – Hardware Information...

  • Page 19: Fws-7840 Main Board

    2.1.2 FWS-7840 Main Board Component Side Chapter 2 – Hardware Information...
  • Page 20 Main Board Solder Side Chapter 2 – Hardware Information...

  • Page 21: Per-T629 Nim Two Slot Riser Card

    2.1.3 PER-T629 NIM Two Slot Riser Card Chapter 2 – Hardware Information...

  • Page 22: Per-T636 Pcie [X8] Riser Card

    2.1.4 PER-T636 PCIe [x8] Riser Card Chapter 2 – Hardware Information...

  • Page 23: Per-T639 Dual Sfp+ Port Expansion Card

    2.1.5 PER-T639 Dual SFP+ Port Expansion Card Chapter 2 – Hardware Information...

  • Page 24: Jumpers And Connectors

    Jumpers and Connectors Component Side Chapter 2 – Hardware Information...
  • Page 25 Solder Side Chapter 2 – Hardware Information...

  • Page 26: List Of Jumpers

    List of Jumpers The FWS-7840 system board is configured with a number of jumpers which can be configured for your application. This section details those jumpers and their settings. Label Function Clear CMOS 2.3.1 Clear CMOS 1-3, 2-4 3-5, 4-6 Normal (Default) Clear CMOS Note: To avoid unintended operation or damage to the system, do not use any other...

  • Page 27: List Of Connectors

    List of Connectors The FWS-7840 system board is configured with a number of connectors which can be used for configuring your system and connecting with external modules. This section details those connectors and settings. Label Function DDR4 UDIMM Slot DDR4 UDIMM Slot SATA Power SATA Power Battery Header...

  • Page 28: Battery Header (Cn6)

    Label Function Front Panel Header LED5 Status LED SFP 1Gbps Port (Optional, Colay with CN23) SFP 1Gbps Port (Optional, Colay with CN23) SATA1 SATA Connector SATA2 SATA Connector SLOT1 Mini Card socket (Optional, mSATA) USB1 USB3.1 Header 2.4.1 Battery Header (CN6) Signal +3.3V 2.4.2 Digital I/O Header (CN10)

  • Page 29: Case Open Sensor (Cn11)

    2.4.3 Case Open Sensor (CN11) Signal Case Open 2.4.4 COM Port (C17) Signal Signal DCD2 DSR2 RXD2 RTS2 TXD2 CTS2 DTR2 2.4.5 Front Panel Pin Header (FP1) Signal Signal Power Button SW+ Ground Hardware Reset SW+ Ground PWRLED Ground HDDACT HDD LED- Chapter 2 –...

  • Page 30: Per-T629 Connectors

    PER-T629 Connectors Chapter 2 – Hardware Information...

  • Page 31: Per-T636 Pcie [X8] Riser Card

    PER-T636 PCIe [x8] Riser Card 2.6.1 PER-T636 Connectors Chapter 2 – Hardware Information...

  • Page 32: Per-T636 Installation Steps

    2.6.2 PER-T636 Installation Steps Before beginning installation make sure the system is powered down and the power sources are disconnected. Have the PER-T636 PCIe [x8] Riser Card and the PCIe card you wish to install ready. Step 1: Remove the upper panel of the chassis by unscrewing seven (7) retaining screws.
  • Page 33 Step 3: Insert PER-T636 card into the PCIe [x8] slot on the board. Secure the card by fastening a screw to the bracket. Step 4: Remove the rear I/O bracket by removing the retaining screw and sliding the bracket out. Chapter 2 –...
  • Page 34 Step 5: Insert the expansion card, ensuring the rear bracket lines up and the card inserts into the riser card. Secure with the screw removed in Step 4. Chapter 2 – Hardware Information...

  • Page 35: Dual Sfp+ Port Expansion Card

    PER-639 Dual SFP+ Port Expansion Card 2.7.1 PER-639 Connectors Chapter 2 – Hardware Information...

  • Page 36: Installation

    2.7.2 PER-639 Installation Before beginning installation make sure the system is powered down and the power sources are disconnected. Have the PER-T639 Expansion Card ready to install. Step 1: Remove the upper panel of the chassis by unscrewing seven (7) retaining screws.
  • Page 37 Step 3: Remove the punchouts at the front of the system. Step 4: Attach the M3*22mm spacer to the main board as shown. Chapter 2 – Hardware Information...
  • Page 38 Step 5: Insert the PER-T639 card by first aligning the SFP+ ports with the punchouts, then inserting the card into the slot. Finally, secure the card by fastening the bracket to the standoff with a screw. Chapter 2 – Hardware Information...

  • Page 39: Drive Installation

    2.5” Drive Installation This section details the steps of how to install the dual 2.5” drive assembly for the FWS-7840. Before beginning installation make sure the system is powered down and the power sources are disconnected. You will need to have your 2.5” drives and 2.5” drive assembly brackets ready to install.
  • Page 40 Step 3: Mount the two 2.5” drives onto the drive brackets as shown, with four screws on each side. Step 4: Mount the assembly onto the chassis, securing with four screws. Chapter 2 – Hardware Information...
  • Page 41 Step 5: Attach the SATA and SATA Power cables, first to the bottom drive, then the top drive. Chapter 2 – Hardware Information...

  • Page 42: Cpu And Heatsink Installation

    CPU and Heatsink Installation This section details the steps of how to install the CPU and heatsink for the FWS-7840. Before beginning installation make sure the system is powered down and the power sources are disconnected. Make sure you have your CPU and heatsink ready to install. Step 1: Remove the upper panel of the chassis by unscrewing seven (7) retaining screws.
  • Page 43 Step 3: Unlock the CPU retaining bracket and lift up the bracket. Chapter 2 – Hardware Information...
  • Page 44 Step 4: Remove the plastic cover. Step 5: Insert the CPU into the socket. Ensure the notches on the CPU line up correctly with the socket. If you haven’t already, apply a thin layer of thermal paste to the top of the CPU.
  • Page 45 Step 6: Close and lock the CPU bracket in place. Step 7: Place the heatsink and secure with four post screws. Ensure the heatsink is orientated so the fins are parallel to the airflow direction. Chapter 2 – Hardware Information...
  • Page 46 Step 8: Replace the air duct, securing with the screw from Step 2. Chapter 2 – Hardware Information...

  • Page 47: Installing Nim Modules

    2.10 Installing NIM Modules This section details the steps of how to install NIM modules for the FWS-7840. This applies for new installation, or removal/replacement of modules. Before beginning installation make sure the system is powered down and the power sources are disconnected.
  • Page 48 Step 3: Insert the new NIM Module (or cover) and secure with a screw on the bottom of the chassis. Chapter 2 – Hardware Information...

  • Page 49: Chapter 3 - Ami Bios Setup

    Chapter 3 Chapter 3 - AMI BIOS Setup...

  • Page 50: System Test And Initialization

    System Test and Initialization The system uses certain routines to perform testing and initialization during the boot up sequence. If an error, fatal or non-fatal, is encountered, the system will output a few short beeps or an error message. The board can usually continue the boot up sequence with non-fatal errors.

  • Page 51: Ami Bios Setup

    AMI BIOS Setup The AMI BIOS ROM has a pre-installed Setup program that allows users to modify basic system configurations, which is stored in the battery-backed CMOS RAM and BIOS NVRAM so that the information is retained when the power is turned off. To enter BIOS Setup, press <Del>...

  • Page 52: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – AMI BIOS Setup...

  • Page 53: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – AMI BIOS Setup...

  • Page 54: Cpu Configuration

    3.4.1 CPU Configuration Options Summary Active Processor Optimal Default, Failsafe Default Cores Number of cores to enable in each processor package. Hyper-Threading Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Hyper-Threading Technology Intel® Speed Shift Disable Technology Enable Optimal Default, Failsafe Default Enable/Disable Intel®...

  • Page 55: Pch-Fw Configuration

    3.4.2 PCH-FW Configuration Chapter 3 – AMI BIOS Setup...

  • Page 56: Firmware Update Configuration

    3.4.2.1 Firmware Update Configuration Options Summary Me FW Image Enabled Re-Flash Disabled Optimal Default, Failsafe Default Enable/Disable Me FW Image Re-Flash function. FW Update Disabled Enabled Optimal Default, Failsafe Default Enable/ Disable ME FW Update function Chapter 3 – AMI BIOS Setup...

  • Page 57: Trusted Computing

    3.4.3 Trusted Computing Options Summary Security Deice Enable Optimal Default, Failsafe Default Support Disable Enables or Disables BIOS support for security device. O.S. will not show Security Device. TCG EFI protocol and INT1A interface will not be available. SHA-1 PCR Bank Disabled Optimal Default, Failsafe Default Enabled...
  • Page 58 Options Summary Platform Hierarchy Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Platform Hierarchy Storage Hierarchy Enabled Optimal Default, Failsafe Default Disabled Enable or Disable Storage Hierarchy Endorsement Enabled Optimal Default, Failsafe Default Hierarchy Disabled Enable or Disable Endorsement Hierarchy TPM 2.0 UEFI Spec TCG_2 Optimal Default, Failsafe Default...

  • Page 59: Sata And Rst Configuration

    3.4.4 SATA And RST Configuration Options Summary SATA Controller(s) Enabled Optimal Default, Failsafe Default Disabled Enable/Disable SATA Device. SATA Mode AHCI Optimal Default, Failsafe Default Selection Intel RST Premium With Intel Optane System Acceleration Determines how SATA controller(s) operate. Hot Plug Disabled Optimal Default, Failsafe Default Enabled...

  • Page 60: Sio Configuration

    3.4.5 SIO Configuration Chapter 3 – AMI BIOS Setup...

  • Page 61: Serial Port 0 Configuration

    3.4.5.1 Serial Port 0 Configuration Options Summary Use This Device Enabled Optimal Default, Failsafe Default Disabled Enable/Disable this Logical Device Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8; IRQ=4; IO=2F8; IRQ=3; Allow user to change device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 62: Serial Port 1 Configuration

    3.4.5.2 Serial Port 1 Configuration Options Summary Use This Device Enabled Optimal Default, Failsafe Default Disabled Enable/Disable this Logical Device Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8; IRQ=3; IO=3F8; IRQ=4; Allow user to change device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 63: Parallel Port Configuration

    3.4.5.3 Parallel Port Configuration Options Summary Use This Device Enabled Optimal Default, Failsafe Default Disabled Enable or Disable this Logical Device Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=378h; IRQ=5; IO=378h; IRQ=5,6,7,10,11,12; IO=278h; IRQ=5,6,7,10,11,12; IO=3BCh; IRQ=5,6,7,10,11,12; Allow user to change device resource settings. New settings will be reflected on this setup page after system restarts.

  • Page 64: Hardware Monitor

    3.4.6 Hardware Monitor Chapter 3 – AMI BIOS Setup...

  • Page 65: Smart Fan Function

    3.4.6.1 Smart Fan Function Chapter 3 – AMI BIOS Setup...
  • Page 66 3.4.6.1.1 Fan 1/ 2 Setting Options Summary Smart Fan 1/2 Mode Software Mode Optimal Default, Failsafe Default Automatic Mode Smart Fan Mode Select Manual PWM Optimal Default, Failsafe Default Setting 0~255 Manual Mode: Fan will work with this Manual PWM Value Temperature select CPU Temperature (DTS) Optimal Default, Failsafe Default...
  • Page 67 Options Summary Fan full Speed Optimal Default, Failsafe Default Temperature limit Fan will full speed when temperature higher than this limit Fan start PWM Optimal Default, Failsafe Default Fan will start with this PWM value Chapter 3 – AMI BIOS Setup...

  • Page 68: Serial Port Console Redirection

    3.4.7 Serial Port Console Redirection Options Summary Console Redirection Enabled Optimal Default, Failsafe Default Disabled Console Redirection Enable or Disable Console Redirection Settings The settings specify how the host computer and the remote computer (which the user is using) will exchange data. Both computers should have the same or compatible settings.

  • Page 69: Com0 Console Redirection Settings

    3.4.7.1 COM0 Console Redirection Settings Options Summary Terminal Type VT100 VT100+ Optimal Default, Failsafe Default VT-UTF8 ANSI Emulation: ANSI: Extended ASCII char set. VT100: ASCII char set. VT100+: Extends VT100 to support color, function keys, etc. VT-UTF8: Uses UTF8 encoding to map Unicode. Bits per second 9600 19200...
  • Page 70 Options Summary Data Bits Optimal Default, Failsafe Default Data Bits Parity None Optimal Default, Failsafe Default Even Mark Space A Parity bit can be sent with the data bits to detect some transmission errors. Even: parity bit is 0 if the num of 1’s in the data bits is even. Odd: parity bit is 0 if the num of 1’s in the data bits is odd.
  • Page 71 Options Summary Select FunctionKey and KeyPad on Putty. Chapter 3 – AMI BIOS Setup...

  • Page 72: Power Management

    3.4.8 Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select power supply mode. Restore AC Power Last State Loss Always On Optimal Default, Failsafe Default Always Off Select power state when power is re-applied after a power failure. RTC wake system Disabled Optimal Default, Failsafe Default...

  • Page 73: Digital Io Port Configuration

    3.4.9 Digital IO Port Configuration Options Summary DIO Port1~4 Output Optimal Default, Failsafe Default Input Set DIO as Input or Output Output Level High Optimal Default, Failsafe Default Set output level when DIO pin is output DIO Port5~8 Output Input Optimal Default, Failsafe Default Set DIO as Input or Output Chapter 3 –...

  • Page 74: Lan Bypass Configuration

    3.4.10 LAN Bypass Configuration Options Summary Configure LAN LED OFF Optimal Default, Failsafe Default Bypass Status LED RED LED ON RED LED BLINK RED LED FAST BLINK GREEN LED ON GREEN LED BLINK GREEN LED FAST BLINK LAN Bypass Status LED Mode for Power-on ByPass PassTru Optimal Default, Failsafe Default...
  • Page 75 Options Summary WDT Configuration System Reset Optimal Default, Failsafe Default Force ByPass Configure LAN kit behavior when WDT is triggered. (Bypass/Pass Through) Chapter 3 – AMI BIOS Setup...

  • Page 76: Case Open Configuration

    3.4.11 Case Open Configuration Options Summary Case Open Disabled Optimal Default, Failsafe Default Warning Enabled Clear Case Open detecting function Chapter 3 – AMI BIOS Setup...

  • Page 77: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – AMI BIOS Setup...

  • Page 78: System Agent (Sa) Configuration

    3.5.1 System Agent (SA) Configuration Options Summary VT-d Disabled Optimal Default, Failsafe Default Enabled VT-d capability Chapter 3 – AMI BIOS Setup...

  • Page 79: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 80: Secure Boot

    3.6.1 Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key (PK) is enrolled, and the System is in User mode. The mode change requires platform reset Secure Boot Mode Standard Custom Optimal Default, Failsafe Default...

  • Page 81: Key Management

    3.6.1.1 Key Management Options Summary Provision Factory Disabled Optimal Default, Failsafe Default Defaults Enabled Install factory default Secure Boot keys after the platform reset and while the System is in Setup mode Restore Factory Force System to User Mode. Install factory default Secure Boot key Keys databases.
  • Page 82 Secure Boot Variables Enroll Factory Defaults or load certificates from a file: 1. Public Key Certificate in: a) EFI_SIGNATURE_LIST b) EFI_CERT_X509 (DER encoded) c) EFI_CERT_RSA2048 (bin) d) EFI_CERT_SHAXXX 2. Authenticated UEFI Variable 3. EFI PE/COFF Image (SHA256) Key Source: Default, External, Mixed Chapter 3 –...

  • Page 83: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable or Disable Quiet Boot option. Network Stack Disabled Optimal Default, Failsafe Default Enabled Enable/Disable UEFI Network Stack. UEFI Hard Disk Drive BBS Specifies the Boot Device Priority sequence from available Priorities.

  • Page 84: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – AMI BIOS Setup...

  • Page 85: Chapter 4 - Drivers Installation

    Chapter 4 Chapter 4 – Drivers Installation...

  • Page 86: Drivers Download And Installation

    Drivers Download and Installation Drivers for the FWS-7840 can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/rackmount-network-appliance-fws-7840 Download the driver(s) you need and follow the steps below to install them. Step 1 – LAN Drivers Open the Step 1 - LAN folder.

  • Page 87: Appendix A - Watchdog Timer Programming

    Appendix A Appendix A - Watchdog Timer Programming...

  • Page 88: Watchdog Timer Initial Program

    Watchdog Timer Initial Program Table 1 : SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E(Note1) 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F(Note2) 0x2F or 0x4F Table 2 : Watchdog relative register table Register BitNum Value...
  • Page 89 ************************************************************************************ // SuperIO relative definition (Please reference to Table 1) #define byte SIOIndex //This parameter is represented from Note1 #define byte SIOData //This parameter is represented from Note2 #define void IOWriteByte(byte IOPort, byte Value); #define byte IOReadByte(byte IOPort); // Watch Dog relative definition (Please reference to Table 2) #define byte TimerLDN //This parameter is represented from Note3 #define byte TimerReg //This parameter is represented from Note4 #define byte TimerVal // This parameter is represented from Note24...
  • Page 90 ************************************************************************************ Main VOID // Procedure : AaeonWDTConfig // (byte)Timer : Time of WDT timer.(0x00~0xFF) // (boolean)Unit : Select time unit(0: second, 1: minute). AaeonWDTConfig(); // Procedure : AaeonWDTEnable // This procudure will enable the WDT counting. AaeonWDTEnable(); ************************************************************************************ Appendix A – Watchdog Timer Programming...
  • Page 91 ************************************************************************************ // Procedure : AaeonWDTEnable AaeonWDTEnable () VOID WDTEnableDisable( EnableLDN, EnableReg, EnableBit, 1 // Procedure : AaeonWDTConfig AaeonWDTConfig () VOID // Disable WDT counting WDTEnableDisable( EnableLDN, EnableReg, EnableBit, 0 // Clear Watchdog Timeout Status WDTClearTimeoutStatus(); // WDT relative parameter setting WDTParameterSetting();...
  • Page 92 ************************************************************************************ SIOEnterMBPnPMode() VOID Switch(SIOIndex){ Case 0x2E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0x55); Break; Case 0x4E: IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0xAA); Break; SIOExitMBPnPMode() VOID IOWriteByte(SIOIndex, 0x02); IOWriteByte(SIOData, 0x02); SIOSelectLDN(byte LDN) VOID IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, LDN);...
  • Page 93 ************************************************************************************ SIOBitSet(byte LDN, byte Register, byte BitNum, byte Value) VOID Byte TmpValue; SIOEnterMBPnPMode(); SIOSelectLDN(byte IOWriteByte(SIOIndex, Register); TmpValue = IOReadByte(SIOData); TmpValue &= ~(1 << BitNum); TmpValue |= (Value << BitNum); IOWriteByte(SIOData, TmpValue); SIOExitMBPnPMode(); SIOByteSet(byte LDN, byte Register, byte Value) VOID SIOEnterMBPnPMode(); SIOSelectLDN(LDN);...

  • Page 94: Appendix B - Standard Lan Bypass Platform Setting

    Appendix B Appendix B – Standard LAN Bypass Platform Setting...

  • Page 95: Status Led

    Status LED The FWS-7840 features a Status LED indicator which can be configured using the AAEON SDK. The Status LED can be programed to indicate different system statuses. This section provides information on how to program and configure the Status LED. B.1.1 Status LED Configuration Table 1 : Truth Table of Status LED...

  • Page 96: Sample Code

    B.1.2 Sample Code ****************************************************************************************** **** #define Byte CPLD_SLAVE_ADDRESS //This parameter is represented from Note1 #define Byte OFFSET //This parameter is represented from Note2 ****************************************************************************************** **** bData = aaeonSmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET); switch( LED_FLAG) case 0: //LED Off //BIT2=0, BIT1=0, BIT0=0 bData = bData & 0xF8; break;...
  • Page 97 //Green LED On //BIT2=1, BIT1=1, BIT0=1 bData = (bData & 0xF8) | 0x07; break; case 5: //Green LED Blink //BIT2=1, BIT1=0, BIT0=1 bData = (bData & 0xF8) | 0x05; break; case 6: //Green LED Fast Blink //BIT2=1, BIT1=1, BIT0=0 bData = (bData & 0xF8) | 0x06; break;...

  • Page 98: Lan Bypass

    LAN Bypass The FWS-7840 provides a LAN Bypass kit, allowing uninterrupted network traffic even if a single in-line appliance is shut down or hangs. This section details how to configure and program the LAN Bypass. B.2.1 LAN Bypass Configuration Table 1 : ID Select table of LAN kit LAN_ID3 LAN_ID2 LAN_ID1...
  • Page 99 Table 3 : LAN Bypass relative register mapping table CPLD Slave Address 0x90 (Note1) Attribute Offset(SMBUS) BitNum Value LAN_ID3 0x01(Note2) (Table 1) LAN_ID2 0x01(Note2) (Table 1) LAN_ID1 0x01(Note2) (Table 1) LAN_ID0 0x01(Note2) (Table 1) PWR_ON 0x01(Note2) (Table 2) PWR_OFF 0x01(Note2) (Table 2) WDT_EN 0x01(Note2)

  • Page 100: Sample Code

    B.2.2 Sample Code ****************************************************************************************** **** #define Byte CPLD_SLAVE_ADDRESS //This parameter is represented from Note1 #define Byte OFFSET //This parameter is represented from Note2 ****************************************************************************************** **** // Select Lan Pair BYTE bLanSel = LAN_PAIR; BYTE bData = SmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET); // Set Reg01h bit3 if(bLanSel &...
  • Page 101 bData = bData & 0xDF; else // Bypass bData = bData | 0x20; // WDT Action (Reg01h bit4) if(SET_WDT_RESET) // Reset bData = bData & 0xEF; else // Bypass bData = bData | 0x10; SmbusWriteByte(CPLD_SLAVE_ADDRESS, OFFSET, bData); // Apply Settings (Reg01h bit7) bData = SmbusReadByte(CPLD_SLAVE_ADDRESS, OFFSET);...

  • Page 102: Software Reset Button (General Propose Input)

    Software Reset Button (General Propose Input) The FWS-7840 provides a general purpose input button which can be configured by the AAEON SDK. This section details how to configure and program this feature. B.3.1 Software Reset Button Configuration Table 2 : Software Reset Button register table Function Description Reading this register returns the pin level status which is...

  • Page 103: Sample Code

    B.3.2 Sample Code ************************************************************************************ #define Word BTN_STS //This parameter is represented from Note1 #define Byte BTN_STS_R //This parameter is represented from Note2 ************************************************************************************ GET_Value (Word IoAddr, Byte BitNum,Byte Value) Byte BYTE TmpValue; TmpValue = inportb (IoAddr); return (TmpValue & (1 << BitNum)) ************************************************************************************ Main VOID...

  • Page 104: Appendix C - Digital I/O Ports

    Appendix C Appendix C – Digital I/O Ports...

  • Page 105: Digital I/O Register

    Digital I/O Register Table 2: SuperIO relative register table Default Value Note SIO MB PnP Mode Index Register Index 0x2E 0x2E or 0x4E SIO MB PnP Mode Data Register Data 0x2F 0x2F or 0x4F Table 3 : Digital Input/Output relative register table Register BitNum Note...

  • Page 106: Digital I/O Sample Program

    Digital I/O Sample Program ********************************************************************* // SuperIO relative definition (Please reference to Table 2) #define SIOIndex 0x2E #define SIOData 0x2F #define DIOLDN 0x07 IOWriteByte(byte IOPort, byte Value); IOReadByte(byte IOPort); // DIO relative definition (Please reference to Table 3) #define DirReg1 0xC8 // GPIO1- GPIO4 #define DirReg2...
  • Page 107 ********************************************************************* Main VOID Boolean PinStatus ; // Procedure : AaeonReadPinStatus // Input : Example, Read Digital I/O Pin 3 status // Output : InputStatus : 0: Digital I/O Pin level is low 1: Digital I/O Pin level is High PinStatus = AaeonReadPinStatus( Pin3Bit // Procedure : AaeonSetOutputLevel // Input :...
  • Page 108 ********************************************************************* AaeonReadPinStatus(byte PinBit) Boolean Boolean PinStatus ; If (PinBit < Pin5Bit) { If (PinBit < Pin3Bit) { PinBit + 1; } else { PinBit + 2; PinStatus = IoBitRead( StatusReg1, PinBit } else if ((PinBit > Pin4Bit) && (PinBit < Pin7Bit)) PinStatus = IoBitRead( StatusReg2, (PinBit - PinBit4) + 3 } else if (PinBit == Pin7Bit)
  • Page 109 ********************************************************************* SIOEnterMBPnPMode() VOID IOWriteByte(SIOIndex, 0x87); IOWriteByte(SIOIndex, 0x01); IOWriteByte(SIOIndex, 0x55); IOWriteByte(SIOIndex, 0x55); SIOExitMBPnPMode() VOID IOWriteByte(SIOIndex, 0x02); IOWriteByte(SIOData, 0x01); SIOSelectLDN(byte LDN) VOID IOWriteByte(SIOIndex, 0x07); // SIO LDN Register Offset = 0x07 IOWriteByte(SIOData, ********************************************************************* Appendix C – Digital I/O Ports...
  • Page 110 ********************************************************************* IoBitRead(byte Address, byte BitNum) Boolean Byte TmpValue; TmpValue = IOReadByte(Address); TmpValue &= (1 << BitNum); If(TmpValue == 0) Return 0; Return 1; IoBitSet(byte Address, byte BitNum, Byte Value) Boolean Byte TmpValue; TmpValue = IOReadByte(Address); TmpValue &= ~(1 << BitNum); TmpValue |= (Value &...
  • Page 111 TmpValue |= (Mode << ((PinBit – Pin4Bit) + 3) IOWriteByte(SIOData, TmpValue); } else if (PinBit == Pin7Bit) { IOWriteByte(SIOIndex, DirReg3); TmpValue = IOReadByte(SIOData); TmpValue &= ~(1 << TmpValue |= (Mode << IOWriteByte(SIOData, TmpValue); } else IOWriteByte(SIOIndex, DirReg4); TmpValue = IOReadByte(SIOData); TmpValue &= ~(1 <<...

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