Table of Contents
Advertisement
PDV-LC10
3. BLOCK DIAGRAM AND SCHEMATIC DIAGRAM
3.1 BLOCK DIAGRAM
RF
TA
Spindle
Motor
FA
Slider
B
PDVDS ASSY
CN2001
CN2001
V2001 VAW1051
12
A
PDVDM ASSY
LA9701M
RF
IC101
3
170
RF IC
181
VCO
112-119
PWM
161
LPF
FG
162
9-12
32 33
20
54
2-5
48
18
16
47
14
45
IC201
SERVO DSP
FG
LC78652W
55
46
26
To CN401
PDV-LC10 Only
10
–
16
CN602
CN2001
5
6
OSC2
80
X2001
OSG1
81
78
30
UD/RL
77
29
µ-CONTROL IC
ZOOM
SEG0
47
31
SEG15
COM0
23
26
COM3
LCD
Panel
IC608
KM48V2100CS
16M bit DRAM
VBR Buffer
IC610
PD4995A
MY-CHIP
22-50
DRAM I/F
A/D
CONV.
(bus arbitor)
Sync
Demod
CPU
I/F
ECC &
ID Reg.
DMA
Spindle
control
CD-ROM Sync gen.
Sub-CPU
Sub-code Buffer
I/F
108-111
72-77,102,103
203
SHI-ASIC
1
44
146
52-59 146-163
IC602
74
PD3410A
SH1 ASIC
103
98 97 78
84
64
82
6
–
15
24 25
27 28 30
19 36 37 39 40
26
–
35
4 5
7 8
10
39 16 17 19 20
15
19
21
7
18 11
87
71
—
RESET OUT
67
SCK0
74
SI0
52
IC2001
PE5060A
S2001
56
57
I
96
S2013
97
: RF SIGNAL ROUTE
: AUDIO SIGNAL ROUTE
(V/CB)
: V/CB SIGNAL ROUTE
(Y)
: Y SIGNAL ROUTE
(C)
: C SIGNAL ROUTE
FLDV
9
55-66
56
SREQ
XRESET
165
27
4
16
107
IC603
TC74VHC541AFT
126
3V-5V
LVL
2-5
60
SHIFT
62
102
118
70
SETUP
ENTER
STOP
TOPMEN
PLAY/PAUSE
REV
FWD
TITLE
UP
DOWN
LEFT
RIGHT
MENU
SELEG
Advertisement
Table of Contents
