Sony CDX-GT40U Service Manual page 40

CDX-GT40U/GT40UW/GT42UE/GT44U/GT45U/GT47UE
Pin No. Pin Name
61 DAO5 (SUB-CH)
62 DVSS5
63 VDD1-3
64 VSS-2
65 XVSS3
66 XI
67 XO
68 XVDD3
69 ADVDD3
70 ADIN1 (IN_L-CH)
71 ADVREFL
72 ADVCM
73 ADVREFH
74 ADIN2 (IN_R-CH)
75 ADVSS3
76 MS
77 BUS0
78 BUS1
79 BUS2/So
80 BUS3/Si
81 BUCK/SCL
82 /CCE
83 VDD3-2
84 VSS-3
85 /RST
86 VDD1-4
87 DEC_REQ
88 BSIF-REQ
89 BSIF-GATE
90 BSIF_DATA
91 BSIF_BCK
92 BSIF_LRCK
93 DEC_XMUTE
94 ZDET
95 CD MON0/SP_DATA
96 CD MON1/SP_CLK
97 TEST
98 PDO
99 TMAX
100 LPFN
40
I/O
O SUB channel data output terminal
― Ground terminal
― Power supply terminal (+1.5V)
― Ground terminal
― Ground terminal
I System clock input terminal (16.9344 MHz)
O System clock output terminal (16.9344 MHz)
― Power supply terminal (+3.3V)
― Power supply terminal (+3.3V)
I Audio signal input terminal (L channel)
O Reference voltage output terminal
O Reference voltage output terminal
O Reference voltage output terminal
I Audio signal input terminal (R channel)
― Ground terminal
I I/F mode selection signal input terminal
I/O Bus data input/output with the USB controller
I/O Bus data input/output with the USB controller
O Serial data output to the USB controller
I Serial data input from the USB controller
I Bus clock signal input from the USB controller
I Chip enable signal input from the USB controller
― Power supply terminal (+3.3V)
― Ground terminal
I Reset signal input from the system controller
― Power supply terminal (+1.5V)
O Request signal output to the USB controller
O Request signal output to the USB controller
I Gate signal input from the USB controller
I Audio data input from the USB controller
I Bit clock signal input from the USB controller
I L/R sampling clock signal (44.1 kHz) input terminal for audio data input
I Muting on/off control signal input from the USB controller
O Zero detection signal output terminal
O Spectrum analyzer data output to the USB controller
I Spectrum analyzer data transfer clock signal input from the USB controller
I Setting terminal for test mode
O Phase error margin signal between EFM signal and PLCK signal output terminal
O TMAX detection result output terminal
I Inverted signal input from the operation amplifi er for PLL loop fi lter
Description
Fixed at "L" in this set
Normally fi xed at "L"