HP 5305 B Operating And Service Manual page 38

9E-8-1. INTRODUCTION
9E-8-2. This subsection of the manual contains the
following information:
a. A signal list that gives the signal name and con-
nector pin number of each signal that intercon-
nects with the mainframe (see Table 9E-8-1).
b. Signal waveforms at key points in the input
amplifiers and clock circuits.
PIN
SIGNAL NAME
NO.
1
2
3
4 COMMON RETURN
5
6
7 F2
8 INHIBIT
9 OPEN
10 CLOSE
11 LOG
12
13 EXPONENT
14 OVERFLOW
15 RESET
16 CLOCK
17 MAX TIME
18 TIME BASE OUTPUT
SECTION IX E
5305B 1100 MHz COUNTER
SUBSECTION VIII
CIRCUIT DIAGRAMS
Table 9E-8-1. Counter Signal List
+5V Circuit operating voltages.
-5V
-17V
Common power and signal return line.
Signal to be countend in the mainframe.
F1 Goes low when the mainframe counter reaches 9% full-scale.
"9" Tied to pin 14.
Time Base Clock 10 MHz or 10 MHz ÷16.
High during the measurement cycle, low during the display cycle.
Low signal forces the main gate flip-flop in the mainframe
to the open position.
Low signal forces the main gate flip-flop in the mainframe
to the closed position.
Logarithmic pulse tram from time base triggers main gate flip-
NC flop on rising edge.
Inverted log pulses while main gate in mainframe is open
indicates number of auto-ranging steps.
Low signal enables overflow and storage.
High signal resets all registers.
10 MHz reference signal from mainframe crystal oscillator.
Low signal enables closing of the main gate in the mainframe
on next log pulse. Rising edge initiates display cycle.
Output from the time base decade that is selected by the
time base select code on pins 22, 23, and 24.
c. Component location views of the printed-circuit
boards.
d. Schematic diagrams of the counter
9E-8-3. Use the information in this subsection in con-
junction with the information provided in Subsection V,
Maintenance, while troubleshooting the counter.
DESCRIPTION
Model 5305B
Circuit Diagrams
.
9E-8-1