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MAIN(VIDEO) SCHEMATIC DIAGRAM
DCO0
DCO1
DCO2
DCO3
TO PARAGON
DYO0
DYO1
DYO2
DYO3
OUTH
TO MAIN IF(CN104),
OUTV
CPU,PARAGON
TO PARAGON
CLK27A
TO CPU
VOI_IN
VOI_OUT
TO CPU,PARAGON
VOI_CLK
TO CPU
VIF_CS
TO CPU,OP DRV
T_F_V_RST
VC0
VC1
VC2
VC3
TO CPU
BLKA
BLKB
BLKC
OSD_HD
TO CPU,PARAGON
OSD_VD
DOT_CLK
TO CPU
PSCTL
ANA_IN_H
TO PARAGON
ASPECT
REG_4.8V
REG_3.1V
TO PARAGON
REG_1.7V
GND
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-15(No.YF124)
TL3202
TL3203
ASPECT
L3201
NQR0602-001X
HDCVF
VDCVF
TL3201
CSYNC
VDOUT
SCANMODE
C3206
0.01
VDD(C)
VSS
RESVD
RESHD
SDOUT
SDIN
SCLK
CS
C3207
0.01
VDD(I)
VSS
RST
L3202
NQR0602-001X
C3202
C3203
0.1
0.1
SCANEN
AVDD
AVSS
VREF1
YSOUT
COMP1
ABAR1
YCOUT
IC3201
JCP8055FP-2
IREF1
AVSS
AVDD
COUT
VREF2
CBOUT
COMP2
ABAR2
R3208
820
L3203
L3204
NQR0602-001X
10µ
IC3202
MM3143BN-X
3.1V
VIN
VOUT
GND
C3219
STBY
NC
1
T
T
C3204
C3205
10/6.3
47/6.3
C3218
1
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