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1. Description
2. Features
SC16C2550
Dual UART with 16 bytes of transmit and receive FIFOs
and infrared (IrDA) encoder/decoder
Rev. 03 — 19 June 2003
The SC16C2550 is a 2 channel Universal Asynchronous Receiver and Transmitter
(UART) used for serial data communications. Its principal function is to convert
parallel data into serial data and vice versa. The UART can handle serial data rates
up to 5 Mbits/s.
The SC16C2550 is pin compatible with the ST16C2550. It will power-up to be
functionally equivalent to the 16C2450. The SC16C2550 provides enhanced UART
functions with 16-byte FIFOs, modem control interface, DMA mode data transfer. The
DMA mode data transfer is controlled by the FIFO trigger levels and the TXRDY and
RXRDY signals. On-board status registers provide the user with error indications and
operational status. System interrupts and modem control features may be tailored by
software to meet specific user requirements. An internal loop-back capability allows
on-board diagnostics. Independent programmable baud rate generators are provided
to select transmit and receive baud rates.
The SC16C2550 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature
range, and is available in plastic PLCC44, LQFP48 and DIP40 packages.
2 channel UART
5 V, 3.3 V and 2.5 V operation
Industrial temperature range
Pin and functionally compatible to 16C2450 and software compatible with
INS8250, SC16C550
Up to 5 Mbits/s data rate at 5 V and 3.3 V, and 3 Mbits/s at 2.5 V
16 byte transmit FIFO to reduce the bandwidth requirement of the external CPU
16 byte receive FIFO with error flags to reduce the bandwidth requirement of the
external CPU
Independent transmit and receive UART control
Four selectable Receive FIFO interrupt trigger levels
Automatic software/hardware flow control
Programmable Xon/Xoff characters
Software selectable Baud Rate Generator
Sleep mode
Standard asynchronous error and framing bits (Start, Stop, and Parity Overrun
Break)
Transmit, Receive, Line Status, and Data Set interrupts independently controlled
Product data
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Table of Contents
Related Manuals for Philips SC16C2550
Summary of Contents for Philips SC16C2550
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Page 1: Description
Independent programmable baud rate generators are provided to select transmit and receive baud rates. The SC16C2550 operates at 5 V, 3.3 V and 2.5 V and the Industrial temperature range, and is available in plastic PLCC44, LQFP48 and DIP40 packages. -
Page 2: Ordering Information
flat package; 48 leads; body 7 × 7 × 1.4 mm SC16C2550IB48 LQFP48 SOT313-2 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 2 of 46... -
Page 3: Block Diagram
CDA, CDB CONTROL RXRDYA, RXRDYB GENERATOR DSRA, DSRB LOGIC 002aaa119 XTAL1 XTAL2 Fig 1. SC16C2550 block diagram. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 3 of 46... -
Page 4: Pinning Information
DTRA RTSA OP2A INTA INTB OP2B XTAL1 CTSB XTAL2 RTSB DSRB 002aaa105 Fig 2. DIP40 pin configuration. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 4 of 46... - Page 5 RESET DTRB DTRA RTSA OP2A SC16C2550IA44 TXRDYB RXRDYA INTA INTB OP2B 002aaa103 Fig 3. PLCC44 pin configuration. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 5 of 46...
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Page 6: Pin Description
Chip Select A, B (Active-LOW). This function is associated with individual channels, A through B. These pins enable data transfers between the user CPU and the SC16C2550 for the channel(s) addressed. Individual UART sections (A, B) are addressed by providing a logic 0 on the respective CSA, CSB pin. - Page 7 Read strobe (Active-LOW strobe). A logic 0 transition on this pin will load the contents of an internal register defined by address bits A0-A2 onto the SC16C2550 data bus (D0-D7) for access by external CPU. Write strobe (Active-LOW strobe). A logic 0 transition on this pin will transfer the contents of the data bus (D0-D7) from the external CPU to an internal register that is defined by address bits A0-A2.
- Page 8 7, 8 Transmit data A, B. These outputs are associated with individual serial transmit channel data from the SC16C2550. The TX signal will be a logic 1 during reset, idle (no data), or when the transmitter is disabled. During the local loop-back mode, the TX output pin is disabled and TX data is internally connected to the UART RX input.
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Page 9: Functional Description
CPU, increases performance, and reduces power consumption. The SC16C2550 is capable of operation up to 5 Mbits/s with a 80 MHz clock. With a crystal or external clock input of 7.3728 MHz, the user can select data rates up to 460.8 kbits/s. -
Page 10: Internal Registers
CSB = 0 UART channel B 6.2 Internal registers The SC16C2550 provides two sets of internal registers (A and B) consisting of 12 registers each for monitoring and controlling the functions of each channel of the UART. These registers are shown in Table 4. -
Page 11: Fifo Operation
flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the SC16C2550 will suspend TX transmissions as soon as the stop bit of the character in process is shifted out. Transmission is resumed after the CTS input returns to a logic 0, indicating more data may be sent. -
Page 12: Special Feature Software Flow Control
In the event that the receive buffer is overfilling and flow control needs to be executed, the SC16C2550 automatically sends an Xoff message (when enabled) via the serial TX output to the remote modem. The SC16C2550 sends the Xoff1,2 characters as soon as received data passes the programmed trigger level. To clear this condition, the SC16C2550 will transmit the programmed Xon1,2 characters as soon as receive data drops below the programmed trigger level. -
Page 13: Programmable Baud Rate Generator
80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock input. The SC16C2550 can be configured for internal or external clock operation. For internal clock oscillator operation, an industry standard microprocessor crystal is connected externally between the XTAL1 and XTAL2 pins. -
Page 14: Dma Operation
FIFO in a block sequence determined by the receive trigger level and the transmit FIFO. In this mode, the SC16C2550 sets the TXRDY (or RXRDY) output pin when characters in the transmit FIFO is below 16, or the characters in the receive FIFOs are above the receive trigger level. - Page 15 (OP2A, OP2B) RXRDYA, RXRDYB GENERATOR LOGIC CDA, CDB 002aaa120 XTAL1 XTAL2 Fig 6. Internal loop-back mode diagram. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 15 of 46...
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Page 16: Register Descriptions
Dual UART with 16 bytes of transmit and receive FIFOs and IrDA encoder/decoder 7. Register descriptions Table 7 details the assigned bit functions for the SC16C2550 internal registers. The assigned bit functions are more fully defined in Section 7.1 through Section 7.11. -
Page 17: Transmit (Thr) And Receive (Rhr) Holding Registers
The serial receive section also contains an 8-bit Receive Holding Register (RHR) and a Receive Serial Shift Register (RSR). Receive data is removed from the SC16C2550 and receive FIFO by reading the RHR register. The receive section provides a mechanism to prevent false starts. -
Page 18: Ier Versus Transmit/Receive Fifo Interrupt Mode Operation
UART for transmission via the transmission media. The interrupt is cleared either by reading the ISR register, or by loading the THR with new data characters. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003... -
Page 19: Ier Versus Receive/Transmit Fifo Polled Mode Operation
7.2.2 IER versus Receive/Transmit FIFO polled mode operation When FCR[0] = logic 1, resetting IER[0-3] enables the SC16C2550 in the FIFO polled mode of operation. In this mode, interrupts are not generated and the user must poll the LSR register for TX and/or RX data status. Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). -
Page 20: Fifo Mode
Logic 0 = Set DMA mode ‘0’ Logic 1 = Set DMA mode ‘1’ Transmit operation in mode ‘0’: When the SC16C2550 is in the 16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode (FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and... -
Page 21: Interrupt Status Register (Isr)
RX FIFO trigger level 7.4 Interrupt Status Register (ISR) The SC16C2550 provides four levels of prioritized interrupts to minimize external software interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the ISR will provide the user with the highest pending interrupt level to be serviced. -
Page 22: Line Control Register (Lcr)
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not being used in the 16C450 mode. They are set to a logic 1 when the FIFOs are enabled in the SC16C2550 mode. Logic 0 or cleared = default condition. - Page 23 5, 6, 7, 8 ⁄ 6, 7, 8 Table 16: LCR[1-0] word length LCR[1] LCR[0] Word length 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 23 of 46...
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Page 24: Modem Control Register (Mcr)
MCR[2] (OP1). OP1A/OP1B are not available as an external signal in the SC16C2550. This bit is instead used in the Loop-back mode only. In the loop-back mode, this bit is used to write the state of the modem RI interface signal. -
Page 25: Line Status Register (Lsr)
Philips Semiconductors Dual UART with 16 bytes of transmit and receive FIFOs and IrDA encoder/decoder 7.7 Line Status Register (LSR) This register provides the status of data transfers between the SC16C2550 and the CPU. Table 18: Line Status Register bits description... -
Page 26: Modem Status Register (Msr)
This register provides the current state of the control interface signals from the modem, or other peripheral device to which the SC16C2550 is connected. Four bits of this register are used to indicate the changed information. These bits are set to a logic 1 whenever a control input from the modem changes state. -
Page 27: Scratchpad Register (Spr)
Whenever any MSR bit 0-3 is set to logic 1, a Modem Status Interrupt will be generated. 7.9 Scratchpad Register (SPR) The SC16C2550 provides a temporary data register to store 8 bits of user information. 7.10 Enhanced Feature Register (EFR) Enhanced features are enabled or disabled using this register. - Page 28 SC16C554 mode. (Normal default condition.) Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1, all enhanced features of the SC16C2550 are enabled and user settings stored during a reset will be restored.
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Page 29: Sc16C2550 External Reset Condition
+ 0.3 −40 °C operating temperature −65 °C storage temperature +150 total power dissipation tot(pack) per package 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 29 of 46... -
Page 30: Static Characteristics
µA clock leakage supply current f = 5 MHz input capacitance Except x = 1 V typical. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 30 of 46... -
Page 31: Dynamic Characteristics
When in both DMA mode 0 and FIFO enable mode, the write cycle delay should be larger than one x , clock cycle. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003... -
Page 32: Timing Diagrams
Fig 7. General write timing. VALID A0–A2 ADDRESS ACTIVE ACTIVE D0–D7 DATA 002aaa110 Fig 8. General read timing. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 32 of 46... - Page 33 CHANGE OF STATE 002aaa111 Fig 9. Modem input/output timing. EXTERNAL CLOCK 002aaa112 Fig 10. External clock timing. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 33 of 46...
- Page 34 6 DATA BITS 7 DATA BITS ACTIVE ACTIVE 16 BAUD RATE CLOCK 002aaa113 Fig 11. Receive timing. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 34 of 46...
- Page 35 REACHES THE TRIGGER LEVEL ACTIVE DATA RXRDY READY ACTIVE 002aaa115 Fig 13. Receive ready timing in FIFO mode. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 35 of 46...
- Page 36 7 DATA BITS ACTIVE TX READY ACTIVE ACTIVE 16 BAUD RATE CLOCK 002aaa116 Fig 14. Transmit timing. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 36 of 46...
- Page 37 BYTE #1 ACTIVE TXRDY TRANSMITTER READY TRANSMITTER NOT READY 002aaa117 Fig 15. Transmit ready timing in non-FIFO mode. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 37 of 46...
- Page 38 BYTE #16 TXRDY FIFO FULL 002aaa118 Fig 16. Transmit ready timing in FIFO mode (DMA mode ‘1’). 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 38 of 46...
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Page 39: Package Outline
ISSUE DATE VERSION PROJECTION JEDEC JEITA 99-12-27 SOT129-1 051G08 MO-015 SC-511-40 03-02-13 Fig 17. DIP40 package outline (SOT129-1). 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 39 of 46... - Page 40 ISSUE DATE VERSION PROJECTION JEDEC JEITA 99-12-27 SOT187-2 112E10 MS-018 EDR-7319 01-11-14 Fig 18. PLCC44 package outline (SOT187-2). 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 40 of 46...
- Page 41 ISSUE DATE VERSION PROJECTION JEDEC JEITA 00-01-19 SOT313-2 136E05 MS-026 03-02-25 Fig 19. LQFP48 package outline (SOT313-2). 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 41 of 46...
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Page 42: Soldering
220 °C (SnPb process) or below 245 °C (Pb-free process) • – for all the BGA and SSOP-T packages 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003 42 of 46... -
Page 43: Wave Soldering
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. 9397 750 11621 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 03 — 19 June 2003... -
Page 44: Package Related Soldering Information
VSSOP For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). -
Page 45: Data Sheet Status
This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. -
Page 46: Table Of Contents
7.10 Enhanced Feature Register (EFR) ..27 7.11 SC16C2550 external reset condition ..29 © Koninklijke Philips Electronics N.V. 2003. Printed in the U.S.A All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.