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4.1 Power
(1) VDD1
This pin is used to detect the power of the target system.
(2) SMVDDn (n = 0, 1)
This pin is used to detect the SMVDDn voltage of the target system.
ON: SMVDDn is supplied from the target system.
OFF: Operates at +5 V.
(3) VDDn (n = 0, 2, 3), AVDD
This pin is used to detect the VDDn voltage of the target system.
ON: VDDn operates at the same voltage as VDDn of the target system.
AVDD is supplied from the target system.
OFF: VDDn operates at +5 V.
AVDD operates at +5 V.
4.2 NMI Signal
The NMI signal from the target system is delayed (0.25 ns (MAX.)) because
it passes through QS3384 before it is input to the I/O chip of the emulator.
Target system
4.3 NMI Signal Mask Function
When using the P00/NMI pin in the port mode, do not mask the NMI signal.
4.4 RESET Signal
The RESET signal from the target system is delayed (7.5 ns (MAX.)) because
it passes through VHC00 and VHC04 before it is input to the I/O chip of the emulator.
Target system
CHAPTER 4 CAUTIONS
Diagram of NMI Signal Flow
NMI
NMI pin
Signal
Target voltage
1
1
1
1
1
2
2
2
2
2
VHC00
RESET
Signal
16
IE-703081-MC-EM1
IO chip
QS3384
IE-703081-MC-EM1
VHC04
EVA CHIP
IE-703081-MC-EM1 User's Manual
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