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Pin No.
Port
1-3
-
(+5V pull-up)
4
AVSS
Ground
5,6
-
(+5V pull-up)
7
AVREF
+5V power supply
8
RXD2
Communication data receive
9
TXD2
Communication data send
10
ASCK2
Not used
11
SI1
Serial data
12
SO1
Serial data
13
/SCK1
Data shift clock
14,15 -
(+5V pull-up)
16
PLL_DO
PLL data
17
PLL_DI
PLL data
18
PLL_CLK
PLL data shift clock
19
PLL_CE
PLL chip enable
20-32 -
(+5V pull-up)
33
VSS
Ground
34-39 -
(+5V pull-up)
40
SD
FM Stereo detection
41-55 -
(+5V pull-up)
56
TC
57
TEST
58
-
(+5V pull-up)
59
RDS.DATA
RDS data
60
RESET
Reset input
61,62 -
(+5V pull-up)
63
RDS.CLK
RDS data shift clock
64-66 -
(+5V pull-up)
67
VSS
Ground
68
VDD
+5V power supply
69
X2
Crystal oscillator terminal
70
X1
Crystal oscillator terminal
71
VPP
(Ground pull-down)
72
XT2
Not used
73
XT1
(Connecting to ground)
74
VDD
+5V power supply
75
AVDD
+5V power supply
76
VSM
S-meter level input
77-80 -
(+5V pull-up)
8. PACKAGE AND IC BLOCK DIAGRAM
Descriptions
PA1 : C5EA00000078
4
Vol
I/O
(V)
-
5.0
-
0
-
5.0
-
5.0
I
5.1
O
5.1
-
-
I
5.1
O
5.1
O
0
-
5.0
I
5.1
O
0
O
5.1
O
0
-
5.0
-
0
-
5.0
I
0
-
5.0
I
5.1
I
0
-
5.0
I
2.8
I
5.1
-
5.0
I
2.6
-
5.0
-
0
-
5.0
-
3.2
-
2.5
-
0
-
-
-
0
-
5.0
-
5.0
I
0.4
-
5.0
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