LG GoldStream LW1100P Manual page 7

Differential Quaternary Phase Shift Keying (DQPSK) for 2Mbps, and Complementary Code Keying
(CCK) for 5.5Mbps and 11Mbps. These implement data rates as shown in Table 3. The major
functional blocks of the transmitter include a network processor interface, DPSK modulator, high rate
modulator, a data scrambler and a spreader, as shown in Figure 7. CCK is essentially a quadra-
phase form of M-ARY Orthogonal Keying. A description of that modulation can be found in Chapter 5
of: "Telecommunications System Engineering", by Lindsey and Simon, Prentis Hall publishing.
The preamble is always transmitted as the DBPSK waveform while the header can be configured to
be either DBPSK, or DQPSK, and data packets can be configured for DBPSK, DQPSK, or CCK. The
preamble is used by the receiver to achieve initial PN synchronization while the header includes the
necessary data fields of the communications protocol to establish the physical layer link. The
transmitter generates the synch ronization preamble and header and knows when to make the
DBPSK to DQPSK or CCK switchover, as required.
Header/Packet Description
-
The HFA3861B is designed to handle packetized Direct Sequence Spread Spectrum (DSSS) data
transmissions. The HFA3861B generates its own preamble and header information. It uses two packet
preamble and header configurations. The first is backwards compatible with the existing IEEE 802.11-
1997 1 and 2Mbps modes and the second is the optional shortened mode which maximizes
throughput at the expense of compatibility with legacy equipment.
In the long preamble mode, the device uses a synchronization preamble of 128 symbols along with a
header that includes four fields. The preamble is all 1's (before entering the scrambler) plus a start
frame delimiter (SFD). The actual transmitted pattern of the preamble is randomized by the scrambler.
The preamble is always transmitted as a DBPSK waveform (1Mbps). The duration of the long
preamble and header is 19?s.
In the short preamble mode, the modem uses a synchronization field of 56 zero symbols along with an
SFD transmitted at 1Mbps. The short header is transmitted at 2Mbps. The synchronization preamble is
all 0's to distinguish it from the long header mode and the short preamble SFD is the time reverse of
the long preamble SFD. The duration of the short preamble and header is 9?s.
Scrambler and Data Encoder Description
-
The modulator has a data scrambler that implements the scrambling algorithm specified in the IEEE
802.11 standard. This scrambler is used for the preamble, header, and data in all modes. The data
scrambler is a self synchronizing circuit. It consists of a 7-bit shift register with feedback from specified
taps of the register. Both transmitter and receiver use the same scrambling algorithm. The scrambler
can be disabled by setting CR32 bit 2 to 1
- Spread Spectrum Modulator Description
The modulator is designed to generate DBPSK, DQPSK, and CCK spread spectrum signals. The
modulator is capable of automatically switching its rate where the preamble is DBPSK modulated,
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