Appendix Aflash.lcf - Motorola Digital dna MSC8101ADS Manual

Table of Contents

Advertisement

If the application in Appendix B runs out of internal SRAM, the following changes must be made:
• LED on and off times modified in the FlashLed function in both case statements. Currently there are
• In the main function, comment out Sinit(). This function initializes the IMMR and disables the
Appendix A flash.lcf
Freescale Semiconductor, Inc.
example wait times for using Flash memory and internal SRAM in the function.
watchdog. CodeWarrior version 1.5 has a problem with this function.
; for linking to Flash memory
.provide _CodeStart,
.provide _ROMStart,
.provide _StackStart, 0x4f000
.provide _TopOfStack, 0x7fe00
; by the C/C++ run-time.
; By default, this serves as the heap
; start address.
; The heap grows downwards.
.provide _SR_Setting, 0xe4000c
; exception mode
; interrupt level 7
; saturation on
; rounding mode: nearest even
.memory 0x20000000, 0x207fffff, "rwx" ; sync dram
.provide _sdram_start, 0x20000000
.memory 0, 0xfffff, "rwx"
.memory 0xff800000, 0xffffffff, "rwx" ; 8MB Flash memory declaration
.reserve _StackStart, _TopOfStack ; Reserve for stack space
.provide FlashBase, 0xff800000
.entry _CodeStart ; this is the value programmed in the Flash boot vector
.org _DataStart
; The following line is used if running code out of internal SRAM
; .segment .data, ".data",".ramsp_0",".default",".bss"
; Notes:
; 1.
.bss is used for uninitialized data
; 2.
S-record generator ignores .bss
.org _ROMStart
.segment .intvec, ".intvec"
.segment .text,".text"
.segment .roinit, ".rom_init"
.segment .rotable, ".init_table"
. Take out the following line if using the debugger and running code
. out of internal SRAM
.segment .data,".data"
For More Information On This Product,
Go to: www.freescale.com
Running LEDblinker from Internal SRAM
0xff840000
; Sets the code start address
0xff840000
; Sets the ROM start address
; Sets the stack start address
; The stack grows upwards.
; The highest address to be used
; The value to set the SR after reset:
; Start execution at interrupt
9

Advertisement

Table of Contents
loading

Table of Contents