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Motorola MVME187 Installation Manual

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MVME187
RISC Single Board Computer
Installation Guide
MVME187IG/D4

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Summary of Contents for Motorola MVME187

  • Page 1 MVME187 RISC Single Board Computer Installation Guide MVME187IG/D4...
  • Page 2 Motorola, Inc. assumes no liability resulting from any omissions in this document, or from the use of the information obtained therein. Motorola reserves the right to revise this document and to make changes from time to time in the content hereof without obligation of Motorola to notify any person of such revision or changes.
  • Page 3 Preface This manual provides a general board level hardware description, hardware preparation and installation instructions, debugger general information, and information about using the debugger. This manual applies to the following MVME187 RISC Single Board Computers: Assembly Item Board Description MVME187...
  • Page 4 Motorola, Inc. assumes no liability for the customer's failure to comply with these requirements. The safety precautions listed below represent warnings of certain dangers of which Motorola is aware. You, as the user of the product, should follow these warnings and all other safety precautions necessary for the safe operation of the equipment in your operating environment.
  • Page 5 CE-marked system will maintain the required EMC/safety performance. The computer programs stored in the Read Only Memory of this device contain material copyrighted by Motorola Inc., 1995, and may be used only under a license such as those contained in MotorolaÕs software licenses. ¨...

  • Page 7: Table Of Contents

    Control and Status Bit DeÞnitions 1-4 True/False Bit State DeÞnitions 1-4 Bit Value Descriptions 1-4 Related Documentation 1-5 Document Set for MVME187-0xx Board 1-5 Additional Manuals for this Board 1-6 Other Applicable Motorola Publications 1-6 Non-Motorola Peripheral Controllers Publications Bundle 1-7...
  • Page 8 MCECC Memory Controller ASIC 2-10 Functional Description 2-10 Front Panel Switches and LEDs 2-11 Data Bus Structure 2-12 Local Bus Arbitration 2-12 M88000 MPU 2-12 EPROM 2-13 Programmable EPROM Features 2-13 Static RAM 2-13 Optional SRAM Battery Backup 2-14 Onboard DRAM 2-15 Stacking Mezzanines 2-16 DRAM Programming Considerations 2-16 Battery Backed Up RAM and Clock 2-17...
  • Page 9 Serial Port 4 Clock Configuration Select Headers J7 and J8 3-11 Preparing the MVME187 for Installation 3-14 Preparing the System Chassis 3-15 Installing the Hardware 3-16 Installing the MVME187 in the Chassis 3-16 Transition Modules and Adapter Boards Overview 3-17 Equipment Connections 3-19 Installing Transition Modules and Adapter Boards 3-20...
  • Page 10 Booting and Restarting 187Bug 4-5 Starting Up 187Bug 4-6 Autoboot 4-6 Autoboot Sequence 4-6 ROMboot 4-7 ROMboot Sequence 4-7 Network Boot 4-8 Network Boot Sequence 4-8 Restarting the System 4-9 Reset 4-10 Abort 4-10 Break 4-11 SYSFAIL* Assertion/Negation 4-12 MPU Clock Speed Calculation 4-12 Disk I/O Support 4-13 Disk Support Facilities 4-13 Parameter Tables 4-13...
  • Page 11 MPCR Status Codes 4-22 Multiprocessor Address Register (MPAR) 4-22 MPCR Powerup Sequence 4-22 Global Control and Status Register (GCSR) Method 4-24 Diagnostic Facilities 4-25 187Bug Diagnostic Test Groups 4-27 This Chapter Covers 5-1 Entering Debugger Command Lines 5-1 Terminal Input/Output Control 5-1 Debugger Command Syntax 5-3 Syntactic Variables 5-4 Expression as a Parameter 5-4...
  • Page 12 Signal Adaptations E-4 Sample ConÞgurations E-4 Proper Grounding E-7...
  • Page 13 List of Figures MVME187 General Block Diagram 2-7 MVME187 Switches, Headers, Connectors, Fuses, and LEDs 3-6 Typical Internal SCSI and Serial Port Connections 3-18 Using MVME712A/AM and MVME712B 3-22 Typical Transition Module Peripheral Port Connectors 3-23...
  • Page 14 List of Tables MVME187 General SpeciÞcations 2-6 Bus Transfers 2-9 Front Panel Switches 2-11 Front Panel LEDs 2-11 Local Bus Memory Map 2-25 Local I/O Devices Memory Map 2-26 Startup Overview 3-2 J1 Bit Descriptions 3-9 Factory Settings for J1 General Purpose Readable Jumpers 3-9...

  • Page 15: This Chapter Covers

    Other publications relevant to the MVME187 About this Manual This manual supports the setup, installation, and debugging of the RISC-based MVME187 Single Board Computer; a high- performance engine for VMEbus-based low- and mid-range OEM and integrated systems, embedded controllers, and other single- board computer applications.

  • Page 16: Terminology, Conventions, And Deþnitions Used In This Manual

    Introduction to the MVME187 Installation Guide Terminology, Conventions, and Definitions Used in this Manual Data and Address Parameter Numeric Formats Throughout this manual, a character identifying the numeric format precedes data and address parameters as follows: dollar speciÞes a hexadecimal character percent speciÞes a binary number...

  • Page 17: Assertion And Negation Conventions

    Big-Endian Byte Ordering This manual assumes that the MPU on the MVME187 always programs the CMMUs with big-endian byte ordering, as shown below. Any attempt to use little-endian byte ordering will immediately render the MVME187Bug debugger unusable.

  • Page 18: Control And Status Bit Deþnitions

    Introduction to the MVME187 Installation Guide Control and Status Bit Definitions The terms control bit and status bit are used extensively in this document to describe certain bits in registers. Term Describes The bit can be set and cleared under software...

  • Page 19: Related Documentation

    Related Documentation Related Documentation The MVME187 ships with a start-up installation guide (MVME187IG/D, the document you are presently reading) which includes installation instructions, jumper configuration information, memory maps, debugger/monitor commands, and any other information needed for start-up of the board.

  • Page 20: Additional Manuals For This Board

    MVME187. Other Applicable Motorola Publications The following publications are applicable to the MVME187 and may provide additional helpful information. They may be purchased through your local Motorola sales office. Motorola...

  • Page 21: Non-Motorola Peripheral Controllers Publications Bundle

    Non-Motorola Peripheral Controllers Publications Bundle For your convenience, we have collected user's manuals for each of the peripheral controllers used on the MVME187 from the suppliers. This bundle, which can be ordered as part number 68- 1X7DS, includes the following manuals:...
  • Page 22 Introduction to the MVME187 Installation Guide Part Number Description MK48T08/18B SGS-THOMSON MK48T08 Time Clock/NVRAM Data Sheet MC68230/D MC68230 Parallel Interface Timer (PI/T) Data Sheet SBCCOMPS/L Customer Letter for Component Alternatives...

  • Page 23: Applicable Non-Motorola Publications

    Related Documentation Applicable Non-Motorola Publications The following non-Motorola publications are also available from the sources indicated. Document Title Source Versatile Backplane Bus: VMEbus The Institute of Electrical and ANSI/IEEE Std 1014-1987 Electronics Engineers, Inc. (VMEbus SpeciÞcation) (This is also 345 East 47th St.
  • Page 24 Introduction to the MVME187 Installation Guide 1-10...

  • Page 25: This Chapter Covers

    Memory maps General Description The MVME187 is a high functionality VMEbus RISC single board computer designed around the M88000 chip set. It features: Onboard memory expansion mezzanine module with 4, 8, 16, 32, 64 or 128MB of onboard DRAM...

  • Page 26: Onboard Memory Mezzanine Module

    Board Level Hardware Description Onboard Memory Mezzanine Module The MVME187 onboard DRAM mezzanine boards are available in different sizes and with programmable parity protection or Error Checking and Correction (ECC) protection. The main board and a single mezzanine board together take one slot.

  • Page 27: Serial Ports

    A functional description of the Parallel Port Interface starts on page 2-20. Ethernet Transceiver Interface The Ethernet transceiver interface is located on the MVME187, and the industry standard connector is located on the MVME712X transition module. A functional description of the Ethernet Interface starts on page...

  • Page 28: 187Bug Firmware

    Board Level Hardware Description 187Bug Firmware The MVME187Bug debug monitor firmware (187Bug) is provided in two of the four EPROM sockets on the MVME187. It provides: Over 50 debug commands Up/down load commands Disk bootstrap load commands A full set of onboard diagnostics...
  • Page 29 Features switches RESET ABORT Four 32-bit tick timers for periodic interrupts Watchdog timer Eight software interrupts Ð SCSI Bus interface with DMA Ð Four serial ports with EIA-232-D buffers with DMA Ð Centronics printer port Ð Ethernet transceiver interface with DMA VMEbus interface Ð...

  • Page 30: Speciþcations

    Board Level Hardware Description Specifications Table 2-1. MVME187 General Specifications Characteristics SpeciÞcations Power requirements +5 Vdc (+/-5%) 3.5 A (typical), 4.5 A (maximum) (with all four EPROM sockets (at 25 MHz, with 32MB parity DRAM) populated and excluding 5.0 A (typical), 6.5 A (maximum)

  • Page 31: Board Level Overview

    P2 rows A and C provide the connection to the SCSI bus, serial ports, Ethernet, and printer. Adapters I/O on the MVME187 is connected to the VMEbus P2 connector. The main board is connected to the transition modules through a P2 adapter board and cables.

  • Page 32: Transition Modules

    Adapter Board User's Manual. ASICs The MVME187 board features several Application Specific Integrated Circuits (ASICs) including: VMEchip2 PCCchip2 MEMC040 MCECC All programmable registers in the MVME187 that reside in ASICs are covered in the Single Board Computers Programmer's Reference Guide.

  • Page 33: Vmechip2 Asic

    Board Level Overview VMEchip2 ASIC Provides the VMEbus interface. The VMEchip2 includes: Two tick timers Watchdog timer Programmable map decoders for the master and slave interfaces, and a VMEbus to/from local bus DMA controller VMEbus to/from local bus non-DMA programmed access interface VMEbus interrupter VMEbus system controller...

  • Page 34: Memc040 Memory Controller Asic

    MCECC Memory Controller ASIC The MCECC memory controller ASIC provides the programmable interface for the ECC-protected DRAM mezzanine board. Functional Description The major functional blocks of the MVME187 covered in this section are: Front panel switches and LED indicators Data bus structure...

  • Page 35: Front Panel Switches And Leds

    STAT LED lights when the local bus TIP* signal line is low. This Green indicates one of the local bus masters is executing a local bus cycle. LED lights when the MVME187 is the VMEbus system SCON Green SCON controller.

  • Page 36: Data Bus Structure

    M88000 MPU The MVME187 is based on the M88000 family and uses one MC88100 MPU and two MC88200 or MC88204 CMMUs. One CMMU is used for the data cache and one is used for the instruction cache.

  • Page 37: Eprom

    Map decoder Access time When accessible at address 0 Static RAM The MVME187 includes 128KB of 32-bit wide 100 ns static RAM (SRAM), which: Supports 8-, 16-, and 32-bit wide accesses. Allows debugger operation and execution of limited diagnostics without the DRAM mezzanine.

  • Page 38: Optional Sram Battery Backup

    Board Level Hardware Description Optional SRAM Battery Backup SRAM battery backup is optionally available on the MVME187, but only as a factory build and only by special request. (Contact your local Motorola sales office for details). The battery backup function,...

  • Page 39: Onboard Dram

    Note the battery polarity and press the battery into the socket. Onboard DRAM The MVME187 onboard DRAM is located on a mezzanine board. The mezzanine boards are available in different sizes and with parity protection or ECC protection. Parity mezzanines are only supported on 25 MHz main Note boards.

  • Page 40: Stacking Mezzanines

    4, 8, 16, 32, 64, or 128 MB with ECC protection Stacking Mezzanines Two mezzanine boards may be stacked to provide up to 256MB of onboard RAM (ECC). The MVME187 board and a single mezzanine board together take one slot. The stacked configuration requires two VMEboard slots. DRAM Programming Considerations...

  • Page 41: Battery Backed Up Ram And Clock

    Functional Description Battery Backed Up RAM and Clock The MK48T08 RAM and clock chip is a 28-pin package that provides A time-of-day clock An oscillator A crystal Power fail detection Memory write protection 8KB of RAM A battery The clock provides Seconds, minutes, hours, day, date, month, and year in BCD 24-hour format Automatic corrections for 28-, 29- (leap year), and 30-day...

  • Page 42: Vmebus Interface

    The configuration headers are located on the MVME187 and the MVME712X transition board. The I/O on the MVME187 is connected to the VMEbus P2 connector. The MVME712X transition module is connected to the MVME187 through cables and a P2 adapter board.
  • Page 43 Functional Description All four serial ports use EIA-232-D drivers and receivers located on the MVME187, and all the signal lines are routed to the I/O connector. Serial port 1 is a minimum function asynchronous port. It uses RXD, CTS, TXD, and RTS.

  • Page 44: Parallel Port Interface

    Board Level Hardware Description Parallel Port Interface The PCCchip2 provides an 8-bit bidirectional parallel port. This port may be used as a Centronics-compatible parallel printer port or as a general parallel I/O port. All eight bits of the port must be either inputs or outputs (no individual bit selection).

  • Page 45: Ethernet Interface

    Every MVME187 is assigned an Ethernet Station Address. The address is $08003E2xxxxx where xxxxx is the unique 5-nibble number assigned to the board (i.e., every MVME187 has a different value for xxxxx). Each module has the Ethernet Station Address displayed on a label attached to the VMEbus P2 connector.

  • Page 46: Scsi Interface

    Refer to the 82596CA user's guide for detailed programming information. SCSI Interface The MVME187 provides for mass storage subsystems through the industry-standard SCSI bus. These subsystems may include hard and floppy disk drives, streaming tape drives, and other mass storage devices.

  • Page 47: Local Resources

    Local Bus Timeout The MVME187 provides a timeout function for the local bus. When the timer is enabled and a local bus access times out, a Transfer Error Acknowledge (TEA) signal is sent to the local bus master. The timeout value is selectable by software for 8 µsec, 64 µsec, 256 µsec,...

  • Page 48: Memory Maps

    The normal address range is defined by the Transfer Type (TT) signals on the local bus. On the MVME187, Transfer Types 0 and 1 define the normal address range. Table 2-5 on page 2-25 is the entire map from $00000000 to $FFFFFFFF.

  • Page 49: Local Bus Memory Map

    Memory Maps Table 2-5. Local Bus Memory Map Software Address Devices Accessed Port Size Size Cache Notes Range Inhibit $00000000 - User programmable DRAMSIZE 1, 2 DRAMSIZE (onboard DRAM) DRAMSIZE User programmable D32/D16 3, 4 - $FF7FFFFF (VMEbus) $FF800000 - $FFBFFFFF $FFC00000 - Reserved...

  • Page 50: Local I/O Devices Memory Map

    Board Level Hardware Description The following table focuses on the Local I/O Devices portion of the local bus Main Memory Map. Table 2-6. Local I/O Devices Memory Map Address Range Devices Accessed Port Size Size Notes $FFF00000 - $FFF3FFFF Reserved 256KB $FFF40000 - $FFF400FF VMEchip2 (LCSR)
  • Page 51 Memory Maps Table 2-6. Local I/O Devices Memory Map (Continued) Address Range Devices Accessed Port Size Size Notes $FFFE000B IACK LEVEL 2 1 byte $FFFE000F IACK LEVEL 3 1 byte $FFFE0013 IACK LEVEL 4 1 byte $FFFE0017 IACK LEVEL 5 1 byte $FFFE001B IACK LEVEL 6...

  • Page 52: Vmebus Memory Map

    The VMEchip2 includes a user-programmable map decoder for the VMEbus to local bus interface. The map decoder allows you to program the starting and ending address and the modifiers the MVME187 responds to. VMEbus Short I/O Memory Map The VMEchip2 includes a user-programmable map decoder for the GCSR.

  • Page 53: This Chapter Covers

    This chapter provides instructions on: Unpacking the equipment Preparing the hardware Installing the MVME187 RISC Single Board Computer Note that hardware preparation instructions for the MVME712X transition module are provided in separate userÕs manuals for each model. Refer to the userÕs manual you received with your MVME712X.

  • Page 54: Overview Of Startup Procedure

    Disconnect AC power cable. received with Remove chassis cover. your chassis Remove Þller panels from card slots. Install your MVME187 in the chassis. Installing the 3-16 Hardware Remove IACK and BG jumpers from backplane. Slide the module into the chassis and...
  • Page 55 Overview of Startup Procedure Table 3-1. Startup Overview (Continued) Stage What you will need to do... Refer to... page... Install adapter boards and transition modules. Transition 3-17 Modules and Adapter Boards Overview Installing 3-20 Transition Modules and Adapter Boards Set jumpers on the transition module(s). The userÕs manual you received with your Connect and install the MVME712X...
  • Page 56 Note that the debugger prompt appears. 3-25 Powering Up the System Starting Up 187Bug You may also wish to obtain the Debugging Package for Motorola 88K RISC CPUs UserÕs Manual and the 187Bug Diagnostics UserÕs Manual Examine and/or change environmental Examining 3-25 parameters.

  • Page 57: Preparing The Hardware

    MVME187, certain option modifications may be necessary before installation. The location of the switches, jumper headers, connectors, and LED indicators on the MVME187 is illustrated in Figure 3-1. Option Modification The MVME187 has provisions for option modification via: Software control for most options...
  • Page 58 Hardware Preparation and Installation MVME FAIL STAT RUN SCON +12V SCSI VME ABORT RESET Figure 3-1. MVME187 Switches, Headers, Connectors, Fuses, and LEDs...

  • Page 59: Checking The 187Bug Eproms

    There are two spare EPROM sockets, XU3 and XU4, available to carry user-programmed EPROMs. Jumper Settings The MVME187 has been factory tested and is shipped with the factory jumper settings described on the following pages. The MVME187 operates with its required and factory-installed Debug...

  • Page 60: Optional Jumper Settings

    TRXC4 and RTXC4 clock signals. General Purpose Software Readable Header J1 Each MVME187 may be configured with readable jumpers. They can be read as a register (at $FFF40088) in the VMEchip2 LCSR. The bit values are read as a one when the jumper is off, and as a zero when the jumper is on Reserved/DeÞned Bits...
  • Page 61 Preparing the Hardware Table 3-2. J1 Bit Descriptions J1 Pins Description Bit #0 (GPI0) When this bit is a one (high), it instructs the debugger to use local Static RAM for its work page (i.e., variables, stack, vector tables, etc.). This bit will be high when jumper is removed. Bit #1 (GPI1) When this bit is a one (high), it instructs the debugger to use the default setup/operation parameters in ROM versus the...

  • Page 62: System Controller Header J2

    Hardware Preparation and Installation System Controller Header J2 The MVME187 can be VMEbus system controller. The system controller function is enabled by installing a jumper on header J2 (see Table 3-4). When the MVME187 is system controller, the SCON LED is turned on.

  • Page 63: Optional Sram Backup Power Source Select Header J6

    Serial Port 4 Clock Configuration Select Headers J7 and J8 Serial port 4 can be configured to use clock signals provided by the TRXC4 and RTXC4 signal lines. Headers J7 and J8 on the MVME187 configure serial port 4 to drive or receive TRXC4 and RTXC4, respectively (see Table 3-6).

  • Page 64: Settings For Optional J6 Sram Backup Power Source Select Header

    Hardware Preparation and Installation Table 3-5. Settings for Optional J6 SRAM Backup Power Source Select Header Header Header ConÞguration Jumpers Number Description Primary source VMEbus +5V STBY Secondary source VMEbus +5V STBY (Factory conÞguration) Primary source optional battery Secondary source optional battery SRAM backup power source...

  • Page 65: Select Headers

    Preparing the Hardware Table 3-6. Settings for J7 and J8 Serial Port 4 Clock Configuration Select Headers Header Header ConÞguration Jumpers Number Description Receive TRXC4 (Factory conÞguration) Drive TRXC4 Serial Port 4 clock conÞguration Receive RTXC4 select headers (Factory conÞguration) Drive RTXC4 3-13...

  • Page 66: Preparing The Mvme187 For Installation

    Hardware Preparation and Installation Preparing the MVME187 for Installation Refer to the setup procedures in the manuals for your particular chassis or system for additional details concerning the installation of the MVME187 into a VME chassis. Table 3-7. MVME187 Preparation Procedure Step Action...

  • Page 67: Preparing The System Chassis

    Preparing the Hardware Preparing the System Chassis Now that the MVME187 module is ready for installation, prepare the system chassis and determine slot assignments (for peripherals, transition modules, etc.) as follows: Inserting or removing modules while power is applied could result in damage to module components.

  • Page 68: Installing The Hardware

    SCSI drives, and serial or parallel printers Installing the MVME187 in the Chassis Note that if the MVME187 is to be used as system controller, it must installed in the left-most card slot (slot 1), otherwise it may be installed in any unused double-height card slot.

  • Page 69: Transition Modules And Adapter Boards Overview

    MVME712X transition modules provide configuration headers and industry-standard connectors for internal and external I/O devices. The I/O on the MVME187 is connected to the VMEbus P2 connector. The MVME712X transition module is connected to the MVME187 through cables and a P2 adapter board as shown Figure 3-2 on page 3-18.
  • Page 70 Hardware Preparation and Installation MVME712X TERMINATOR MVME187 LC P2 ADAPTER J2, P2, OR J11 ENCLOSURE BOUNDARY 1859 9609 Figure 3-2. Typical Internal SCSI and Serial Port Connections 3-18...

  • Page 71: Equipment Connections

    Installing the Hardware Equipment Connections Some connection diagrams are in the Single Board Computer Programmer's Reference Guide. The MVME712X transition modules and P2 adapter boards connect peripheral equipment to the MVME187 as shown in Table 3-10. Table 3-10. Peripheral Connections Equipment Type Connect Through...

  • Page 72: Installing Transition Modules And Adapter Boards

    SCSI devices. Connecting Peripherals The MVME187 mates with (optional) terminals or other peripherals at the EIA-232-D serial ports (marked SERIAL PORTS 1, 2, 3, and 4 on the MVME712X transition module), parallel port, SCSI ports, and LAN Ethernet port, as shown in Figure 3-3 on page 3-22.

  • Page 73: Peripheral Connection Procedures

    EIA-232-D port connectors with the appropriate cables and conÞguration. After power-up, these ports can be reconÞgured by programming the MVME187 CD2401 Serial Controller Chip (SCC), or by using the 187Bug PF command. Set up the device serial ports as described in Step ConÞguring a Port under...
  • Page 74 XON/XOFF handshaking is enabled. Refer to Configuring a Port under the PF (Port Format) command in the Debugging Package for 88K RISC CPUs UserÕs Manual. MVME712B MVME712X MVME187 P2 ADAPTER ENCLOSURE BOUNDARY Figure 3-3. Using MVME712A/AM and MVME712B 3-22...
  • Page 75 Installing the Hardware MVME 712A/12/13 MVME 712B To J10 on Transition Module MVME 712A MVME (MVME712M 712B similar) (if used) Optional Modem Port To J2 on Adapter Board Figure 3-4. Typical Transition Module Peripheral Port Connectors 3-23...

  • Page 76: Completing The Installation

    Hardware Preparation and Installation Completing the Installation Table 3-13. Installation Completion Procedure Step Action... Reassemble the chassis. Reconnect the AC power. Starting the System After completing the preparation and installation procedures, you are ready to start up your system. Table 3-14. System Startup Overview Stage What you will need to do...

  • Page 77: Powering Up The System

    Installing the Hardware Powering Up the System The following table shows what takes place when you turn equipment power ON (depending on whether 187Bug is in Board Mode or in System Mode): If 187Bug is in... Board Mode 187Bug executes some self-checks and displays the debugger prompt 187-Bug>...

  • Page 78: Programming The Pccchip2 And Vmechip2

    Hardware Preparation and Installation Table 3-15. RTC Initialization Procedure Step Action Board Mode System Mode Allow 187Bug to boot up normally. Stop the auto-boot sequence by pressing the <BREAK> key. (If the system has already started and failed a conÞdence test in system mode, you should be in the debugger menu).

  • Page 79: System Considerations

    System Considerations Backplane Power Connections The MVME187 needs to draw power from both P1 and P2 of the VMEbus backplane. P2 is also used for the upper 16 bits of data for 32-bit transfers, and for the upper 8 address lines for extended addressing mode.

  • Page 80: Multiple Module Cage Configuration

    The MVME187 provides +12 Vdc power to the Ethernet LAN transceiver interface through a 1-amp fuse (F2) located on the MVME187. The +12V LED lights when +12 Vdc is available. The fuse is socketed and is located adjacent to diode CR1 near connector P1.

  • Page 81: Scsi Bus Termination

    System Considerations SCSI Bus Termination The MVME187 provides SCSI terminator power through a 1- amp fuse (F1) located on the P2 adapter board. The fuse is socketed. If the fuse is blown, the SCSI devices may not operate or may function erratically.
  • Page 82 Hardware Preparation and Installation 3-30...

  • Page 83: This Chapter Covers

    The M88000 firmware family provides a high degree of functionality and user friendliness, and yet stresses portability and ease of maintenance. This member of the M88000 firmware family is implemented on the MVME187 RISC Single Board Computer, and is known as the MVME187Bug, or just 187Bug.

  • Page 84: Description Of 187Bug

    Debugger General Information Description of 187Bug The 187Bug package is a powerful evaluation and debugging tool for systems built around the MVME187 RISC-based microcomputers. 187Bug consists of three parts: The ÒdebuggerÓ or Ò187BugÒ; a command-driven user- interactive software debugger, described in Chapter 5...

  • Page 85: Debugger Or Diagnostic Directories

    Introduction to MVME187Bug Debugger or Diagnostic Directories When using 187Bug, you operate out of either the debugger directory or the diagnostic directory. With the If you are in... You have available... prompt... The debugger directory All of the debugger 187-Bug> commands The diagnostic directory All of the diagnostic...

  • Page 86: Comparison With M68000-Based Firmware

    Debugger General Information Comparison with M68000-Based Firmware If you have used one or more of Motorola's other debugging packages, you will find the RISC 187Bug very similar, after making due allowances for the architectural differences between the M68000 and M88000 CPU architectures. These differences are...

  • Page 87: Memory Requirements

    187Bug stack and static variable space and the rest is reserved as user space. Whenever the MVME187 is reset, the target IP is initialized to the address corresponding to the beginning of the user space, and the target stack pointers are initialized to addresses within the user space, with the target Pseudo Stack Pointer (R31) set to the top of the user space.

  • Page 88: Starting Up 187Bug

    Debugger General Information Starting Up 187Bug 1. Verify that the MVME187 is properly installed and operating as described in Table 3-1 on page 3-2. 2. Power up the system. 187Bug executes some self-checks and displays the debugger prompt (if 187Bug is in 187-Bug>...

  • Page 89: Romboot

    Booting and Restarting 187Bug 4. Following this message there is a delay to allow you an opportunity to abort the Autoboot process if you wish. To gain control without Autoboot, you can press the BREAK or the software switches. ABORT RESET 5.

  • Page 90: Network Boot

    Your routine must pass a checksum test, which ensures that this routine was really intended to receive control at powerup. For complete details on how to use ROMboot, refer to the Debugging Package for Motorola 88K RISC CPUs User's Manual. Network Boot Network Auto Boot is a software routine contained in the 187Bug EPROMs that provides a mechanism for booting an operating system using a network (local Ethernet interface) as the boot device.

  • Page 91: Restarting The System

    Booting and Restarting 187Bug 3. At powerup, Network Boot is enabled, and providing the drive and controller numbers encountered are valid, the following message is displayed on the system console: "Network Boot in progress... To abort hit <BREAK>" Following this message there is a delay to allow you to abort the Network Boot process if you wish.

  • Page 92: Reset

    COLD and WARM reset modes are available. By default, 187Bug is in COLD mode. During COLD reset: 1. A total system initialization takes place, as if the MVME187 had just been powered up. 2. All static variables (including disk device and controller parameters) are restored to their default states.

  • Page 93: Break

    Booting and Restarting 187Bug Whenever abort is invoked while running target code (a user program), a ÒsnapshotÓ of the processor state is captured and stored in the target registers. For this reason, abort is most appropriate when terminating a user program that is being debugged.

  • Page 94: Sysfail* Assertion/Negation

    Debugger General Information Break Sequence 1. Removes any breakpoints in your code and keeps the breakpoint table intact. 2. Takes a snapshot of the machine state if the function was entered using SYSCALL. This machine state is then accessible to you for diagnostic purposes. SYSFAIL* Assertion/Negation Upon a reset/powerup condition the debugger asserts the VMEbus SYSFAIL* line (refer to the VMEbus specification).

  • Page 95: Disk I/O Support

    Disk I/O Support Disk I/O Support 187Bug can initiate disk input/output by communicating with intelligent disk controller modules over the VMEbus. This section covers: Blocks Versus Sectors Device Probe Function Disk I/O via 187Bug Commands Disk I/O via 187Bug System Calls Default 187Bug Controller and Device Parameters Disk I/O Error Codes Disk Support Facilities...

  • Page 96: Blocks Versus Sectors

    Debugger General Information Blocks Versus Sectors The logical block defines the unit of information for disk devices. A disk is viewed by 187Bug as a storage area divided into logical blocks. By default, the logical block size is set to 256 bytes for every block device in the system.

  • Page 97: Disk I/O Via 187Bug Commands

    These following 187Bug commands are provided for disk I/O. Detailed instructions for their use are found in the Debugging Package for Motorola 88K RISC CPUs User's Manual. When a command is issued to a particular controller LUN and device LUN, these LUNs are remembered by 187Bug so that the next disk command defaults to use the same controller and device.

  • Page 98: Bh (Bootstrap And Halt)

    Refer to the Debugging Package for Motorola 88K RISC CPUs User's Manual for information on using these and other system calls. Controller Command Packets...

  • Page 99: Default 187Bug Controller And Device Parameters

    Refer to the system call descriptions in the Debugging Package for Motorola 88K RISC CPUs User's Manual for details on the format and construction of these standardized "user" packets. The packets which a controller module expects to be given vary from controller to controller.

  • Page 100: Disk I/O Error Codes

    Debugger General Information There are three ways to change the parameter tables: When you invoke one of Change Using... If a cold-start reset occurs... these commands... status is... Command The conÞguration area of Temporary The default parameter BO or BH the disk is read and the information is written back parameters...

  • Page 101: Network I/O Support

    Network I/O Support Network I/O Support The Network Boot Firmware provides the capability to boot the CPU through the ROM debugger using a network (local Ethernet interface) as the boot device. The booting process is executed in two distinct phases. The first phase allows the diskless remote node to discover its network identify and the name of the file to be booted.

  • Page 102: Rarp/Arp Protocol Modules

    Debugger General Information RARP/ARP Protocol Modules The Reverse Address Resolution Protocol (RARP) basically consists of an identity-less node broadcasting a "whoami" packet onto the Ethernet, and waiting for an answer. The RARP server fills an Ethernet reply packet up with the target's Internet Address and sends it.

  • Page 103: Network I/O Error Codes

    187Bug returns an error code if an attempted network operation is unsuccessful. Multiprocessor Support The MVME187 dual-port RAM feature makes the shared RAM available to remote processors as well as to the local processor. This can be done by either of the following two methods:...

  • Page 104: Mpcr Status Codes

    Debugger General Information MPCR Status Codes The status codes stored in the MPCR are of two types: Status returned (from 187Bug) Command set by the bus master (job requested by some processor) The status codes that may be returned from 187Bug are: (HEX 00) Wait.
  • Page 105 Multiprocessor Support 3. As the initialization proceeds, the execution path comes to the "prompt" routine. Before sending the prompt, this routine places an R in the MPCR to indicate that initialization is complete. Then the prompt is sent. Ð If no terminal is connected to the port, the MPCR is still polled to see whether an external processor requires control to be passed to the dual-port RAM.

  • Page 106: Global Control And Status Register (Gcsr) Method

    2. The remote processor then sets bit 8 (SIG0) of the VMEchip2 LM/SIG register. 3. This causes the MVME187 to install breakpoints and begin execution. The result is identical to the MPCR method (with status code B) described in the previous section.

  • Page 107: Diagnostic Facilities

    Included in the 187Bug package is a complete set of hardware diagnostics intended for testing and troubleshooting of the MVME187. These diagnostics are completely described in the MVME187Bug Debugging Package User's Manual. In order to use the diagnostics, you must switch directories to the diagnostic directory.

  • Page 108: Diagnostic Utilities

    Debugger General Information Table 4-1. Diagnostic Monitor Commands/Prefixes Command/ Description PreÞx Non-Verbose Mode Switch Directories Stop on Error Mode Selftest Clear (Zero) Error Counters Zero Pass Count Table 4-2. Diagnostic Utilities Command Description Write loop enable Read loop enable 4-26...

  • Page 109: 187Bug Diagnostic Test Groups

    Diagnostic Facilities 187Bug Diagnostic Test Groups Refer to the MVME187Bug Debugging Package User's Manual for complete descriptions of the diagnostic routines available and instructions on how to invoke them. Note that some diagnostics depend on restart defaults that are set up only in a particular restart mode.
  • Page 110 Debugger General Information 4-28...

  • Page 111: This Chapter Covers

    Using the 187Bug Debugger This Chapter Covers Entering debugger command lines Entering and debugging programs Calling system utilities from user programs Preserving the debugger operating environment Floating point support The 187Bug debugger command set Entering Debugger Command Lines 187Bug is command-driven and performs its various operations in response to user commands entered at the keyboard.
  • Page 112 Using the 187Bug Debugger The presence of the upward caret ( ^ ) before a Note character indicates that the Control (CTRL) key must be held down while striking the character key. (cancel line) The cursor is backspaced to the beginning of the line. (backspace) The cursor is moved back one position.

  • Page 113: Debugger Command Syntax

    Entering Debugger Command Lines Ò.RETURNÓ. Debugger Command Syntax In general, a debugger command is made up of the following parts: The command identifier (i.e., MD or md for the Memory Display command). Note that either upper- or lowercase is allowed. A port number if the command is set up to work with more than one port.

  • Page 114: Syntactic Variables

    Using the 187Bug Debugger Syntactic Variables The syntactic variables shown below are encountered in the command descriptions on the following pages. In addition, other syntactic variables may be used and are defined in the particular command description in which they occur. Delimiter;...

  • Page 115: Address As A Parameter

    Entering Debugger Command Lines A numeric value may also be expressed as a string literal of up to four characters. The string literal must begin and end with the single quote mark ('). The numeric value is interpreted as the concatenation of the ASCII values of the characters.

  • Page 116: Address Formats

    Using the 187Bug Debugger Address Formats Addresses are entered as a hexadecimal number, e.g., 20000 would correspond to address $00020000. The address, or starting address of a range, can be qualified by a suffix of the form ^S, ^s, ^U, or ^u where S or s defines Supervisor address space, and U or u defines user address space.

  • Page 117: Offset Registers

    MVME187 P2 connector). Sometimes known as the Òconsole portÓ, it is used for interactive user input/output by default. 2. MVME187 EIA-232-D (Terminal Port 1 or 01) (PORT 2 on the MVME187 P2 connector). Sometimes known as the Òhost portÓ, this is the default for downloading, uploading,...

  • Page 118: Entering And Debugging Programs

    1. Enter the program one source line at a time. 2. After each source line is entered, it is assembled and the object code is loaded to memory. Refer to the Debugging Package for Motorola 88K RISC CPUs User's Manual for complete details of the 187Bug Assembler/Disassembler.

  • Page 119: Read The Program From Disk

    MVME187 port 1. (Hardware configuration details are provided in Connecting Peripherals on page 3-20.) The file is downloaded from the host to MVME187 memory by the Load (LO) command. Read the Program from Disk Another way to enter a program is by reading the program from disk, using one of the disk commands (BO, BH, IOP).

  • Page 120: Preserving The Debugger Operating Environment

    Hardware functions Exception vectors used by 187Bug CPU/MPU registers 187Bug uses certain of the MVME187 onboard resources and may also use offboard system memory to contain temporary variables, exception vectors, etc. If you disturb resources upon which 187Bug depends, then the debugger may function unreliably or not at all.

  • Page 121: Hardware Functions

    Note Although the 187Bug does not explicitly manage the MC88200 or MC88204 CMMUs, hardware prevents caching of I/O space on the MVME187, i.e., $FFFXXXXX. Furthermore, the code cache must not be operative for code pages which are being traced or breakpointed.
  • Page 122 Using the 187Bug Debugger Valid data types that can be used when modifying a floating point data register or a floating point memory location: Integer Data Types Byte 1234 Half-Word 12345678 Word Floating Point Data Types 1_FF_7FFFFF Single Precision Real Format 1_7FF_FFFFFFFFFFFFF Double Precision Real Format -3.12345678901234501_E+123...

  • Page 123: Single Precision Real

    Floating Point Support Single Precision Real This format would appear in memory as: 1-bit sign Þeld (1 binary digit) 8-bit biased exponent Þeld (2 hex digits. Bias = $7F) 23-bit fraction Þeld (6 hex digits) A single precision number takes 4 bytes in memory. Double Precision Real This format would appear in memory as: 1-bit sign Þeld...

  • Page 124: Scientiþc Notation

    Using the 187Bug Debugger Scientific Notation This format provides a convenient way to enter and display a floating point decimal number. Internally, the number is assembled into a packed decimal number and then converted into a number of the specified data type. Entering data in this format requires the following fields: An optional sign bit (+ or -).

  • Page 125: The 187Bug Debugger Command Set

    The 187Bug Debugger Command Set The 187Bug Debugger Command Set The 187Bug debugger commands are summarized in Table 5-1. The command syntax is shown using the symbols explained earlier in this chapter. The CNFG and ENV commands are explained in Appendix A.
  • Page 126 Using the 187Bug Debugger Table 5-1. Debugger Commands (Continued) Command Title Command Line Syntax Mnemonic CNFG ConÞgure Board CNFG [; [I] [M]] Information Block Checksum CS range [; B|H|W] Data Conversion DC exp | addr [; [B] [O] [A]] DMA Block of Memory DMA range del addr del vdir del am del blk [;...
  • Page 127 The 187Bug Debugger Command Set Table 5-1. Debugger Commands (Continued) Command Title Command Line Syntax Mnemonic NOMAL Disable Macro Expansion NOMAL Listing Save Macros MAW [controller LUN] [del [device LUN] [del block #]] Load Macros MAR [controller LUN] [del [device LUN] [del block #]] Memory Display MD[S] addr [:count |del addr]...
  • Page 128 Using the 187Bug Debugger Table 5-1. Debugger Commands (Continued) Command Title Command Line Syntax Mnemonic Register Display RD {[+|-|=] [dname] [/]} {[+|-|=] [reg1 [-reg2]] [/]} [; E] REMOTE Connect the Remote REMOTE Modem to CSO RESET Cold/Warm Reset RESET Read Loop RL addr [;...

  • Page 129: This Appendix Covers

    This command is used to display and configure the board information block. This block is resident within the Non-Volatile RAM (NVRAM). Refer to the MVME187 RISC Single Board Computer User's Manual for the actual location. The information block contains various elements detailing specific operation parameters of the hardware.
  • Page 130 Configure and Environment Commands Example: Display the current contents of the board information block. cnfg 187-Bug> Board (PWA) Serial Number = "000000061050" Board Identifier = "MVME187-03 " Artwork (PWA) Identifier = "01-W3827B03A " MPU Clock Speed = "2500" Ethernet Address...

  • Page 131: Setting Environment To Bug/Operating System

    Setting Environment to Bug/Operating System Once modification and update are complete, you can now display the current contents as described earlier. Setting Environment to Bug/Operating System command allows you to interactively view and configure all Bug operational parameters that are kept in Battery Backed Up RAM (BBRAM), also known as Non-Volatile RAM (NVRAM).
  • Page 132 Configure and Environment Commands The parameters to be configured are listed in the following table: Table A-1. ENV Command Parameters ENV Parameter and Options Default Meaning of Default Bug or System environment [B/S] System Mode Field Service Menu Enable [Y/N] Display Þeld service menu.
  • Page 133 Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Auto Boot Abort Delay This is the time in seconds that the Auto Boot sequence will delay before starting the boot. The purpose for the delay is to allow you the option of stopping the boot by use of the Break key.
  • Page 134 Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Network Auto Boot Controller LUN of a network controller module currently supported by the Bug. Default is 00. Network Auto Boot Device LUN LUN of a network device currently supported by the Bug.
  • Page 135 This must be a multiple of the debugger work page, modulo $10000 (64KB). In a multi-187 environment, each MVME187 board could be set to start its work page at a unique address to allow multiple debuggers to operate simultaneously...
  • Page 136 Memory Search Delay Address FFFFCE0F The process of using the Memory Search Delay Address was implemented on the MVME188. It has not been used on the MVME187. Memory Size Enable [Y/N] Memory will be sized for Self Test diagnostics. Memory Size Starting Address 00000000 Default Starting Address is $0.
  • Page 137 Slave address decoders setup. The slave address decoders are used to allow another VMEbus master to access a local resource of the MVME187. There are two slave address decoders. They are set up as follows. Slave Enable #1 [Y/N] Yes, Setup and enable the Slave Address Decoder #1.
  • Page 138 Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Slave Address Translation 00000000 This register deÞnes which bits of the Select #1 Translation Address are signiÞcant. A logical one "1" indicates signiÞcant address bits, logical zero "0"...
  • Page 139 Setting Environment to Bug/Operating System Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Master Enable #1 [Y/N] Yes, Setup and enable the Master Address Decoder #1. Master Starting Address #1 02000000 Base address of the VMEbus resource that is accessible from the local bus.
  • Page 140 Configure and Environment Commands Table A-1. ENV Command Parameters (Continued) ENV Parameter and Options Default Meaning of Default Master Enable #4 [Y/N] Do not set up and enable the Master Address Decoder #4. Master Starting Address #4 00000000 Base address of the VMEbus resource that is accessible from the local bus.
  • Page 141 ROM Speed Bank A Code Used to set up the ROM speed. ROM Speed Bank B Code Default is $05 = 165 ns (25 MHz MVME187) or $04=145 ns (33 MHz MVME187). Static RAM Speed Code Used to set up the SRAM speed.
  • Page 142 Configure and Environment Commands A-14...

  • Page 143: Disk/Tape Controller Modules Supported

    Second Address and can be called up by Second CLUN. First First Second Second Controller Type CLUN Address CLUN Address RISC Single Board Computer (MVME187) MVME320 - Winchester/Floppy $FFFFB000 $FFFFAC00 Controller MVME323 - ESDI Winchester $FFFFA000 $FFFFA200 Controller MVME327A - SCSI Controller $FFFFA600 $FFFFA700...

  • Page 144: Disk/Tape Controller Default Conþgurations

    Disk/Tape Controller Data Disk/Tape Controller Default Configurations Note SCSI Common Command Set (CCS) devices are only the ones tested by Motorola Computer Group. RISC Single Board Computers -- 7 Devices Controller LUN Address Device LUN Device Type $XXXXXXXX SCSI Common Command Set...
  • Page 145 Disk/Tape Controller Default Configurations MVME327A -- 9 Devices Controller LUN Address Device LUN Device Type $FFFFA600 SCSI Common Command Set (CCS), which may be any of these: - Fixed direct access $FFFFA700 - Removable ßexible direct access (TEAC style) - CD-ROM - Sequential access Local ßoppy drive Local ßoppy drive...

  • Page 146: Iot Command Parameters For Supported Floppy Types

    QIC-02 streaming tape drive $FFFF5100 IOT Command Parameters for Supported Floppy Types The following table lists the proper IOT command parameters for floppies used with boards such as the MVME328, MVME167, and MVME187. Floppy Types and Formats IOT Parameter DSDD5 PCXT8 PCXT9 PCXT9_3...
  • Page 147 IOT Command Parameters for Supported Floppy Types Floppy Types and Formats IOT Parameter DSDD5 PCXT8 PCXT9 PCXT9_3 PCAT Single/Equal_in_all Track Zero Density Slow/Fast Data Rate Other Characteristics Number of Physical 0A00 0280 02D0 05A0 0960 0B40 1680 Sectors Number of Logical 09F8 0500 05A0...
  • Page 148 Disk/Tape Controller Data...

  • Page 149: Network Controller Modules Supported

    The controllers are accessed via the CLUNs and DLUNs specified in the following table. Table C-1. Network Controller Access Data Controller Interface CLUN DLUN Address Type Type MVME187 $FFF46000 Ethernet MVME376 $FFFF1200 Ethernet MVME376 $FFFF1400 Ethernet MVME376 $FFFF1600 Ethernet MVME376...
  • Page 150 Network Controller Data Table C-1. Network Controller Access Data (Continued) Controller Interface CLUN DLUN Address Type Type MVME376 $FFFFA400 Ethernet MVME374 $FF000000 Ethernet MVME374 $FF100000 Ethernet MVME374 $FF200000 Ethernet MVME374 $FF300000 Ethernet MVME374 $FF400000 Ethernet MVME374 $FF500000 Ethernet...
  • Page 151 DTroubleshooting the MVME187: Solving Startup Problems Try these simple troubleshooting steps before calling for help or sending your CPU board back for repair. Some of the procedures will return the board to the factory debugger environment. (The board was tested under these conditions before it left the factory.)
  • Page 152 Troubleshooting the MVME187: Solving Startup Problems Table D-1. Troubleshooting Steps (Continued) Possible Condition Try This: Problem II. There is a A. The Recheck the keyboard connections and power. display on the keyboard may terminal, but be connected input from the incorrectly.
  • Page 153 Table D-1. Troubleshooting Steps (Continued) Possible Condition Try This: Problem III. Debug A. Debugger 1. Disconnect all power from your system. prompt EPROM may be 2. Check that the proper debugger EPROM is missing. 187-Bug> installed per this manual. B. The board does not appear 3.
  • Page 154 Troubleshooting the MVME187: Solving Startup Problems Table D-1. Troubleshooting Steps (Continued) Possible Condition Try This: Problem IV. Debug A. The initial 1. Start the onboard calendar clock and timer. Type prompt debugger environment set mmddyyhhmm <Return> 187-Bug> parameters may where the characters indicate the month, day, appears at be set wrong.
  • Page 155 Table D-1. Troubleshooting Steps (Continued) Possible Condition Try This: Problem 6. You may need to use the cnfg command (see Appendix A) to change clock speed and/or Ethernet Address, and then later return to env <Return> and step 3. 7. Run selftest by typing in st <Return>...
  • Page 156 Troubleshooting the MVME187: Solving Startup Problems...

  • Page 157: Introduction

    EEIA-232-D Interconnections Introduction The EIA-232-D standard is the most common terminal/computer and terminal/modem interface, and yet it is not fully understood. This may be because not all the lines are clearly defined, and many users do not see the need to follow the standard in their applications.
  • Page 158 EIA-232-D Interconnections Table E-1. EIA-232-D Interconnections Signal Signal Name and Description Number Mnemonic CHASSIS GROUND. Not always used. See section Proper Grounding. TRANSMIT DATA. Data to be transmitted; input to the modem from the terminal. RECEIVE DATA. Data which is demodulated from the receive line;...

  • Page 159: Levels Of Implementation

    Levels of Implementation Table E-1. EIA-232-D Interconnections (Continued) Signal Signal Name and Description Number Mnemonic RING INDICATOR. Output from the modem to the terminal; indicates to the terminal that an incoming call is present. The terminal causes the modem to answer the phone by carrying DTR true while RI is active.
  • Page 160 EIA-232-D Interconnections Signal Adaptations One set of handshaking signals frequently implemented are RTS and CTS. CTS is used in many systems to inhibit transmission until the signal is high. In the modem application, RTS is turned around and returned as CTS after 150 microseconds. RTS is programmable in some systems to work with the older type 202 modem (half duplex).
  • Page 161 Levels of Implementation SERIAL PORT 1488 1489A 39kΩ -12V CONNECTOR +12V LS08 TERMINAL 470Ω 470Ω 470Ω OPTIONAL HARDWARE TRANSPARENT MODE SIG GND CHASSIS GND LOGIC LS08 +12V SIG GND 470Ω 1488 SERIAL PORT 1489A CONNECTOR 39kΩ -12V MODEM 1488 HOST SYSTEM 470Ω...
  • Page 162 EIA-232-D Interconnections Figure E-2 shows a way of wiring an EIA-232-D connector to enable a computer to connect to a basic terminal with only three lines. This is feasible because most terminals have DTR and RTS signals that are ON, and which can be used to pull up the CTS, DCD, and DSR signals.
  • Page 163 Levels of Implementation Proper Grounding Another subject to consider is the use of ground pins. There are two pins labeled GND. Pin 7 is the SIGNAL GROUND and must be connected to the distant device to complete the circuit. Pin 1 is the CHASSIS GROUND, but it must be used with care.
  • Page 164 EIA-232-D Interconnections...
  • Page 165 3-20 information block A-1 adapters 2-7 level hardware description 2-1 additional manuals for the MVME187 level overview 2-7 board 1-6 select value 4-24 address 5-4 boldface string 5-3 as a parameter 5-5...
  • Page 166 Index BOOTP descriptions 5-4 address determination and bootfile facilities 4-2 selection 4-20 identifier 5-3 protocol module 4-20 line 5-1 Bootstrap command parameters and Halt (BH) 4-16 IOT B-4 Operating System (BO) 4-15 commands Protocol (BOOTP) 4-20 diagnostic utilities 4-26 braces 5-3 commands/prefixes, diagnostic monitor break 4-11 4-25...
  • Page 167 4-19 ment) E-1 display of memory 4-2 debug monitor 3-14 DLUN (device LUN) B-2, C-1 see also 187Bug and MVME187Bug document set for MVME187-0xx board debug port 5-7 debugger 3-9 documentation commands 5-15 available non-Motorola publications directories 4-3...
  • Page 168 4-25 functions 5-11 factory debugger environment D-1 interrupts 2-23 FAIL LED 2-11 preparation 3-5 features of the MVME187 RISC Single preparation and installation 3-1 Board Computer 2-4 headers 3-8 flexible diskette B-2 hexadecimal character 1-2 floating point host port 5-7...
  • Page 169 LCSR (Local Control and Status Regis- on 25 MHz main boards 2-2 ters) 3-8 mezzanines, stacking 2-16 LEDs 2-11 mixed parity 2-16 loading and executing user programs 4-2 modem(s) E-1 local modifying memory 4-2 bus arbitration 2-12 Motorola-style byte ordering 1-3 floppy drive B-3 IN-13...
  • Page 170 2-24 4-21 numeric value 5-4 method 4-21 NVRAM (Non-Volatile RAM) multiprocessor support 4-21 checksum error 4-12 MVME187 2-1, C-1 low battery condition 4-12 block diagram 2-7 specifications 2-6 object code 5-8 MVME187Bug debugging package offset registers 5-7...
  • Page 171 Pseudo Stack Pointer (R31) 4-5 see also CD2401 pseudo-registers 5-7 scientific notation 5-14 publications SCON LED 2-11 applicable Motorola 1-6 SCSI Non-Motorola 1-9 bus termination 3-29 not included in the set 1-6 Common Command Set (CCS) B-2, QIC-02 streaming tape drive B-4...
  • Page 172 Index SCSI commands small-endian byte ordering 1-3 Inquiry 4-14 software-programmable hardware inter- Mode Sense 4-14 rupts 2-23 sector size 4-14 source line 5-8 selftest error 4-12 special function unit (SFU) 5-11 sequential access device B-2, B-3 specifications 2-6 Serial Controller Chip (SCC) square brackets 5-3 see also CD2401 SRAM (static RAM) 2-13...
  • Page 173 I/O space 4-24 transfer type (TT) 2-24 specification 1-9 transition boards supported VMEchip2 MVME187 2-8 ASIC 2-9 transition module installation 3-20 LCSR (Local Control and Status Reg- translation table 5-10 isters) 3-8 translation through the Memory Man- LM/SIG register 4-24...

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