Mitsubishi Electric DD-6000 Service Manual page 48

Table 3-5-10 (1/5) TMP94CS40AF
Pin
Name
No.
77 P00 – P07 Port 0: I/O port.
| D0 – D7 Data 0–7: data bus 0–7.
84 Function is selectable by setting of AM0/1
terminal.
It becomes high impedance at no external
memory access.
86 P10 – P17 Port 1: I/O port.
| D8 – D15 Data 8–15: data bus 8–15.
93 Function is selectable by setting of AM0/1
terminal.
It becomes high impedance at no external
memory access.
95 P20 – P27 Port 2: I/O port.
| D16 – D23 Data 16–23: data bus 16–23.
102 Function is selectable by setting of AM0/1
terminal.
It becomes high impedance at no external
memory access.
104 P30 – P37 Port 3: I/O port.
| D24 – D31 Data 24–31: data bus 24–31.
111 Function is selectable by setting of AM0/1
terminal.
It becomes high impedance at no external
memory access.
113 P40 – P47 Port 4: I/O port.
| A0 – A7 Address 0–7: address bus 0–7.
120 Function is selectable by setting of AM0/1
terminal.
Signal does not change at no external
memory access.
122 P50 – P57 Port 5: I/O port.
| A8 – A15 Address 8–15: address bus 8–15.
129 Function is selectable by setting of AM0/1
terminal.
Signal does not change at no external
memory access.
131 P60 – P67 Port 6: I/O port.
| A16 – A23 Address 16–23: address bus 16–23.
138 Function is selectable by setting of AM0/1
terminal.
Signal does not change at no external
memory access.
75 P70 Port 70: output port. (Initializes to "1" output.)
R D Read: strobe signal reading external memory.
Function is selectable by setting of AM0/1
terminal.
Strobe signal is not developed at no
external memory access.
74 P71 Port 71: output port. (Initializes to "1" output.)
W R L L Write: strobe signal writing D0–D7 of
external memory.
Strobe signal is not developed at no
external memory access.
73 P72 Port 72: output port. (Initializes to "1" output.)
W R L H Write: strobe signal writing D8–D15 of
external memory.
Strobe signal is not developed at no
external memory access.
72 P73 Port 73: output port. (Initializes to "1" output.)
W R H L Write: strobe signal writing D16–D23 of
external memory.
Strobe signal is not developed at no
external memory access.
71 P74 Port 74: output port. (Initializes to "1" output.)
W R H H Write: strobe signal writing D24–D31 of
external memory.
Strobe signal is not developed at no
external memory access.
Function
3-33
Table 3-5-10 (2/5) TMP94CS40AF
Pin
Name
No.
70 P75 Port 75: I/O port.
B U S R Q Bus request: signal with memory interface
terminal requested to be high impedance.
The following pins become high
impedance, but no change is made when
used as a port.
A0 – A23, D0 – D31, RD, WRLL, WRLH,
WRHL, WRHH, CS0 – CS5, OE0 – OE1,
WE0–WE1, RAS group, CAS group
69 P76 Port 75: output port. (Initializes to "1" output.)
B U S A K Bus acknowledge: signal, that indicates
request of BUSRQ received.
67 P80 Port 80: output port. (Initializes to "1" output.)
C S 0 Chip select 0: "L" level is developed if
address is within the assigned address
range.
66 P81 Port 81: output port. (Initializes to "1" output.)
C S 1 Chip select 1: "L" level is developed if
address is within the assigned address
range.
R A S 0 Low address strobe 0: RAS strobe signal
for DRAM is developed if address is within
the assigned address range.
65 P82 Port 82: output port. (Initializes to "0" output.)
C S 2 Chip select 2: "L" level is developed if
address is within the assigned address
range.
64 P83 Port 83: output port. (Initializes to "1" output.)
C S 3 Chip select 3: "L" level is developed if
address is within the assigned address
range.
R A S 1 Low address strobe 1: RAS strobe signal
for DRAM is developed if address is within
the assigned address range.
63 P84 Port 84: output port. (Initializes to "1" output.)
C S 4 Chip select 4: "L" level is developed if
address is within the assigned address
range.
62 P85 Port 85: output port. (Initializes to "1" output.)
C S 5 Chip select 5: "L" level is developed if
address is within the assigned address
range.
49 P86 Port 86: I/O port.
WAIT Wait: Bus wait request signal
60 PA 0 Port A0: output port. (Initializes to "1" output.)
C A S 0 Column address strobe 0: CAS strobe
signal for DRAM is developed if address is
within the assigned address range.
L C A S 0 Lower column address strobe 0: lower CAS
strobe signal for DRAM is developed if
address is within the assigned address
range.
59 PA 1 Port A1: output port. (Initializes to "1" output.)
U C A S 0 Upper column address strobe 0: upper CAS
strobe signal for DRAM is developed if
address is within the assigned address
range.
58 PA 2 Port A2: output port. (Initializes to "1" output.)
O E 0 Out enable 0: out enable signal for DRAM is
developed.
57 PA 3 Port A3: output port. (Initializes to "1" output.)
O E 1 Out enable 1: out enable signal for DRAM is
developed.
56 PA 4 Port A4: output port. (Initializes to "1" output.)
W E 0 Write enable 0: write enable signal for
DRAM is developed.
Function