Haier L37V6-A8K Service Manual page 47

+3.3V_AVDD 3.3V_AVDD
Close to respective power Pins
1 2
FB14 C53 C54 C55 C56 C57 C58 C59 C60
22uF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
+3.3V_DVDD 3.3V_DVDD
Close to respective power Pins
Close to respective power Pins
1 2
FB15 C67 C68 C69 C70 C71 C72 C73
22uF 100nF 100nF 100nF 100nF 100nF 100nF
+1.8V_DVDD CVDD_1.8
Close to respective power Pins
1 2
FB16 C78 C79 C80 C81 C82 C83 C84
FB0805
22uF 100nF 100nF 100nF 100nF 100nF 100nF
AVDD_1.8
+1.8V_AVDD
Close to respective power Pins
1 2
FB17 C90 C91 C92 C93 C94 C95
22uF 100nF 100nF 100nF 100nF 100nF
BootStrap Signals
RMADDR[6:0] For I2C address [6:0] to JTAG bridge
Host I/F, to determine device address.
RMADDR[12:7] User_Bits[5:0] for configuration setting
OP_MODE[1:0]:
00 = Normal. UART in 186 on system pins.
01 = I2C to JTAG bridge.
RMADDR[14:13] 10 = JTAG port, 5 wires
11 = External parallel control bus using
ROM Addr/Data
SPI_EN: 0 = parallel ROM I/F. 1 = SPI
RMADDR15 serial ROM and Cache control
Initial state of OCM ROM:
0 = internal ROM on, and mapped to top
32K of OCM and OCM boot will be from
internal ROM codes.
RMADDR16
1 = Internal ROM off. The external ROM
mapped to entire upper 512K of OCM
address. OCM boot from external ROM
code.
OSC_SEL: 0 = Xtal and internal oscillator.
RMADDR17 1 = TTL oscillator (on TCLK pin)
BOOTSTRAP OPTIONS SELECT
(NOT POPULATED SHOULD BE
HARD WIRED)
JP4
MCSCL
MCSCL 1,2,8,9,11
3
MCSDA
MCSDA 1,2,8,9,11
2
1
CONN3_250MM
C61 C62 C63 C64 C65 C66
100nF 100nF 100nF 100nF 100nF 220pF
C74 C75 C76 C77
100nF 100nF 100nF 220pF
C85 C86 C87
100nF 220pF 220pF
100R R311
DDC_SCL_VGA 0 R312
C96 C97 C98 100R R313
DDC_SDA_VGA_1 0 R314
220pF 220pF 100nF
0R/OP R70
1,8,9,11 RESETn
R71
0R SW1
SW PUSHBUTTON
C100
100nF
10nF C104 BLUE-
10nF C105 GREEN-
10nF C106 RED-
R73 R74 R75
47R 47R 47R
SELECT ONE
3.3V_DVDD FB27 FB
1 2
+5V_5221 FB28 FB/OP
1 2
SOCKET:
R409 IC51-2084-1052
10K
+5V_5221
U15
10K_NC R89 RMADDR0
10K_NC R91 RMADDR1 RMADDR17 30
NC/A17 VCC
10K_NC R93 RMADDR2 RMADDR16 2
A16
10K_NC R95 RMADDR3 RMADDR15 3
A15 OE
10K_NC R96 RMADDR4 RMADDR14 29
A14 WE
10K_NC R98 RMADDR5 RMADDR13 28
A13
10K_NC R99 RMADDR6 RMADDR12 4
A12 CE
10K_NC R100 RMADDR7 RMADDR11 25
A11
10K_NC R101 RMADDR8 RMADDR10 23
A10
RMADDR9 26
A9
RMADDR8 27
A8 DQ7
RMADDR7 5
A7 DQ6
RMADDR6 6
A6 DQ5
RMADDR5 7
A5 DQ4
RMADDR4 8
A4 DQ3
RMADDR3 9
A3 DQ2
+5V_5221 RMADDR2 10
A2 DQ1
RMADDR1 11
A1 DQ0
RMADDR0 12
A0
10K_NC R103 RMADDR9
10K_NC R104 RMADDR10 1
NC
10K_NC R105 RMADDR11
GND
10K R106 RMADDR12
10K_NC R107 RMADDR13
AT49F020-70JC
10K_NC R108 RMADDR14
10K_NC R109 RMADDR15 32-Pin PLCC Socket
10K_NC R110 RMADDR16
10K_NC R111 RMADDR17
3.3V_DVDD
U14
3.3V_AVDD
11
AVDD_OUT_LV_E_33
24
AVDD_OUT_LV_E_33
26
AVDD_LV_33
27
AVDD_OUT_LV_O_33
40
AVDD_OUT_LV_O_33
113
AVDD_IMB_33
120
AVDD_RX2_33
125
AVDD_RX1_33
130
AVDD_RX0_33
134
AVDD_RXC_33
141
AVDD_BLUE_33
145
AVDD_GREEN_33
150
AVDD_RED_33
+5V_5221 154
AVDD_ADC_33
172
LBADC_VDD_33
171
GPROBE
AVDD_RPLL_33
12
DEBUG
AVSS_OUT_LV_E
23
AVSS_OUT_LV_E
PORT 25
AVSS_LV
28
AVSS_OUT_LV_O
39
AVSS_OUT_LV_O
115
AGND_IMB
117
AGND_RX2
122
4 AGND_RX1
3.3V_AVDD 127
3 AGND_RX0
131
2 AGND_RXC
144
1 AGND_BLUE
149
AGND_GREEN
G_UART_DI C88 C89 153
CN8
AGND_RED
UART_DI 156
RS232
AGND_ADC
15pF 15pF 168
AGND_RPLL
177
LBADC_GND
X1 136
GND_RXPLL
G_UART_DO 14.318MHz
UART_DO TCLK 170
TCLK
XTAL 169
XTAL
71
HOST_SCL/UART_DI
72
HOST_SDA/UART_DO
77
3 DDC_SCL_VGA DDC_SCL_VGA
78
3 DDC_SDA_VGA_1
DDC_SDA_VGA
DDC_SCL_DVI 79
1 DDC_SCL_DVI DDC_SCL_DVI
DDC_SDA_DVI 80
1 DDC_SDA_DVI
DDC_SDA_DVI
178
RESETn
10nF C99 BLUE+ 142
3 BAIN
BLUE+
R325 C101 BLUE- 143
10 SOG BLUE-
0R/OP 10nF SOG_MCSS 146
SOG_MCSS
C102 GREEN+ 147
3 GAIN GREEN+
10nF GREEN- 148
GREEN-
C103 RED+ 151
3 RAIN
RED+
10nF RED- 152
RED-
VGAHS 181
3 AHSYNC HSYNC
VGAVS 182
3 AVSYNC
VSYNC
155
ADC_TEST
RX2+ 118
1 RX2+
RX2+
RX2- 119
1 RX2- RX2-
RX1+ 123
1 RX1+ RX1+
RX1- 124
1 RX1-
RX1-
RX0+ 128
1 RX0+ RX0+
RX0- 129
1 RX0- RX0-
RXC+ 132
1 RXC+
RXC+
RXC- 133
1 RXC- RXC-
3.3V_AVDD 138
CLKOUT
R80 270 114
REXT
R238 3.3K RMADDR17 183
ROM_ADDR17
RMADDR16 184
ROM_ADDR16
RMADDR15 185
ROM_ADDR15
RMADDR14 186
ROM_ADDR14
RMADDR13 187
ROM_ADDR13
RMADDR12 188
ROM_ADDR12
RMADDR11 189
ROM_ADDR11
RMADDR10 192
ROM_ADDR10
RMADDR9 193
ROM_ADDR9
RMADDR8 194
ROM_ADDR8
RMADDR7 195
ROM_ADDR7
RMADDR6 196
ROM_ADDR6
RMADDR5 197
ROM_ADDR5
RMADDR4 198
ROM_ADDR4
RMADDR3 199
ROM_ADDR3
RMDATA[0..7] RMADDR2 200
ROM_ADDR2
RMADDR1 201
ROM_ADDR1
RMADDR0 202
ROM_ADDR0
+5V_5221
RMDATA7 203
ROM_DATA7
R87 R88 RMDATA6 204
ROM_DATA6
10K 10K RMDATA5 207
ROM_DATA5
J5 RMDATA4 208
ROM_DATA4
JUMPER
C110 RMDATA3 1
ROM_DATA3
100nF RMDATA2 2
ROM_DATA2
RMDATA1 3
ROM_DATA1
32 RMDATA0 4
ROM_DATA0
24 ROM_OEn 5
ROM_OEn
31 ROM_WEn 6
ROM_WEn
ROM_CSn 7
ROM_CSn
22
0R/OP R328
gm5221
21 RMDATA7 R102 PQFP208
20 RMDATA6
10K
19 RMDATA5
18 RMDATA4
17 RMDATA3 100R R359
1 AS_1
15 RMDATA2 100R R360
1 AS_2
14 RMDATA1 100R R361
1 AS_3
13 RMDATA0
1 VS1
RMDATA[0..7]
8 MP3_GPIO
16
- 47 -
AVDD_1.8
CVDD_1.8
3.3V_DVDD
CVDD_1.8
10
VCO_LV
13 LV_E9
CH3P_LV_E(PD0/ER0)
14 LV_E8
CH3N_LV_E(PD1/ER1)
15 LV_E7
CLKP_LV_E(PD2/ER2)
3.3V_A 16 LV_E6
CLKN_LV_E(PD3/ER3)
17 LV_E5
CH2P_LV_E(PD4/ER4)
18 LV_E4
CH2N_LV_E(PD5/ER5)
19 LV_E3
CH1P_LV_E(PD6/ER6)
20 LV_E2
CH1N_LV_E(PD7/ER7)
21 LV_E1
CH0P_LV_E(PD8/EG0)
22 LV_E0
CH0N_LV_E(PD9/EG1)
29 LV_O9
CH3P_LV_O(PD10/EG2)
30 LV_O8
CH3N_LV_O(PD11/EG3)
31 LV_O7
CLKP_LV_O(PD12/EG4)
32 LV_O6
CLKN_LV_O(PD13/EG5)
33 LV_O5
CH2P_LV_O(PD14/EG6)
34 LV_O4
CH2N_LV_O(PD15/EG7)
35 LV_O3
CH1P_LV_O(PD16/EB0)
36 LV_O2
CH1N_LV_O(PD17/EB1)
AGND 37 LV_O1
CH0P_LV_O(PD18/EB2)
38 LV_O0
CH0N_LV_O(PD19/EB3)
43 PD20
PD20/EB4
44 PD21
PD21/EB5
45 PD22
PD22/EB6
46 PD23
PD23/EB7
+5V
56
PD24/OR0
57
PD25/OR1
58 R336
PD26/OR2
59 4.7K/OP
PD27/OR3
60
PD28/OR4
61
PD29/OR5
62
PD30/OR6
63
PD31/OR7
64 R337
PD32/OG0
65 0R
PD33/OG1
66
PD37/OG5
47 DEN
DEN
DEN
48 DHS
DHS DHS
49 DVS
DVS
DVS
55 DCLK
DCLK DCLK
67 PPWR
PPWR
PPWR
68 PBIAS
PBIAS PBIAS
3.3K/OP
81 GPIO0
GPIO0
82 GPIO1
VGACON 3
GPIO1
83
GPIO2
84 100R R326
LED
GPIO3
85 SoftReset
GPIO4 STBY
88 100R R47
GPIO5
89
GPIO6
90 100R
GPIO7/IRQin
91 C107 100pF
GPIO8/IRQout
92 SCL 0R R76
GPIO9/SCL
93 SDA 0R R77
GPIO10/SDA
98
PWM0 4
PWM0/GPIO11
99 PWM1
PWM1/GPIO12
100
PWM2/GPIO13
101
PWM3/GPIO14 5VAON 6
69
VBI_INTR 9
STI_TM1/GPIO15
167
VBUFC_RPLL
135
VBUFC_DVI
70
STI_TM2
206
CRVSS
191
CRVSS
180
CRVSS
140
CRVSS
97 R83
CRVSS
94
CRVSS
76 100
CRVSS
74
CRVSS
51
CRVSS
42
CRVSS
8
CRVSS
87
CRVSS
165 R85
GND_RPLL
163 470K
GND1_ADC
173 LBADC_IN1
LBADC_IN1
174 LBADC_IN2 100 R92
LBADC_IN2
175 LBADC_IN3
LBADC_IN3
176
LBADC_RETURN
C140 C111 C112
100nF_SC 100nF 100nF
R138 0R
R90 100R_SC
KEYBOARD INPUT
ADC_IN1 2
TO LBW ADC
T_STATE 11
TEMP_DETECT 6
Route (LBADC_IN1, LBADC_RET) and
(LBADC_IN2, LBADC_RET) as differential
C113 R84 tracks close to each other and ground the
470K
return track of each pair very close to the
100nF 3.3V_AVDD
5221 and ground pin
RaisingSun Co.Ltd
Title
RS LCD TV
Size Document Number
C 5221
Date: Friday, April 22, 2005
LV_E[0..9] 4,5
LV_O[0..9] 4,5
PD[20..23] 5
TJC3-10A
ENBKL
4 ENBKL 1
2
+5V 3
BRI
4 BRI 4
5 DHS
5
5 DVS
6
+5V 7
8
9
10
CN9
+5V_5221
5
5
5
5
R234
R236 R235
4.7K 4.7K
4.7K
4
4
R72
VGA_TV_SW 3
YUV_TV_SW 10
2
6
STBY_34XY 1
MUTE 1
R327
IR_IN 2,8
R237
MCSCL_EE 2
4.7K
MCSDA_EE 2
+5V_5221
4.7K R78
4.7K R79
C108 C109
47pF 47pF +5V_5221
R247
4.7K
100R/OP
STBY_AMP 1
R48
WP 2
3.3V_AVDD
R86
470K_NC
R133
Scart_Signal_1 1
33K
ADC_IN2 2
R94
Scart_Signal_2 1
33K
R137 R97 ADCIN:
12K 12K 接口有 ： 信号
2.53–3.2V = SCART 4 3
接口有 ： 信号
1.33–2.13V = SCART 16 9
0–0.54V = SCART接口无信号
Rev
V0.1
Sheet 7 of 12