Pioneer CDJ-1000 Service Manual page 61

CDJ-1000 CDJ-1000
Wi PD3431 A9 (MAIN ASSY : IC201)
« System Control CPU
@ Pin Function (1/3)
[Ne] PinName | WO
fi fv = ss—i'idr:C«=sd By the capacitor (0.1pF) it GND-connects.
DGP2
2 | bs Motorola DSP (preceding paragraph) Interface
@ Pin Function (3/3)
Motorola OSP (latter part) Interface
Motorola DSP (preceding paragraph) Interface
Motorola DSP (latter part) Interface
7 jDOSW t | Digital OUT ON/OFF SW detection
8 |CNT2 | | Control 2 input terminal
| 9 | CNT1 YO |Control 1 input and output terminal
minal which detects a flash write-in permission signal
87 |IRQO MBLKCK joi |
7
88 fo | The interruption demand from FPGA
te
TCLKB TKCNT Track pulse input (pulse width is measured and speed is detected) OQ {A serial output besides a controller ,
9s [Pa2 FEC | 0 [Serial input enabie of ADSC CIRC par (0 permission 1: prohibiior) [1 [he setalinputtom SP SSCSSSCSCSCSC~SC*@Y
96 |PA3 ENS | © |Serial input enable of ADSC part (0: permission 1: prohibition) Isto. - ss [Aserialinputbesidesacontoller —stCi<"—s~s—sSCSCSC'S
37 [Pa TeONT | _1 [Track pulse inp sex ——S*d 0 |e seialceckw ose SCSCSC~"SCSCSCSCSCSCS
17 |S1CK OA seriai clock besides a controller
XFRST O | Reset to FPGA .
Reset to circumference IC
| 20 [ASwc 0 [Serial change SW enable
Line OUT output MUTE
22 |Vss - {Digital GND
Monitor terminal 2
98 [PAS XDMUTE2 | © [Driver IC mute control (O:MUTE 1:MUTE release)
99 [PAS FESEN | © |FEP serial input enable (0: permission 1: prohibition)
100 [TIOCB2 FG | 1 _|FG pulse input
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a
4
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fad 4 m
o
OQ |The terminal for repealing zero detection
The reset terminal for DAC
FPGA interface (data bus)
Power supply (VD5V)
FPGA interface (data bus)
81 80