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13255
4K UV PROM Module
13255-Ql007/06
Fev
AUG-Ol-76
3.0
FUNCTIONAL DESCRIPTION.
Refer to the block diagram (figure
1),
schematic diagram (figure 2), component location diagram (figure
3),
and parts list
(02640-60007)
located in the appendix.
3.1
3.1.1
3.1.2
3.2
3.2.2
3.3
3.3.2
This PCA provides
4K
bytes of memory contained in
UV
erasable PROMs.
The PCA is divided into
2
bloCKS of
2K
bytes each.
The PROMs are
Intel 1702A, organized as 256 x
8
bits, with an access time of
1.2
microseconds.
BLOCK A.
This bloCK consists of e1ght 1702A PROMs.
A particular PROM Is selected by the chip select (C5) signals from
the access control bloCK.
The byte of interest within the selected
PROM
is determined by the signals ADORO-7.
The
8
bits of data are
sent to the data path to be output onto the terminal bus.
BLOCK B.
See
3.1.1.
See
3.1.2.
BLOCK STARTING ADDRESS.
This bloCK allows each 2K byte bloCK of PROMs to be selectively
enabled Or disabled independently ot the other bloCK.
The starting
address of each 2K byte bloCK may be independently set to any
2K
byte boundary with1n a 64K byte address space.
The 74LS136 gates act as comparators between the jumpers and the
address
~ignals
ADDR11-15.
If the address line Is low and the
corresponding jumper is out, the output of the exclusive-or gate
Is high (note that toe address lines are negative true); this is
also the case if the address line is high and the jumper is in
(grounding the input of the exclusive-or).
Otherwise, the
output of the exclusive-or is low.
The outputs of the exclusive-
or gates are wire-anded for each block to determine whether the
address corresponds to that selected by the jumpers--if any output
is low, then the signals BLOCK A and BLOCK B will be low.
An
additional jumper is provided to connect the signals BLOCK A or
BLOCK B directly to ground, inhibiting the PROM blOCK from being
selected, irrespective of the state of the address lines.
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