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Introduction
Power Sequence
It is recommended that the following power sequence be followed when using the C410x with a host
server.
1. For a single host server connected to a C410x:
2. For multiple host servers connected to a C410x:
NOTE:
Supported GPGPU Configurations
The C410x supports installing different GPGPU and other devices in the chassis.
Mixing different GPGPUs connected to the same host server is not supported. All GPGPUs connected to a
host server must be the same type.
Mixing other devices with GPGPUs connected to the same host server is supported.
GPGPU Support Limitation
There are some host servers that have multiple PCIex16 expansion slots. This allows multiple Host
Interface Cards (HIC) to be installed in a single host server. The flexibility of the C410x system allows 16
GPGPUs to be connected to a single host server with multiple PCIex16 expansion slots. Host servers that
are based on x86 architecture have a 16 bit (total 64 K) IO address space hardware limit. The 16 bit IO
address space hardware limit limits the number of PCI devices that can be connected to the host server.
The host server does not boot or other POST errors occur if the IO address space limit is exceeded. The
number of onboard host server PCI devices utilize a fixed amount of IO address space. The remaining IO
address space is used to determine the number of GPGPU that can be installed in a C410x that is
connected to the single host server. Each GPGPU requires 4K of IO address space. The number of
onboard PCI devices plus the number of GPGPUs determine the amount of IO address space used.
Therefore, the 16 bit IO address space limitation does not allow a single host server to support 16
GPGPUs installed in a C410x.
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