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HP Visualize B1000 Hardware Manual
HP Visualize B1000 Hardware Manual

HP Visualize B1000 Hardware Manual

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An Overview of the VISUALIZE fx Graphics
Accelerator Hardware
Noel D. Scott
Daniel M. Olsen
Ethan W. Gannett
Article 4
1998 Hewlett Packard Company
Three graphics accelerator products with different levels of performance are
based on varying combinations of five custom integrated circuits. In addition,
these products are the first ones from Hewlett-Packard to provide native
acceleration for the OpenGL API.
T
he VISUALIZE fx family of graphics subsystems consists of three
6
4
products, fx
, fx
These products are built around a common architecture using the same
custom integrated circuits. The primary difference between these controllers
is the number of custom chips used in each product (see Table I).
Table I
Number of custom chips in the different
VISUALIZE fx products
Product
2
fx
4
fx
6
fx
A chip-level block diagram of the VISUALIZE fx
This is the most complex configuration and also the one with the highest
performance in the product line. The VISUALIZE fx
products use subsets of the chips used in the fx
have support for the optional hardware-accelerated texture map module,
which contains a local texture cache for storage of texture map images. If the
texture accelerator is not present, the bus between the interface chip and the
first raster chip is directly connected.
2
, and fx
, and an optional hardware texture mapping module.
Texture
Geometry
Chip
Chip
1
2
28
Raster
Chip
1
2
2
2
3
4
6
product is shown in Figure 1.
4
and the VISUALIZE fx
6
6
4
. The fx
and fx
subsystems
May 1998 The Hewlett-Packard Journal
2

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Summary of Contents for HP Visualize B1000

  • Page 1 An Overview of the VISUALIZE fx Graphics Accelerator Hardware Three graphics accelerator products with different levels of performance are Noel D. Scott based on varying combinations of five custom integrated circuits. In addition, Daniel M. Olsen these products are the first ones from Hewlett-Packard to provide native Ethan W.
  • Page 2 Figure 1 A chip-level diagram of the VISUALIZE fx product. Geometry Accelerator Up to 8 Texture Accelerator 200 MHz/ 200 MHz/ 33 Bits 41 Bits Geometry SDRAM SDRAM Chip Texture Cache RAM Video Chip Video Geometry Data Chip 200 MHz/41 Bits Texture Texture Chip...
  • Page 3: Occlusion Culling

    Occlusion Culling The HP fast-break program (page 8) enabled us to understand representation of a more complex part is visible. Since a customer requirements by analyzing what is important in bounding box, or more generally a bounding volume, com- OpenGL graphics today. As a result, we developed a technol-...
  • Page 4 There is also special circuitry in the interface chip that is bus connects the interface chip to the video chip. This used to accelerate many operations commonly done by provides video control, download of color maps, and X11 or other 2D APIs. cursor control.
  • Page 5 The system design of virtual texture mapping involved changes in the HP-UX operating system to support graphics interrupts, onboard firmware support for these interrupts, the introduction of an asynchronous texture interrupt managing daemon pro- cess, and the associated texturing hardware described in this *A texel is one element of a texture.
  • Page 6 article. Having a centralized daemon process manage the (Figure 3). These features have made these products very cache allows for cache efficiency, parallel handling of texture appealing systems for texturing applications on workstation downloads while 3D graphics rendering is occurring, and shar- graphics.
  • Page 7 HP Workstation Systems Division. He performance projections, and modeling. He is responsible for the development of new 3D came to HP in 1988 after receiving an MS designed the I/O bus for the geometry chip products for HP workstations. He has been degree in computer science from Iowa State described in the article.