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Epson S1C63000 Core Cpu Manual

Seiko epson s1c63000 cmos 4-bit single chip microcomputer core cpu manual
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MF855-03
CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER
S1C63000
Core CPU Manual

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Summary of Contents for Epson S1C63000

  • Page 1 MF855-03 CMOS 4 - BIT SINGLE CHIP MICROCOMPUTER S1C63000 Core CPU Manual...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any...
  • Page 3 The information of the product number change Starting April 1, 2001, the product number will be changed as listed below. To order from April 1, 2001 please use the new product number. For further information, please contact Epson sales representative.

  • Page 5: Table Of Contents

    3.3.4 Memory write ... 24 3.3.5 Memory read ... 25 3.4 Initial Reset ... 25 3.4.1 Initial reset sequence ... 25 3.4.2 Initial setting of internal registers ... 26 S1C63000 CORE CPU MANUAL CPU M ANUAL ... 4 ... 22...
  • Page 6 4.2.3 Instruction list by function ... 40 4.2.4 List in alphabetical order ... 48 4.2.5 List of extended addressing instructions ... 55 4.3 Instruction Formats ... 59 4.4 Detailed Explanation of Instructions ... 60 ... 33 EPSON S1C63000 CORE CPU MANUAL...

  • Page 7: Chapter 1: Outline

    CHAPTER The S1C63000 is the core CPU of the 4-bit single chip microcomputer S1C63 Family that utilizes original EPSON architecture. It has a large and linear addressable space, maximum 64K words (13 bits/ word) program memory (code ROM area) and maximum 64K words (4 bits/word) data memory (RAM, data ROM and I/O area), and high speed, abundant instruction sets.

  • Page 8: Block Diagram

    QUEUE (16) X (16) Y (16) SP2 (8) SP1 (8) DATA ADDRESS LATCH 1.4 Input-Output Signals Tables 1.4.1 (a) and 1.4.1 (b) show the input/output signals between the S1C63000 and peripheral circuits. Type Terminal name Power supply Clock Address bus IA00–IA15 DA00–DA15...
  • Page 9 Status signal FETCH STOP BS16 DBS0 DBS1 S1C63000 CORE CPU MANUAL Table 1.4.1(b) Input/output signal list (2) Instruction bus Inputs an instruction code. 16-bit data bus A bidirectional data bus to connect to the RAM (stack RAM) for 16-bit accessing.

  • Page 10: Chapter Rchitecture

    CHAPTER 2: ARCHITECTURE CHAPTER This chapter explains the S1C63000 ALU, registers, configuration of the program memory area and data memory area, and addressing. 2.1 ALU and Registers 2.1.1 ALU The ALU (Arithmetic and Logic Unit) loads 4-bit data from a memory or a register and operates the data according to the instruction.

  • Page 11: Flags

    The queue register is accessed by the hardware, so it is not necessary to be aware of the register operation when programming. 2.1.3 Flags The S1C63000 contains a 4-bit flag register (F register) that indicates such things as the operation result status within the CPU. • Z (zero) flag The Z flag is set to "1"...
  • Page 12 The RETI instruction is used to return from interrupt processing routines (including software interrupts), and returns the F register data that was evacuated when the interrupt was generated. Inverts flag(s) %F,imm4 Evacuates the F register PUSH %F Returns the F register Returns the F register RETI EPSON S1C63000 CORE CPU MANUAL...

  • Page 13: Arithmetic Operations With Numbering System

    2.1.4 Arithmetic operations with numbering system In the S1C63000, some instructions support a numbering system. These instructions are indicated with the following notations in the instruction list. operand,n4 operand,n4 operand,n4 operand,n4 (See "Instruction List" or "Detailed Explanation of Instructions" for the contents of the operand.) "n4"...

  • Page 14: Ext Register And Data Extension

    2.1.5 EXT register and data extension The S1C63000 has a linear 64K-word addressable space, therefore it is required to handle 16-bit address data. The EXT register and the F flag that extend 8-bit data into 16-bit data permit 16-bit data processing.
  • Page 15 1.Instructions which have a source and /or a destination operand with the post-increment function, [%X]+ and [%Y]+. 2.Instructions which have [%X] and/or [%Y] in both the source and destination operands. 3.The RETD instruction and the LDB instructions which transfers 8-bit data. S1C63000 CORE CPU MANUAL CHAPTER 2: ARCHITECTURE EPSON...
  • Page 16 ...Works as "JR 0x3A88" ( = C, NC, Z, or NZ) 0x88 %EXT,0xF8 ...Works as "CALR 0xF862" CALR 0x62 See Section 2.2.3, "Branch instructions" for the branch instructions. %YL,imm8 %Y,sign8 %Y,imm8 sign8 JRNC sign8 EPSON sign8 JRNZ sign8 S1C63000 CORE CPU MANUAL...

  • Page 17: Program Memory

    2.2.1 Configuration of program memory The S1C63000 can access a maximum 64K-word ( 13 bits) program memory space. In the individual model of the S1C63 Family, the ROM of which size is decided depending on the model is connected to this space to write a program and static data.

  • Page 18: Branch Instructions

    Table 2.2.3.1 Types of branch instructions Condition Unconditional Conditional JRC, JRNC, JRZ, JRNZ Unconditional Unconditional CALZ Unconditional CALR Unconditional RET, RETS, RETD, RETI Unconditional sign8 JRNC sign8 JRZ sign8 256) = 25600 EPSON Instruction JRNZ sign8 S1C63000 CORE CPU MANUAL...
  • Page 19 %EXT,0x24 %YL,0x00 Figure 2.2.3.1 shows the operation of the jump instructions and the branch range. S1C63000 CORE CPU MANUAL ...Jumps to the instruction 5 steps after ...Jumps to the instruction 30 steps after ...Sets the bit 0 in the address 0010H to "1" ([0010H] = 5) ...Jumps to the instruction 6 steps after...
  • Page 20 003FH FFFFH Fig. 2.2.3.1 Operation of jump instructions EPSON Program memory 0000H xxxxH JR %BA xxxxH+256 FFFFH xxxxH+1 BA=0 xxxxH+1 xxxxH+16 BA=255 xxxxH+256 Program memory 0000H JP %Y FFFFH Branch destination absolute address Indirect jump instruction S1C63000 CORE CPU MANUAL...

  • Page 21: Calr [Addr

    Figure 2.2.3.2 shows the operation of the call instructions and the branch range. Program memory 0000H xxxxH-32767 xxxxH-127 xxxxH CALR sign8 xxxxH+128 xxxxH+32768 FFFFH S1C63000 CORE CPU MANUAL 256) = 17800 Program memory Program memory 0000H xxxxH-1 %EXT,imm8 xxxxH CALR sign8 xxxxH CALR [addr6]...

  • Page 22: Table Look-Up Instruction

    ;Sets data to be converted CALR TOASCII ;Calls converting routine %BA,[%X]+ ;Loads result from memory to BA register Mainroutine Subroutine sign8 %A,[%X] RET (RETD) RETS Fig. 2.2.3.3 Return from subroutine EPSON NC,1 Return to xxxxH+1 Return to xxxxH+2 S1C63000 CORE CPU MANUAL...

  • Page 23: Data Memory

    4-bit microcomputers. The S1C63000 has a built-in 16-bit data bus for the address stack (SP1), and a RAM that permits 16-bit data accessing can be connected to the addresses 0000H to 03FFH. The 16-bit accessible area is different depending on the individual models.

  • Page 24: Addressing For Data Memory

    LD [%Y]+,[%X]+ LD [%Y],[%X] In addition, the S1C63000 has also provided instructions in order to efficiently access only the area which is accessed frequently such as the I/O memory and lower addresses. One of that is the addressing using the EXT register explained in Section 2.1.5.

  • Page 25: Stack And Stack Pointer

    0000H to 03FFH. The stack area can be set from an optional address (toward the lower address) using the stack pointer. The S1C63000 contains two stack pointers SP1 and SP2. (1) Stack pointer SP1 The SP1 is used for the address data stack, and permits 16-bit data accessing.
  • Page 26 Figure 2.3.3.4. The SP2 is decremented after the data is evacuated and is incremented when the data is returned. 8 bits to be modified Fig. 2.3.3.3 SP2 configuration EPSON Stack pointer 2 S1C63000 CORE CPU MANUAL...

  • Page 27: Memory Mapped I/O

    2.3.4 Memory mapped I/O The S1C63 Family contains the S1C63000 as the core CPU and various types of peripheral circuits, such as input/output ports. The S1C63000 has adopted a memory mapped I/O system for controlling the peripheral circuits, and the control bits and the registers for exchanging data are arranged in the data memory area.

  • Page 28: Cpu O

    1/2 cycle of the CLK and the one bus cycle that becomes the instruction execution unit is composed of four states. The clock that is input to the S1C63000 is generated by an oscillation circuit provided outside of the CPU. The S1C63 Family models have a built-in oscillation circuit.

  • Page 29: Data Bus (Data Memory) Control

    3.3.1 Data bus status The S1C63000 output the data bus status in each bus cycle externally on the DBS0 and DBS1 signals as a 2-bit status. The peripheral circuits perform the direction control of the bus driver and other controls with these signals.

  • Page 30: Interrupt Vector Read

    The S1C63000 contains a 4-bit data bus (D0–D3) and a 16-bit data bus (M00–M15) for an address stacking. The CPU switches the data bus according to the instruction. The BS16 signal is provided for this switch- ing.

  • Page 31: Memory Read

    3.4 Initial Reset The S1C63000 has a reset (SR) terminal in order to start the program after initializing the circuit when the power is turned on or other situations. The following explains the operation at an initial reset and the initial setting of the internal registers.

  • Page 32: Initial Setting Of Internal Registers

    When all the interrupt processing has finished, the interrupted program is resumed. The S1C63000 has the hardware interrupt function for the peripheral circuits including an NMI (non- maskable interrupt) and the hardware interrupt function. The hardware interrupts excluding the NMI can be set to the DI (disable interrupts) status by setting the I (interrupt) flag.

  • Page 33: Interrupt Sequence

    Further, these instructions may modify the content of the I flag. If these instructions set the I flag (EI status), the interrupt processing is done after executing the next instruction. If these instruc- tions reset the I flag (DI status), interrupts generated after the instruction fetch cycle are masked. S1C63000 CORE CPU MANUAL LDB %EXT,%BA %F,imm4...
  • Page 34 Fig. 3.5.2.1 NMI sequence (normal acceptance) In this chart, the dummy fetch cycle starts after fetching the "LD %A, [%X]" instruction that follows the "LDB %EXT, imm8" instruction. Fig. 3.5.2.2 NMI sequence (interrupt acceptance after 1 instruction) S1C63000 CORE CPU MANUAL...
  • Page 35 LDB %EXT,imm8 LD %A,[%X] FETCH BS16 DBS1/0 RDIV DA00–DA15 D0–D3 M00–M15 IACK NACK Interrupt sampling S1C63000 CORE CPU MANUAL 010xH (010xH) SP2-1 DUMMY SP1-1 F reg. Inte rrupt vector 010xH DUMMY (010xH) 00xxH SP2-1 DUMMY SP1-1 [00xxH] F reg.

  • Page 36: Notes For Interrupt Processing

    "1". Pay attention to the F register setting except when describing such a processing consciously. pc-1 pc+1 INT addr6 DUMMY SP2-1 DUMMY F reg. Fig. 3.5.2.5 Software interrupt sequence EPSON 01addr6H (01addr6H) SP1-1 pc+1 S1C63000 CORE CPU MANUAL...

  • Page 37: Standby Status

    3.6 Standby Status The S1C63000 has a function that stops the CPU operation and it can greatly reduce power consumption. This function should be used to stop the CPU when there is no processing to be executed in the CPU, example while the application program waits an interrupt.
  • Page 38 CLK and starts the interrupt processing. T2 T3 T4 T1T2 T3 T4 pc+1 DUMMY FETCH DBS1/0 STOP Oscillation stable waiting time SLEEP status Interrupt processing Fig. 3.6.2.1 Sequence of the shift to SLEEP status and restarting EPSON S1C63000 CORE CPU MANUAL...

  • Page 39: Chapter Instruction Set

    CHAPTER NSTRUCTION The S1C63000 offers high machine cycle efficiency and a high speed instruction set. It has 47 basic instructions (412 instructions in all) that are designed as an instruction system permitting relocatable programming. This chapter explains about the addressing modes for memory management and about the details of each instruction.
  • Page 40 Instructions which have [%X] or [%X]+ as the operand Instructions which have [%Y] or [%Y]+ as the operand ...Increments the content of a memory specified with the addr6 ...Decrements the content of a memory specified with the addr6 EPSON S1C63000 CORE CPU MANUAL...

  • Page 41: Extended Addressing Mode

    4.1.2 Extended addressing mode In the S1C63000, when data is written to the EXT register (the E flag is set) and a specific instruction follows, the data specified by that instruction is extended with the EXT register data (see Section 2.1.5).
  • Page 42 [%Y],%r %r,[%Y] [%X],%r [%Y],%r ...Works as "LD %A, [0x0037]" ...Works as "ADD [0xFF9C]" EPSON [%X],imm4 [%Y],imm4 [%X],imm4 [%Y],imm4 [%X],imm4 [%Y],imm4 [%Y],%B,n4 [%X],imm4 [%Y],imm4 [%X],imm4 [%Y],imm4 [%Y],%B,n4 [%X],imm4 [%Y],imm4 [%X],imm4 [%Y],imm4 [%X],imm4 [%Y],imm4 [%X],imm4 [%Y],imm4 [%X],imm4 [%Y],imm4 S1C63000 CORE CPU MANUAL...

  • Page 43: Instruction List

    Table 4.2.1.1 lists the function classifications of the instructions. Table 4.2.1.1 Instruction function classifications Function classification Mnemonic Arithmetic Logic Transfer S1C63000 CORE CPU MANUAL sign8 JRNC sign8 ...Works as "JR 0x6429" ...Works as "JR 0x3A88" ( = C, NC, Z, or NZ) ...Works as "CALR 0xF862" Operation...

  • Page 44: Symbol Meanings

    ... 6-bit address (00H to 3FH) a5–a0 ... Each bit in addr6 00addr6 ... addr6 which specifies an address within 0000H to 003FH FFaddr6 ... addr6 which specifies an address within FFC0H to FFFFH EPSON S1C63000 CORE CPU MANUAL...
  • Page 45 Operations and others + ... Addition - ... Subtraction Logical product Logical sum Exclusive OR Data load Data exchange Extended addressing mode (EXT.mode) ... Can be used Cannot be used (prohibit use) S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET EPSON...

  • Page 46: Instruction List By Function

    – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C63000 CORE CPU MANUAL...
  • Page 47 1 1 0 0 0 0 1 1 0 0 0 0 1 %A,[%Y] 1 1 0 0 0 0 1 1 0 0 0 1 0 %A,[%Y]+ 1 1 0 0 0 0 1 1 0 0 0 1 1 S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Operation A+imm4 A+[X]...
  • Page 48 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C63000 CORE CPU MANUAL...
  • Page 49 In the SBC and DEC instructions, the "n4" is placed as it is at the low-order 4 bits in the machine code. (However, when 16 is specified to n4, the machine code is generated with 0000H as the low-order 4 bits.) S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET...
  • Page 50 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C63000 CORE CPU MANUAL...
  • Page 51 [00addr6],imm2 1 0 0 1 0 i1 i0 a5 a4 a3 a2 a1 a0 [FFaddr6],imm2 1 0 0 1 1 i1 i0 a5 a4 a3 a2 a1 a0 S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Operation A imm4 A [X]...
  • Page 52 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C63000 CORE CPU MANUAL Page Page...
  • Page 53 • X in the machine code row indicates that the bit is valid even though it is "0" or "1", but the assembler generates it as "0". When entering the code directly, such as for debugging, "0" should be entered. S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Operation...

  • Page 54: List In Alphabetical Order

    – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C63000 CORE CPU MANUAL...
  • Page 55 [%Y],%A 1 1 0 1 0 1 1 1 0 1 0 1 0 [%Y],%B 1 1 0 1 0 1 1 1 0 1 1 1 0 S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Operation [X]+imm4 [X]+A, X...
  • Page 56 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C63000 CORE CPU MANUAL...
  • Page 57 %BA,%XH 1 1 1 1 1 1 1 0 0 1 0 0 1 %BA,%XL 1 1 1 1 1 1 1 0 0 1 0 0 0 S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Operation N's adjust ([X]+1)
  • Page 58 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C63000 CORE CPU MANUAL...
  • Page 59 1 0 1 1 1 i1 i0 a5 a4 a3 a2 a1 a0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 S1C63000 CORE CPU MANUAL CHAPTER 4: INSTRUCTION SET Operation...
  • Page 60 – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C63000 CORE CPU MANUAL...

  • Page 61: List Of Extended Addressing Instructions

    %EXT,imm8 %A,[%Y] %EXT,imm8 %B,[%X] %EXT,imm8 %B,[%Y] %EXT,imm8 [%X],%A %EXT,imm8 [%X],%B %EXT,imm8 [%X],imm4 S1C63000 CORE CPU MANUAL Operation [00imm8] (00imm8 = 0000H ~ 00FFH) [FFimm8] (FFimm8 = FF00H + 00H ~ FFH) [00imm8] [FFimm8] [00imm8] [00imm8] [00imm8] imm4 [FFimm8] [FFimm8] [FFimm8]...
  • Page 62 E I C Z – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – S1C63000 CORE CPU MANUAL...
  • Page 63 [%X],%A %EXT,imm8 [%X],%B %EXT,imm8 [%X],imm4 S1C63000 CORE CPU MANUAL Operation N's adjust (B + [00imm8] + C) (00imm8 = 0000H ~ 00FFH) N's adjust (B + [FFimm8] + C) (FFimm8 = FF00H + 00H ~ FFH) [00imm8] N's adjust ( [00imm8] + B + C)
  • Page 64 [00imm8] (C [FFimm8] (C [00imm8] (0 [FFimm8] (0 [00imm8] (C [FFimm8] (C [00imm8] (C [FFimm8] (C EPSON S1C63000 CORE CPU MANUAL Flag E I C Z – – – – – – – – – – – – – –...

  • Page 65: Instruction Formats

    %EXT,imm8 CALR sign8 4.3 Instruction Formats All the instructions of the S1C63000 are configured with 1 word (13 bits) as follows: 13-bit operation code 9-bit operation code + 4-bit immediate data OP Code 7-bit operation code + 6-bit immediate data...

  • Page 66: Detailed Explanation Of Instructions

    1 1 0 0 1 1 1 1 1 0 1 1 X Status of the flag – EPSON Number of bus cycles 1 cycle 19F0H, (19F1H) 19F2H, (19F3H) 19F4H, (19F5H) 19F6H, (19F7H) – Does not change Reset Set/reset S1C63000 CORE CPU MANUAL...

  • Page 67: Adc %R,%R

    Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 0 1 1 1 1 1 0 0 0 X 1 1 0 0 1 1 1 1 1 0 0 1 X 1 1 0 0 1 1 1 1 1 0 1 0 X 1 1 0 0 1 1 1 1 1 0 1 1 X 1 1 0 0 1 1 1 0 0 i3 i2 i1 i0 19C0H–19CFH...

  • Page 68: Adc %R,[%Ir

    1 1 0 0 1 1 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 0 0 1 1 1 EPSON 1 cycle 19E0H 19E2H 19E4H 19E6H 1 cycle 19E1H 19E3H 19E5H 19E7H S1C63000 CORE CPU MANUAL...

  • Page 69: Adc [%Ir],%R

    Mode: Dst: Register indirect Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 0 1 0...

  • Page 70: Adc [%Ir]+,Imm

    [FFimm8] + imm4 + C (FFimm8 = FF00H + 00H to FFH) ir + 1 1 1 0 0 1 1 0 0 1 i3 i2 i1 i0 1990H–199FH 1 1 0 0 1 1 0 1 1 i3 i2 i1 i0 19B0H–19BFH EPSON 2 cycles S1C63000 CORE CPU MANUAL...

  • Page 71: Adc %B,%A,N

    ADC %B,[%Y],n4 n4 should be specified with a value from 1 to 16. Note: S1C63000 CORE CPU MANUAL 1 0 0 0 0 1 1 0 1 1 1 1 0 1 1 1 0 0 1 1 1 0 1 1 1 1 0 N’s adjust (B + [00imm8] + C) (00imm8 = 0000H + 00H to FFH)

  • Page 72: Adc [%Ir],%B,N

    N’s adjust ([00imm8] + B + C) (00imm8 = 0000H + 00H to FFH) [FFimm8] N’s adjust ([FFimm8] + B + C) (FFimm8 = FF00H + 00H to FFH) EPSON [10H-n4] 1DD0H–1DDFH [10H-n4] 1DF0H–1DFFH [10H-n4] 1D40H–1D4FH [10H-n4] 1D60H–1D6FH S1C63000 CORE CPU MANUAL 2 cycles...
  • Page 73 %EXT,imm8 ADC [%Y],0,n4 n4 should be specified with a value from 1 to 16. Note: S1C63000 CORE CPU MANUAL ir + 1 1 1 1 0 1 0 0 0 0 1 1 1 0 1 0 0 1 0 [00imm8] N’s adjust ([00imm8] + 0 + C)
  • Page 74 1 1 0 0 1 0 1 1 1 0 1 0 X 1 1 0 0 1 0 1 1 1 0 1 1 X EPSON [10H-n4] 1D10H–1D1FH [10H-n4] 1D30H–1D3FH 1970H, (1971H) 1972H, (1973H) 1974H, (1975H) 1976H, (1977H) S1C63000 CORE CPU MANUAL 1 cycle...

  • Page 75: Add %R,Imm

    ADD %r,[%X] %EXT,imm8 ADD %r,[%Y] S1C63000 CORE CPU MANUAL 1 1 0 0 1 0 1 0 0 i3 i2 i1 i0 1940H–194FH 1 1 0 0 1 0 1 0 1 i3 i2 i1 i0 1950H–195FH 1 1 0 0 1 0 1 1 0 0 0 0 0...

  • Page 76: Add [%Ir],%R

    1 1 0 0 1 0 1 1 0 1 1 1 0 [00imm8] [00imm8] + r (00imm8 = 0000H + 00H to FFH) [FFimm8] [FFimm8] + r (FFimm8 = FF00H + 00H to FFH) EPSON 1 cycle 1961H 1963H 1965H 1967H 2 cycles 1968H 196CH 196AH 196EH S1C63000 CORE CPU MANUAL...

  • Page 77: Add [%Ir],Imm

    ADD [%X],imm4 %EXT,imm8 ADD [%Y],imm4 S1C63000 CORE CPU MANUAL 1 1 0 0 1 0 1 1 0 1 0 0 1 1 1 0 0 1 0 1 1 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 1 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 i3 i2 i1 i0 1900H–190FH...
  • Page 78 1 1 0 0 1 0 0 1 1 i3 i2 i1 i0 1930H–193FH 1 1 1 1 1 1 1 0 1 0 0 0 X 1 1 1 1 1 1 1 0 1 0 0 1 X EPSON 1 cycle 1FD0H, (1FD1H) 1FD2H, (1FD3H) S1C63000 CORE CPU MANUAL...

  • Page 79: Add %Ir,Sign

    Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 0 1 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 0C00H–0CFFH 0 1 1 0 1 s7 s6 s5 s4 s3 s2 s1 s0 0D00H–0DFFH ir + sign16 (upper 8-bit: imm8, lower 8-bit: sign8)
  • Page 80 1 1 0 1 0 0 1 0 0 i3 i2 i1 i0 1A40H–1A4FH 1 1 0 1 0 0 1 0 1 i3 i2 i1 i0 1A50H–1A5FH 1 0 0 0 0 1 0 0 0 i3 i2 i1 i0 1080H–108FH EPSON 1 cycle 1 cycle S1C63000 CORE CPU MANUAL...
  • Page 81 Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 1 0 0 1 1 0 0 0 0 0 1 1 0 1 0 0 1 1 0 0 0 1 0 1 1 0 1 0 0 1 1 0 0 1 0 0...
  • Page 82 1 1 0 1 0 0 1 1 0 1 0 1 1 1 1 0 1 0 0 1 1 0 1 1 1 1 EPSON 2 cycles 1A68H 1A6CH 1A6AH 1A6EH 1A69H 1A6DH 1A6BH 1A6FH S1C63000 CORE CPU MANUAL...

  • Page 83: And [%Ir]+,Imm

    Mode: Dst: Register indirect Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 1 0 0 0 0 0 i3 i2 i1 i0 1A00H–1A0FH 1 1 0 1 0 0 0 1 0 i3 i2 i1 i0 1A20H–1A2FH [00imm8]...

  • Page 84: Bit %R,%R

    1 1 0 1 0 1 1 0 0 i3 i2 i1 i0 1AC0H–1ACFH 1 1 0 1 0 1 1 0 1 i3 i2 i1 i0 1AD0H–1ADFH EPSON 1 cycle 1AF0H, (1AF1H) 1AF2H, (1AF3H) 1AF4H, (1AF5H) 1AF6H, (1AF7H) 1 cycle S1C63000 CORE CPU MANUAL...
  • Page 85 Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 1 0 1 1 1 0 0 0 0 0 1 1 0 1 0 1 1 1 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 1 0 0...
  • Page 86 1 1 0 1 0 1 1 1 0 1 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 EPSON 1 cycle 1AE8H 1AECH 1AEAH 1AEEH 1 cycle 1AE9H 1AEDH 1AEBH 1AEFH S1C63000 CORE CPU MANUAL...
  • Page 87 Mode: Dst: Register indirect Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 1 0 1 0 0 0 i3 i2 i1 i0 1A80H–1A8FH 1 1 0 1 0 1 0 1 0 i3 i2 i1 i0 1AA0H–1AAFH [00imm8]...
  • Page 88 (sign16 = -32768 to 32767, upper 8-bit: imm8, lower 8-bit: sign8) EPSON PC + [addr6] + 1 PC + sign8 + 1 (sign8 = -128~127) PC + 1, SP1 SP1 - 1, S1C63000 CORE CPU MANUAL 2 cycles 1 cycle...
  • Page 89 – – Src: Immediate data Mode: Dst: 6-bit absolute Extended addressing: Invalid S1C63000 CORE CPU MANUAL PC + 1, SP1 SP1 - 1, PC 0 0 0 1 1 i7 i6 i5 i4 i3 i2 i1 i0 0300H–03FFH – imm2...

  • Page 90: Cmp %R,%R

    1 1 1 1 0 0 1 0 0 i3 i2 i1 i0 1E40H–1E4FH 1 1 1 1 0 0 1 0 1 i3 i2 i1 i0 1E50H–1E5FH EPSON 1 cycle 1E70H, (1E78H) 1E72H, (1E7AH) 1E74H, (1E7CH) 1E76H, (1E7EH) 1 cycle S1C63000 CORE CPU MANUAL...
  • Page 91 Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 0 0 1 0 0...
  • Page 92 1 1 1 1 0 0 1 1 0 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 EPSON 1 cycle 1E68H 1E6CH 1E6AH 1E6EH 1 cycle 1E69H 1E6DH 1E6BH 1E6FH S1C63000 CORE CPU MANUAL...
  • Page 93 Mode: Dst: Register indirect Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 1 1 0 0 0 0 0 i3 i2 i1 i0 1E00H–1E0FH 1 1 1 1 0 0 0 1 0 i3 i2 i1 i0 1E20H–1E2FH [00imm8] - imm4 (00imm8 = 0000H + 00H to FFH) [FFimm8] - imm4 (FFimm8 = FF00H + 00H to FFH) 1 1 1 1 0 0 0 0 1 i3 i2 i1 i0 1E10H–1E1FH...

  • Page 94: Cmp %Ir,Imm

    0 1 1 1 1 FFH-imm8 ir - imm16 (upper 8-bit: FFH - imm8, lower 8-bit: imm8') 1 0 0 0 0 0 0 a5 a4 a3 a2 a1 a0 1000H–103FH EPSON 1 cycle 0E00H–0EFFH 0F00H–0FFFH 2 cycles S1C63000 CORE CPU MANUAL...
  • Page 95 1 to 16. When 16 is specified for n4, the low-order 4 bits of the machine code (n3–n0) become 0000B. S1C63000 CORE CPU MANUAL 1 1 1 0 0 1 0 0 0 n3 n2 n1 n0 1C80H–1C8FH 1 1 1 0 0 1 0 1 0 n3 n2 n1 n0 1CA0H–1CAFH...

  • Page 96: Dec %Sp

    1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 – EPSON 1 cycle 1FE0H 1FE4H 1 cycle 1FF7H S1C63000 CORE CPU MANUAL...

  • Page 97: Ex %R,[%Ir

    Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 0 0 0 0 1 1 1 1 1 0 0 0 1 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 1 1 1 1 1 1 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 –...
  • Page 98 Extended addressing: Invalid 1 1 1 1 1 1 1 1 1 1 1 0 0 – 1 0 0 0 0 0 1 a5 a4 a3 a2 a1 a0 1040H–107FH EPSON 2 cycles 1FFCH 2 cycles S1C63000 CORE CPU MANUAL...
  • Page 99 Dst: Register indirect Extended addressing: Invalid Note: n4 should be specified with a value from 1 to 16. S1C63000 CORE CPU MANUAL 1 1 1 0 1 1 0 0 0 1 1 1 0 1 1 0 1 0 [00imm8] N’s adjust ([00imm8] + 1) (00imm8 = 0000H + 00H to FFH)
  • Page 100 1 1 1 1 1 1 1 1 0 1 1 0 0 1 1 1 1 1 1 0 i5 i4 i3 i2 i1 i0 1F80H–1FBFH – EPSON 1 cycle 1FE8H 1FECH 3 cycles PC + 1, SP1 SP1 - 1, PC imm6 S1C63000 CORE CPU MANUAL...

  • Page 101: Jp %Y

    – – Register direct Mode: Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 1 1 1 1 1 1 1 0 0 1 X – 1 1 1 1 1 1 1 1 1 0 0 0 1 –...
  • Page 102 Extended addressing: Invalid 1 1 1 1 1 1 1 1 1 0 0 0 0 – 1 1 1 1 1 0 1 a5 a4 a3 a2 a1 a0 1F40H–1F7FH – EPSON 1 cycle 1FF0H 2 cycles S1C63000 CORE CPU MANUAL...
  • Page 103 Extended LDB %EXT,imm8 operation: JRC sign8 S1C63000 CORE CPU MANUAL 0 0 0 0 0 s7 s6 s5 s4 s3 s2 s1 s0 0000H–00FFH – PC + sign16 + 1 (sign16 = -32768 to 32767, upper 8-bit: imm8, lower 8-bit: sign8) 0 0 1 0 0 s7 s6 s5 s4 s3 s2 s1 s0 0400H–04FFH...

  • Page 104: Jrnc Sign

    0 0 1 1 1 s7 s6 s5 s4 s3 s2 s1 s0 0700H–07FFH – If Z = 0 then PC PC + sign16 + 1 (sign16 = -32768 to 32767, upper 8-bit: imm8, lower 8-bit: sign8) EPSON 1 cycle 1 cycle S1C63000 CORE CPU MANUAL...
  • Page 105 Src: Register direct Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 0 0 1 1 0 s7 s6 s5 s4 s3 s2 s1 s0 0600H–06FFH – If Z = 1 then PC PC + sign16 + 1...

  • Page 106: Ld %R,Imm

    1 1 1 1 0 1 1 1 0 0 1 1 0 – [00imm8] (00imm8 = 0000H + 00H to FFH) [FFimm8] (FFimm8 = FF00H + 00H to FFH) EPSON 1 cycle 1 cycle 1EE0H 1EE2H 1EE4H 1EE6H S1C63000 CORE CPU MANUAL...
  • Page 107 [%X],%r %EXT,imm8 [%Y],%r S1C63000 CORE CPU MANUAL 1 1 1 1 0 1 1 1 0 0 0 0 1 1 1 1 1 0 1 1 1 0 0 0 1 1 1 1 1 1 0 1 1 1 0 0 1 0 1 1 1 1 1 0 1 1 1 0 0 1 1 1 –...

  • Page 108: Ld [%Ir],Imm

    1 1 1 1 0 1 0 1 0 i3 i2 i1 i0 1EA0H–1EAFH – [00imm8] imm4 (00imm8 = 0000H + 00H to FFH) [FFimm8] imm4 (FFimm8 = FF00H + 00H to FFH) EPSON 1 cycle 1EE9H 1EEDH 1EEBH 1EEFH 1 cycle S1C63000 CORE CPU MANUAL...
  • Page 109 Mode: Dst: Register indirect Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 1 1 0 1 0 0 1 i3 i2 i1 i0 1E90H–1E9FH 1 1 1 1 0 1 0 1 1 i3 i2 i1 i0 1EB0H–1EBFH –...
  • Page 110 1 1 1 1 0 1 1 1 1 1 0 0 1 – 1 1 1 1 0 1 1 1 1 1 1 1 0 1 1 1 1 0 1 1 1 1 1 1 0 0 – EPSON 1EFBH 1EF9H 1EFEH 1EFCH S1C63000 CORE CPU MANUAL...
  • Page 111 Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL ir’ + 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 –...

  • Page 112: Ldb %Ba,[%Ir

    1 1 1 1 1 1 1 0 1 1 0 1 0 – 1 1 1 1 1 1 1 0 1 0 1 1 X – EPSON 2 cycles 1FD8H 1FDAH 1 cycle 1FD6H, (1FD7H) S1C63000 CORE CPU MANUAL...

  • Page 113: Ldb %Ba,%Rr

    Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 1 1 1 1 1 0 0 1 0 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 1 1 1 1 1 1 0 0 1 0 1 0 1 1 1 1 1 1 1 0 0 1 0 1 1 –...
  • Page 114 1 1 1 1 1 1 1 0 1 1 0 1 1 – X + 2 0 0 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0 0100H–01FFH – EPSON 2 cycles 1FD9H 1FDBH S1C63000 CORE CPU MANUAL...

  • Page 115: Ldb %Ext,Imm

    Src: Register direct Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 0 1 0 0 0 i7 i6 i5 i4 i3 i2 i1 i0 0800H–08FFH – 1 1 1 1 1 1 1 0 1 0 1 0 X –...

  • Page 116: Ldb %Rr,Imm

    1 1 1 1 1 1 1 0 0 0 0 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 – EPSON 1 cycle 1 cycle 1FC0H 1FC1H 1FC2H 1FC3H S1C63000 CORE CPU MANUAL...

  • Page 117: Ldb %Sp,%Ba

    Code: Mnemonic Flags: – – S1C63000 CORE CPU MANUAL 1 1 1 1 1 1 1 0 0 0 1 0 X 1 1 1 1 1 1 1 0 0 0 1 1 X – PC+1) 1 1 1 1 1 1 1 1 1 1 1 1 X –...

  • Page 118: Or %R,%R

    1 1 0 1 1 0 1 0 0 i3 i2 i1 i0 1B40H–1B4FH 1 1 0 1 1 0 1 0 1 i3 i2 i1 i0 1B50H–1B5FH EPSON 1 cycle 1B70H, (1B71H) 1B72H, (1B73H) 1B74H, (1B75H) 1B76H, (1B77H) 1 cycle S1C63000 CORE CPU MANUAL...

  • Page 119: Or %F,Imm

    %r,[%X] %EXT,imm8 %r,[%Y] S1C63000 CORE CPU MANUAL 1 0 0 0 0 1 0 0 1 i3 i2 i1 i0 1090H–109FH 1 1 0 1 1 0 1 1 0 0 0 0 0 1 1 0 1 1 0 1 1 0 0 0 1 0...
  • Page 120 1 1 0 1 1 0 1 1 0 1 1 1 0 [00imm8] [00imm8] r (00imm8 = 0000H + 00H to FFH) [FFimm8] [FFimm8] r (FFimm8 = FF00H + 00H to FFH) EPSON 1 cycle 1B61H 1B63H 1B65H 1B67H 2 cycles 1B68H 1B6CH 1B6AH 1B6EH S1C63000 CORE CPU MANUAL...
  • Page 121 [%X],imm4 %EXT,imm8 [%Y],imm4 S1C63000 CORE CPU MANUAL 1 1 0 1 1 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 1 1 0 0 0 0 i3 i2 i1 i0 1B00H–1B0FH...
  • Page 122 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1 0 1 1 0 1 – (r = A, B) (r = F) EPSON 1 cycle 1FEFH 1FEEH 1FEDH S1C63000 CORE CPU MANUAL...

  • Page 123: Pop %Ir

    – Register direct Mode: Extended addressing: Invalid S1C63000 CORE CPU MANUAL SP1 +1 1 1 1 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 X –...

  • Page 124: Push %Ir

    1 1 1 1 1 1 1 1 0 0 0 1 X – SP1 +1 1 1 1 1 1 1 1 1 1 1 0 X 0 – EPSON 1 cycle 1FE1H 1FE2H, (1FE3H) 1 cycle 1FF8H, (1FFAH) S1C63000 CORE CPU MANUAL...
  • Page 125 SP2 into the F register, then increments the SP2. This instruction is used for returning from interrupt routines. Code: Mnemonic RETI Flags: S1C63000 CORE CPU MANUAL SP1 +1, [X] i3-0, [X+1] 1 0 0 0 1 i7 i6 i5 i4 i3 i2 i1 i0 1100H–11FFH – SP1 +1, F...
  • Page 126 1 1 1 1 1 1 1 1 1 1 0 1 1 – 1 0 0 0 0 1 1 1 1 0 0 1 0 1 0 0 0 0 1 1 1 1 0 1 1 0 EPSON 2 cycles 1FFBH 1 cycle 10F2H 10F6H S1C63000 CORE CPU MANUAL...
  • Page 127 Register indirect Mode: Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 0 0 0 0 1 1 1 0 1 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 Rotates the content of [00imm8] (00imm8 = 0000H + 00H to FFH)
  • Page 128 1 0 0 0 0 1 1 1 0 1 1 1 0 Rotates the content of [00imm8] (00imm8 = 0000H + 00H to FFH) Rotates the content of [FFimm8] (FFimm8 = FF00H + 00H to FFH) EPSON 1 cycle 10F3H 10F7H 2 cycles 10ECH 10EEH S1C63000 CORE CPU MANUAL...

  • Page 129: Rr [%Ir

    Src: Register direct Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL ir +1 1 0 0 0 0 1 1 1 0 1 1 0 1 1 0 0 0 0 1 1 1 0 1 1 1 1...

  • Page 130: Sbc %R,Imm

    1 1 0 0 0 1 1 1 0 0 1 1 0 r - [00imm8] - C (00imm8 = 0000H + 00H to FFH) r - [FFimm8] - C (FFimm8 = FF00H + 00H to FFH) EPSON 1 cycle 1 cycle 18E0H 18E2H 18E4H 18E6H S1C63000 CORE CPU MANUAL...

  • Page 131: Sbc [%Ir],%R

    [%X],%r %EXT,imm8 [%Y],%r S1C63000 CORE CPU MANUAL 1 1 0 0 0 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 1 1 1 0 0 1 0 1...

  • Page 132: Sbc [%Ir],Imm

    1 1 0 0 0 1 0 1 0 i3 i2 i1 i0 18A0H–18AFH [00imm8] [00imm8] - imm4 - C (00imm8 = 0000H + 00H to FFH) [FFimm8] [FFimm8] - imm4 - C (FFimm8 = FF00H + 00H to FFH) EPSON 18E9H 18EDH 18EBH 18EFH 2 cycles S1C63000 CORE CPU MANUAL...
  • Page 133 1 to 16. When 16 is specified for n4, the low-order 4 bits of the machine code (n3–n0) become 0000B. S1C63000 CORE CPU MANUAL ir + 1 1 1 0 0 0 1 0 0 1 i3 i2 i1 i0 1890H–189FH 1 1 0 0 0 1 0 1 1 i3 i2 i1 i0 18B0H–18BFH...
  • Page 134 1 1 1 0 0 1 1 1 0 n3 n2 n1 n0 1CE0H–1CEFH N’s adjust (B - [00imm8] - C) (00imm8 = 0000H + 00H to FFH) N’s adjust (B - [FFimm8] - C) (FFimm8 = FF00H + 00H to FFH) ir + 1 EPSON S1C63000 CORE CPU MANUAL...
  • Page 135 1 to 16. When 16 is specified for n4, the low-order 4 bits of the machine code (n3–n0) become 0000B. S1C63000 CORE CPU MANUAL 1 1 1 0 0 0 1 0 0 n3 n2 n1 n0 1C40H–1C4FH 1 1 1 0 0 0 1 1 0 n3 n2 n1 n0 1C60H–1C6FH...
  • Page 136 N’s adjust ([FFimm8] - 0 - C) (FFimm8 = FF00H + 00H to FFH) ir + 1 1 1 1 0 0 0 0 0 1 n3 n2 n1 n0 1C10H–1C1FH 1 1 1 0 0 0 0 1 1 n3 n2 n1 n0 1C30H–1C3FH EPSON 2 cycles S1C63000 CORE CPU MANUAL...
  • Page 137 Flags: – Register direct Mode: Extended addressing: Invalid S1C63000 CORE CPU MANUAL imm2 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 1 0 1 0 0 EPSON...
  • Page 138 + 1 1 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 0 0 0 1 1 EPSON 2 cycles 10E0H 10E2H 2 cycles 10E1H 10E3H S1C63000 CORE CPU MANUAL...
  • Page 139 – Register direct Mode: Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 1 1 1 1 1 1 1 1 1 0 1 – 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1...
  • Page 140 + 1 1 0 0 0 0 1 1 1 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 1 1 1 EPSON 2 cycles 10E4H 10E6H 2 cycles 10E5H 10E7H S1C63000 CORE CPU MANUAL...

  • Page 141: Sub %R,%R

    Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 0 0 0 1 1 1 0 0 0 X 1 1 0 0 0 0 1 1 1 0 0 1 X 1 1 0 0 0 0 1 1 1 0 1 0 X 1 1 0 0 0 0 1 1 1 0 1 1 X r’)

  • Page 142: Sub %R,[%Ir

    1 1 0 0 0 0 1 1 0 0 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 EPSON 1 cycle 1860H 1862H 1864H 1866H 1 cycle 1861H 1863H 1865H 1867H S1C63000 CORE CPU MANUAL...

  • Page 143: Sub [%Ir],%R

    Mode: Dst: Register indirect Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 1 0...

  • Page 144: Sub [%Ir]+,Imm

    [FFimm8] - imm4 (FFimm8 = FF00H + 00H to FFH) ir + 1 1 1 0 0 0 0 0 0 1 i3 i2 i1 i0 1810H–181FH 1 1 0 0 0 0 0 1 1 i3 i2 i1 i0 1830H–183FH EPSON 2 cycles S1C63000 CORE CPU MANUAL...

  • Page 145: Tst [Addr6],Imm

    Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 1 1 1 1 1 1 0 0 0 X 1 1 0 1 1 1 1 1 1 0 0 1 X 1 1 0 1 1 1 1 1 1 0 1 0 X 1 1 0 1 1 1 1 1 1 0 1 1 X r’)
  • Page 146 1 1 0 1 1 1 1 0 0 i3 i2 i1 i0 1BC0H–1BCFH 1 1 0 1 1 1 1 0 1 i3 i2 i1 i0 1BD0H–1BDFH 1 0 0 0 0 1 0 1 0 i3 i2 i1 i0 10A0H–10AFH EPSON 1 cycle 1 cycle S1C63000 CORE CPU MANUAL...
  • Page 147 Mode: Dst: Register direct Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 1 1 1 0 0 0 1 0 1 1 0 1 1 1 1 1 0 0 1 0 0...
  • Page 148 1 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 1 1 1 1 1 0 1 1 1 1 EPSON 2 cycles 1BE8H 1BECH 1BEAH 1BEEH 2 cycles 1BE9H 1BEDH 1BEBH 1BEFH S1C63000 CORE CPU MANUAL...

  • Page 149: Xor [%Ir]+,Imm

    Mode: Dst: Register indirect Extended addressing: Invalid S1C63000 CORE CPU MANUAL 1 1 0 1 1 1 0 0 0 i3 i2 i1 i0 1B80H–1B8FH 1 1 0 1 1 1 0 1 0 i3 i2 i1 i0 1BA0H–1BAFH [00imm8]...
  • Page 150 RR %r ... 122 RR [%ir] ... 122 RR [%ir]+ ... 123 SBC %r,%r’ ... 123 EPSON S1C63000 CORE CPU MANUAL SBC %r,imm4 ... 124 SBC %r,[%ir] ... 124 SBC %r,[%ir]+ ... 125 SBC [%ir],%r ... 125 SBC [%ir]+,%r ... 126 SBC [%ir],imm4 ...
  • Page 151 EPSON HONG KONG LTD. 20/F., Harbour Centre, 25 Harbour Road Wanchai, Hong Kong Phone: +852-2585-4600 Fax: +852-2827-4346 Telex: 65542 EPSCO HX EPSON TAIWAN TECHNOLOGY & TRADING LTD. 10F, No. 287, Nanking East Road, Sec. 3 Taipei Phone: 02-2717-7360 Fax: 02-2712-9164 Telex: 24444 EPSONTB HSINCHU OFFICE 13F-3, No.
  • Page 152 In pursuit of “Saving” Technology, Epson electronic devices. Our lineup of semiconductors, liquid crystal displays and quartz devices assists in creating the products of our customers’ dreams. Epson IS energy savings.
  • Page 153 S1C63000 Core CPU Manual ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http://www.epson.co.jp/device/ First issue July, 1995 Printed February, 2001 in Japan...

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