Page 1 FUJITSU SEMICONDUCTOR CM44-10136-1E CONTROLLER MANUAL -16LX 16-BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL...
Page 3 -16LX 16-BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL FUJITSU LIMITED...
Page 5 This manual explains the functions and operation of the MB90360 series for engineers who actually use the MB90360 series to design products. Please read this manual first. Trademark MC, an abbreviation of FUJITSU Flexible Microcontroller, is a registered trademark of FUJITSU Ltd. Embedded Algorithm is a registered trademark of Advanced Micro Devices Inc.
Page 6 CHAPTER 10 I/O PORTS This chapter explains the functions and operations of the I/O ports. CHAPTER 11 TIMEBASE TIMER This chapter explains the functions and operations of the timebase timer. CHAPTER 12 WATCHDOG TIMER This chapter describes the function and operation of the watchdog timer. CHAPTER 13 16-Bit I/O TIMER This chapter explains the function and operation of the 16- bit I/O timer.
Page 7 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION This chapter shows an example of a serial programming connection using the AF220/AF210/ AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer Corporation when the AF220/AF210/AF120/AF110 flash serial microcontroller programer from Yokogawa Digital Computer Corporation is used.
Page 8 (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.
Page 9: Table Of Contents
CONTENTS CHAPTER 1 OVERVIEW ... 1 Overview of MB90360 ... 2 Block Diagram of MB90360 series ... 9 Package Dimensions ... 12 Pin Assignment ... 13 Pin Functions ... 14 Input-Output Circuits ... 17 Handling Device ... 21 CHAPTER 2 CPU ...
Page 10 CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE ... 83 Overview of Delayed Interrupt Generation Module ... 84 Block Diagram of Delayed Interrupt Generation Module ... 85 Configuration of Delayed Interrupt Generation Module ... 86 4.3.1 Delayed interrupt request generate/cancel register (DIRR) ... 87 Explanation of Operation of Delayed Interrupt Generation Module ...
Page 11 CHAPTER 9 MEMORY ACCESS MODES ... 161 Outline of Memory Access Modes ... 162 9.1.1 Mode Pins ... 163 9.1.2 Mode Data ... 164 9.1.3 Memory Space in Each Bus Mode ... 165 CHAPTER 10 I/O PORTS ... 167 10.1 I/O Ports ...
Page 12 13.5 Explanation of Operation of 16-bit Free-run Timer ... 229 13.6 Explanation of Operation of Input Capture ... 231 13.7 Precautions when Using 16-bit I/O Timer ... 233 13.8 Program Example of 16-bit I/O Timer ... 234 CHAPTER 14 16-BIT RELOAD TIMER ... 237 14.1 Overview of the 16-bit Reload Timer ...
Page 13 CHAPTER 17 DTP/EXTERNAL INTERRUPTS ... 313 17.1 Overview of DTP/External Interrupt ... 314 17.2 Block Diagram of DTP/External Interrupt ... 315 17.3 Configuration of DTP/External Interrupt ... 317 17.3.1 DTP/External Interrupt Factor Register (EIRR1) ... 319 17.3.2 DTP/External Interrupt Enable Register (ENIR1) ... 321 17.3.3 Detection Level Setting Register (ELVR1) ...
Page 14 20.4.2 LIN-UART Serial Mode Register (SMR) ... 395 20.4.3 Serial Status Register (SSR) ... 397 20.4.4 Reception and Transmission Data Register (RDR/TDR) ... 399 20.4.5 Extended Status/Control Register (ESCR) ... 401 20.4.6 Extended Communication Control Register (ECCR) ... 403 20.4.7 Baud Rate Generator Register 0 and 1 (BGR0/1) ...
Page 15 21.4.20 Reception Interrupt Enable Register (RIER) ... 476 21.4.21 Acceptance Mask Select Register (AMSR) ... 477 21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) ... 479 21.4.23 Message Buffers ... 481 21.4.24 ID Register x (x = 0 to 15) (IDRx) ... 483 21.4.25 DLC Register x (x = 0 to 15) (DLCRx) ...
Page 16 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S)SERIAL PROGRAMMING CONNECTION ... 553 25.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) ... 554 25.2 Example of Serial Programming Connection (User Power Supply Used) ... 557 25.3 Example of Serial Programming Connection (Power Supplied from Programmer) ... 559 25.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used) ...
Page 17: Chapter 1 Overview
CHAPTER 1 OVERVIEW The MB90360 Series is a family member of the F 16LX micro controllers. 1.1 Overview of MB90360 1.2 Block Diagram of MB90360 series 1.3 Package Dimensions 1.4 Pin Assignment 1.5 Pin Functions 1.6 Input-Output Circuits 1.7 Handling Device...
Page 18: Overview Of Mb90360
CHAPTER 1 OVERVIEW Overview of MB90360 The MB90360 Series is a 16-bit microcontroller designed for automotive applications and contains CAN function, capture, compare timer, A/D converter, and so on. Features of MB90360 Series MB90360 series has the following features: Clock •...
Page 19 CPU-independent automatic data transfer function Extended intelligent I/O service (EI Lower-power consumption (standby) modes • Sleep mode (stops CPU clock) • Timebase timer mode (operates only oscillation clock and subclock, timebase timer and watch timer) • Watch mode (product without S-suffix operates only subclock and watch timer) •...
Page 20 CHAPTER 1 OVERVIEW Delayed interrupt generation module Generates interrupt request for task switching 8-/10-bit A/D converter: 16 channels • 8-bit and 10-bit resolutions • Start by external trigger input • Conversion time: 3 µs (including sampling time at 24-MHz machine clock frequency) Program patch function Detects address match for six address pointers Low voltage/CPU operation detection reset function (product with T-suffix)
Page 21: Product Overview
Product overview Table 1.1-1 Product Overview (1/2) Features System clock pin Sub clock pin (X0A, X1A) Clock supervisor RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Power supply for emulator* Corresponding EVA product name *: It is setting of Jumper switch (TOOL V ware manual.
Page 22 CHAPTER 1 OVERVIEW Table 1.1-2 Product Overview (2/2) Features System clock pin Sub clock pin (X0A, X1A) Clock supervisor RAM capacitance CAN interface Low voltage/CPU operation detection reset Package Power supply for emulator* Corresponding EVA product name *: It is setting of Jumper switch (TOOL V ware manual.
Page 23 Features Table 1.1-3 MB90360 Features (1/2) MB90F362/T(S), MB90362/T(S) Features MB90F367/T(S), MB90367/T(S) UART Wide range of baud rate settings using a dedicated reload timer LIN functionality working either as LIN master or LIN slave device A/D converter 10-bit or 8-bit resolution Conversion time: Minimum 3 µs include sample time (per one channel) 16-bit reload timer Operation clock frequency: fsys/2...
Page 24 CHAPTER 1 OVERVIEW Table 1.1-3 MB90360 Features (2/2) MB90F362/T(S), MB90362/T(S) Features MB90F367/T(S), MB90367/T(S) CAN interface Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame 16 message buffers for transmission/reception Supports multiple messages Flexible configuration of acceptance filtering: •...
Page 25: Block Diagram Of Mb90360 Series
Block Diagram of MB90360 series Figure 1.2-3 shows a block diagram of the MB90360. Block Diagram of Evaluation Chip Figure 1.2-1 Block Diagram of Evaluation Chip (MB90V340A-101/102) X0, X1 Clock X0A, X1A * control RAM 30KB Prescaler (5 channels) SOT4 to SOT0 UART SCK4 to SCK0 (5 channels)
Page 26 CHAPTER 1 OVERVIEW Figure 1.2-2 Block Diagram of Evaluation Chip (MB90V340A-103/104) X0,X1 X0A,X1A * oscillation RAM 30KB Prescaler (5 channels) SOT4 to SOT0 SCK4 to SCK0 5 channels SIN4 to SIN0 AV cc 8-/10-bit AV ss AN23 to AN0 converter AVRH 24 channels AVRL...
Page 27: Block Diagram Of Flash/Mask Rom Version
Block Diagram of Flash/Mask ROM Version Figure 1.2-3 Block Diagram of Flash/Mask ROM Version X0,X1 X0A,X1A * oscillation Prescaler (2 channels) SOT0,SOT1 SCK0,SCK1 2 channels SIN0,SIN1 AN15 to AN0 16 channels ADTG PPGF(E),PPGD(C), PPGC(D),PPGE(F) 2 channels *1: Product without S-suffix *2: Product with T-suffix *3: CR oscillation circuit/clock supervisor supports MB90367/T(S), MB90F367/T(S) only Clock...
Page 28: Package Dimensions
(FPT-48P-M26) 9.00±0.20(.354±.008)SQ +0.40 7.00 –0.10 INDEX LEAD No. 0.50(.020) 2003 FUJITSU LIMITED F48040S-c-2-2 Package width × package length Lead shape Sealing method Mounting height (Reference) Note 1) * : These dimensions include resin protrusion. Note 2) Pins width and pins thickness include plating thickness.
Page 29: Pin Assignment
Pin Assignment This section shows the pin assignments for the MB90360 series. Pin assignment (LQFP-48) Figure 1.4-1 shows the pin assignments of LQFP-48 type. AVcc P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6/PPGC(D) P67/AN7/PPGE(F) P80/ADTG/INT12R P50/AN8 *1: MB90F362/T, MB90362/T, MB90F367/T, MB90367/T : X0A, X1A MB90F362S/TS, MB90362S/TS, MB90F367S/TS, MB90367S/TS : P40, P41 *2: High current port Figure 1.4-1 Pin Assignment (LQFP-48)
Page 30: Pin Functions
CHAPTER 1 OVERVIEW Pin Functions Table 1.5-1 describes the pin functions of the MB90360 series. Pin Functions Table 1.5-1 Pin Description (1/3) Pin number Pin name 3 to 8 P60 to P65 AN0 to AN5 9 to 10 P66, P67 AN6, AN7 PPGC(D), PPGE(F)
Page 31 Table 1.5-1 Pin Description (2/3) Pin number Pin name 29 to 32 P24 to P27 IN0 to IN3 33, 34 P22 to P23 PPGF(E), PPGD(C) 35, 36 P20, P21 SIN1 SCK1 SOT1 INT9R SOT0 TOT2 SCK0 INT15R SIN0 INT14R TIN2 Circuit type Capacity pin for stabilizing power supply.
Page 32 CHAPTER 1 OVERVIEW Table 1.5-1 Pin Description (3/3) Pin number Pin name FRCK0 46, 47 P40, P41 X1A, X0A Circuit type General-purpose I/O port (I/O circuit type of P44 is different from that of MB90V340A.) Free-run timer 0 clock pin General-purpose I/O port (product with S-suffix and MB90V340A-101/103 only) Oscillation input pin for subclock...
Page 33: Input-Output Circuits
Input-Output Circuits Table 1.6-1 lists the input-output circuits. Input-output Circuits Table 1.6-1 I/O Circuit Types (1/4) Type Pull-down resistor Circuit Xout Standby control signal Xout Standby control signal Hysteresis input Hysteresis input CHAPTER 1 OVERVIEW Remarks Oscillation circuit High-speed oscillation feedback resistor = approx.
Page 34 CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (2/4) Type Pull-up resistor Circuit Hysteresis input Pout Nout Hysteresis input Automotive input Standby control for input shutdown Pull-up control Pout Nout Hysteresis input Automotive input Standby control for input shutdown Remarks CMOS hysteresis input pin Pull-up resister value: approx.
Page 35 Table 1.6-1 I/O Circuit Types (3/4) Type Circuit Pout Nout Hysteresis input Automotive input Standby control for input shutdown Analog input Pull-up control High current output Pout High current output Nout Hysteresis input Automotive input Standby control for input shutdown CHAPTER 1 OVERVIEW Remarks CMOS level output...
Page 36 CHAPTER 1 OVERVIEW Table 1.6-1 I/O Circuit Types (4/4) Type Circuit Pout Nout CMOS input Automotive input Standby control for input shutdown Remarks CMOS level output = 4 mA, I = -4 mA) CMOS hysteresis inputs (with the standby-time input shutdown function) Automotive hysteresis inputs (with the standby-time input shutdown...
Page 37: Handling Device
Handling Device This section explains notes on handling the MB90360 series. Handling the Device Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than V • A voltage higher than the rated voltage is applied between V •...
Page 38 CHAPTER 1 OVERVIEW Using external clock To use external clock, drive the X0 (X0A) pin and leave X1 (X1A) pin open. Precautions for when not using a sub clock signal If you do not connect pins X0A and X1A to an oscillator, use pull-down handling on the X0A pin, and leave the X1A pin open.
Page 39 Figure 1.7-2 Power Supply Pins (V Pull-up/down resistors The MB90360 Series does not support internal pull-up/down resistors (except Port2: programmable pull-up resistors). Use pull-up/down handling where needed. Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits.
Page 40 CHAPTER 1 OVERVIEW Notes on Energization To prevent malfunction of the internal voltage regulator, supply voltage profile while turning on the power supply should be slower than 50 µs from 0.2 V to 2.7 V. Stabilization of power supply voltage If the power supply voltage varies acutely even within the operation assurance range of the V supply voltage, a malfunction may occur.
Page 41 Flash security Function The security bit is located in the area of the flash memory. If protection code 01 security. Therefore please do not write 01 Please refer to following table for the address of the security bit. Flash memory size MB90F362/T(S), Embedded 512Kbit flash memory MB90F367/T(S)
Page 42 CHAPTER 1 OVERVIEW...
Page 43: Chapter 2 Cpu
CHAPTER 2 This chapter explains the CPU. 2.1 Outline of the CPU 2.2 Memory Space 2.3 Memory Map 2.4 Linear Addressing 2.5 Bank Addressing Types 2.6 Multi-byte Data in Memory Space 2.7 Registers 2.8 Register Bank 2.9 Prefix Codes 2.10 Interrupt Disable Instructions 2.11 Precautions for Use of "DIV A, Ri"...
Page 44: Outline Of The Cpu
CHAPTER 2 CPU Outline of the CPU The F MC-16LX CPU core is a 16-bit CPU designed for applications that require high- speed real-time processing, such as home-use or vehicle-mounted electronic appliances. The F MC-16LX instruction set is designed for controller applications, and is capable of high-speed, highly efficient control processing.
Page 45: Memory Space
Memory Space An F MC-16LX CPU has a 16M bytes memory space. All data program input and output managed by the F MC-16LX CPU are located in this 16M bytes memory space. The CPU accesses the resources by indicating their addresses using a 24-bit address bus. Outline of CPU Memory Space Figure 2.2-1 shows a sample relationship between the F Figure 2.2-1 Sample Relationship between F...
Page 46: Ram Area
CHAPTER 2 CPU ROM area Vector table area (address: FFFC00 This area is used as a vector table for reset/interrupt and CALLV vector. This area is allocated at the highest addresses of the ROM area. The start address of the corresponding processing routine is set as data in each vector table address.
Page 47 Address generation types The F MC-16LX has the following 2 addressing modes: Linear addressing An entire 24-bit address is specified by an instruction. Bank addressing. The eight high-order bits of an address are specified by an appropriate bank register, and the remaining 16 low-order bits are specified by an instruction.
Page 48: Memory Map
CHAPTER 2 CPU Memory Map The memory map of the MB90360 Series is shown in Figure 2.3-1 . Memory Map The ROM data in the high-order portion of FF-bank can be seen as an image in the higher 00-bank in order to support the small model C compiler.
Page 49: Linear Addressing
Linear Addressing There are 2 types of linear addressing: • 24-bit operand specification: Directly specifies a 24-bit address using operands. • 32-bit register indirect specification: Indirectly specifies the 24 low-order bits of a 32- 24-bit Operand Specification Figure 2.4-1 shows an example of 24-bit operand specification. Figure 2.4-2 shows an example of 32-bit register indirect specification.
Page 50: Bank Addressing Types
CHAPTER 2 CPU Bank Addressing Types In the bank method, the 16M bytes space is divided into 256 for 64K bytes banks. The following 5 bank registers are used to specify the banks corresponding to each space: • Program bank register (PCB) •...
Page 51 Table 2.5-1 Default Space Default space Program space PC indirect, program access, branch Data space Addressing mode using @RW0, @RW1, @RW4, or @RW5, @A, addr16, and dir Stack space Addressing mode using PUSHW, POPW, @RW3, or @RW7 Additional space Addressing mode using @RW2 or @RW6 Figure 2.5-1 is an example of a memory space divided into register banks.
Page 52: Multi-Byte Data In Memory Space
CHAPTER 2 CPU Multi-byte Data in Memory Space Data is written to memory from the low-order addresses. Therefore, for a 32-bit data item, the low-order 16 bits are transferred before the high-order 16 bits. If a reset signal is inputted immediately after the low-order bits are written, the high- order bits might not be written.
Page 53: Registers
Registers The F MC-16LX registers are largely classified into two types: special registers in the CPU and general-purpose registers in memory. The special registers are dedicated internal hardware of the CPU, and they have specific use defined by the CPU architecture.
Page 54 CHAPTER 2 CPU 32 bits Figure 2.7-1 Special Registers 8 bits 16 bits Accumulator User stack pointer System stack pointer Processor status Program counter Direct page register Program bank register Data bank register User bank register System stack bank register Additional data bank register...
Page 55 General-purpose registers The F MC-16LX general-purpose registers are located from addresses 000180 configuration) of main storage. The register bank pointer (RP) indicates which of the above addresses are currently being used as a register bank. Each bank has the following three types of registers. These registers are mutually dependent as described in Figure 2.7-2 .
Page 56: Accumulator (A)
CHAPTER 2 CPU 2.7.1 Accumulator (A) The accumulator (A) register consists of 2 16-bit arithmetic operation registers (AH and AL), and is used as a temporary storage for operation results and transfer data. Accumulator (A) During 32-bit data processing, AH and AL are used together. Only AL is used for word processing in 16- bit data processing mode or for byte processing in 8-bit data processing mode (see Figure 2.7-3 and Figure 2.7-4 ).
Page 57: User Stack Pointer (Usp) And System Stack Pointer (Ssp)
2.7.2 User Stack Pointer (USP) and System Stack Pointer (SSP) USP and SSP are 16-bit registers that indicate the memory addresses for saving and restoring data when a push/pop instruction or subroutine is executed. User Stack Pointer (USP) and System Stack Pointer (SSP) The USP and SSP registers are used by stack instructions.
Page 58: Processor Status (Ps)
CHAPTER 2 CPU 2.7.3 Processor Status (PS) The PS register consists of the bits controlling the CPU operation and the bits indicating the CPU status. Processor Status (PS) As shown in Figure 2.7-6 , the high-order byte of the PS register consists of a register bank pointer (RP) and an interrupt level mask register (ILM).
Page 59: Register Bank Pointer (Rp)
T: Sticky bit flag: 1 is set in the T flag when there is at least one "1" in the data shifted out from the carry after execution of a logical right/arithmetic right shift instruction. Otherwise, 0 is set in the T flag. In addition, "0" is set in the T flag when the shift amount is zero.
Page 60 CHAPTER 2 CPU Interrupt level mask register (ILM) The ILM register consists of three bits, indicating the CPU interrupt masking level. An interrupt request is accepted only when the level of the interrupt is higher than that indicated by these three bits. Level 0 is the highest priority interrupt, and level 7 is the lowest priority interrupt (see Table 2.7-1 ).
Page 61: Program Counter (Pc)
2.7.4 Program Counter (PC) The PC register is a 16-bit counter that indicates the low-order 16 bits of the memory address of an instruction code to be executed by the CPU. The high-order eight bits of the address are indicated by the PCB. The PC register is updated by a conditional branch instruction, subroutine call instruction, interrupt, or reset.
Page 62: Register Bank
CHAPTER 2 CPU Register Bank A register bank consists of eight words. The register bank can be used as the following general-purpose registers for arithmetic operations: byte registers R0 to R7, word registers RW0 to RW7, and long word registers RL0 to RL3. In addition, the register bank can be used as instruction pointers.
Page 63 2.8-1 . DPR is eight bits long, and is initialized to 01 instruction. Figure 2.8-1 Generating a Physical Address in Direct Addressing Mode DTB register 24-bit physical address Program counter bank register (PCB) <Initial value: Value in reset vector> Data bank register (DTB) <Initial value: 00 User stack bank register (USB) <Initial value: 00 System stack bank register (SSB) <Initial value: 00 Additional data bank register (ADB) <Initial value: 00...
Page 64: Prefix Codes
CHAPTER 2 CPU Prefix Codes Placing a prefix code before an instruction partially changes the operation of the instruction. Three types of prefix codes can be used: bank select prefix, common register bank prefix, and flag change disable prefix. Bank Select Prefix The memory space used for accessing data is determined for each addressing mode.
Page 65: Common Register Bank Prefix (Cmr)
MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction. RETI SSB is used regardless of the prefix. Common Register Bank Prefix (CMR) To simplify data exchange between multiple tasks, the same register bank must be accessed relatively easily regardless of the RP value.
Page 66 CHAPTER 2 CPU MOV ILM,#imm8 The instruction is executed normally, but the prefix affects the next instruction.
Page 67: Interrupt Disable Instructions
2.10 Interrupt Disable Instructions Interrupt requests are not sampled for the following ten instructions: - MOV ILM,#imm8 - PCB - AND CCR,#imm8 - ADB Interrupt Disable Instructions If a valid hardware interrupt request occurs during execution of any of the above instructions, the interrupt can be processed only when an instruction other than the above is executed.
Page 68: Precautions For Use Of "Div A, Ri" And "Divw A, Rwi" Instructions
CHAPTER 2 CPU 2.11 Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Set "00 " in the bank register before using the "DIV A, Ri" and "DIVW A, RWi" instructions. Precautions for Use of "DIV A, Ri" and "DIVW A, RWi" Instructions Table 2.11-1 Precautions for Use of "DIVA,Ri"...
Page 69 Example: If "DIV A,R0" is executed with DTB = "053 ") × "10 ("03 " + "08 is specified by "DIV A,R0" as the bank register, the remainder is stored in address "05301B8 was obtained by adding the bank address "053 Note: For information about the bank register and Ri and RWi registers, see "2.7 Registers".
Page 70 CHAPTER 2 CPU...
Page 71: Chapter 3 Interrupts
CHAPTER 3 INTERRUPTS This chapter explains the interrupts and function and operation of the extended intelligent I/O service in the MB90360 series. 3.1 Outline of Interrupts 3.2 Interrupt Vector 3.3 Interrupt Control Registers (ICR) 3.4 Interrupt Flow 3.5 Hardware Interrupts 3.6 Software Interrupts 3.7 Extended Intelligent I/O Service (EI 3.8 Operation Flow of and Procedure for Using the Extended Intelligent...
Page 72: Outline Of Interrupts
CHAPTER 3 INTERRUPTS Outline of Interrupts The F MC-16LX has interrupt functions that terminate the currently executing processing and transfer control to another specified program when a specified event occurs. There are four types of interrupt functions: • Hardware interrupt: Interrupt processing due to an internal resource event •...
Page 73: Software Interrupts
Software Interrupts Interrupts requested by executing the INT instruction are software interrupts. An interrupt request by the INT instruction does not have an interrupt request or enable flag. An interrupt request is issued always by executing the INT instruction. No interrupt level is assigned to the INT instruction. Therefore, ILM is not updated when the INT instruction is used.
Page 74 CHAPTER 3 INTERRUPTS Exceptions Exception processing is basically the same as interrupt processing. When an exception is detected between instructions, ordinary processing is suspended, and exception processing is performed. In general, exception processing occurs as a result of an unexpected operation. Therefore, use exception processing for debugging programs or for activating recovery software in an emergency.
Page 75: Interrupt Vector
Interrupt Vector An interrupt vector uses the same area for both hardware and software interrupts. For example, interrupt request number INT42 is used for a delayed hardware interrupt and for software interrupt INT #42. Therefore, the delayed interrupt and INT #42 call the same interrupt processing routine.
Page 76 CHAPTER 3 INTERRUPTS Table 3.2-1 Interrupt Vector (2/2) Interrupt Interrupt cause request INT 25 Timebase timer 3 INT 26 External interrupt 8 to 11 INT 27 Watch timer INT 28 External interrupt 12 to 15 INT 29 A/D converter INT 30 I/O timer 0 INT 31 Reserved...
Page 77: Interrupt Control Registers (Icr)
Interrupt Control Registers (ICR) The interrupt control registers are in the interrupt controller. Each interrupt control register has a corresponding I/O that has an interrupt function. The interrupt control registers have the following 3 functions: • Setting an interrupt level for corresponding peripherals •...
Page 78 CHAPTER 3 INTERRUPTS Table 3.3-1 Interrupt Level Setting Bits and Interrupt Levels ILM2 [bit 11, bit 3] ISE (extended intelligent I/O service enable bits) The ISE bit is readable and writable. In response to an interrupt request, EI set in the ISE bit and an interrupt sequence is activated when '0' is set in the ISE bit. Upon completion of EI OS, the ISE bit is cleared to a zero.
Page 79 [bit 15 to bit 12, bit 7 to bit 4] ICS 3 to ICS 0 (extended intelligent I/O service channel select bits) ICS3 to ICS0 are write-only bits. These bits specify the EI determined the extended intelligent I/O service descriptor addresses in memory, which is explained later.
Page 80 CHAPTER 3 INTERRUPTS [bit 13, bit 12, bits 5, bit 4] S0 and S1 (extended intelligent I/O service status) S0 and S1 are read-only bits. The values set in these bits indicate the end condition of EI are initialized to '00' upon a reset. Table 3.3-3 shows the relationship between the S bits and the end conditions.
Page 81: Interrupt Flow
Interrupt Flow Figure 3.4-1 shows the interrupt flow. Interrupt Flow START I & IF & IE = 1 ILM > IL Fetching and decoding the next instruction instruction Executing an ordinary instruction Completion of string instruction repetition Updating PC Figure 3.4-1 Interrupt Flow ILM : CPU register level ISE : EI ISE = 1...
Page 82 CHAPTER 3 INTERRUPTS Figure 3.4-2 Register Saving during Interrupt Processing "H" "L" Word (16 bits) SSP (SSP value before interrupt) SSP (SSP value after interrupt)
Page 83: Hardware Interrupts
Hardware Interrupts In response to an interrupt request signal from an internal resource, the CPU pauses current program execution and transfers control to the interrupt processing program defined by the user. This function is called the hardware interrupt function. Hardware Interrupts A hardware interrupt occurs when the relevant conditions are satisfied as a result of two operations: comparison between the interrupt request level and the value in the interrupt level mask register (ILM) of PS in the CPU, and hardware reference to the I flag value of PS.
Page 84: Hardware Interrupt Operation
CHAPTER 3 INTERRUPTS 3.5.1 Hardware Interrupt Operation An internal resource that has the hardware interrupt request function has an interrupt request flag and interrupt enable flag. The interrupt request flag indicates whether an interrupt request exists, and the interrupt enable flag indicates whether the relevant internal resource requests an interrupt to the CPU.
Page 85: Occurrence And Release Of Hardware Interrupt
3.5.2 Occurrence and Release of Hardware Interrupt Figure 3.5-1 shows the processing flow from occurrence of a hardware interrupt to release of the interrupt request in an interrupt processing program. Occurrence and Release of Hardware Interrupt Figure 3.5-1 Occurrence and Release of Hardware Interrupt Register file Micro code MC-16LX CPU...
Page 86 CHAPTER 3 INTERRUPTS The time required for the CPU to execute the interrupt processing in steps 6. and 7. is shown below. See Table 3.5-1 for the cycle count compensation value. Interrupt start: 24 + 6 × (Table 3.3-2 machine cycles) Interrupt return: 15 + 6 ×...
Page 87: Multiple Interrupts
3.5.3 Multiple interrupts As a special case, no hardware interrupt request can be accepted while data is being written to the I/O area. This is intended to prevent the CPU from operating falsely because of an interrupt request issued while an interrupt control register for a resource is being updated.
Page 88: Software Interrupts
CHAPTER 3 INTERRUPTS Software Interrupts In response to execution of a special instruction, control is transferred from the program currently executed by the CPU to the interrupt processing program defined by the user. This is called the software interrupt function. A software interrupt occurs always when the software interrupt instruction is executed.
Page 89 Figure 3.6-1 Occurrence and Release of Software Interrupt Register file Micro code MC-16LX • CPU Save (1) The software interrupt instruction is executed. (2) Special CPU registers in the register file are saved according to the microcode corresponding to the software interrupt instruction.
Page 90: Extended Intelligent I/O Service (Ei 2 Os)
CHAPTER 3 INTERRUPTS Extended Intelligent I/O Service (EI The EI OS function, a kind of hardware interrupt operation, automatically transfers data between input and output and memory. An interrupt processing program was conventionally used for such processing, but EI performed like DMA (direct memory access). Extended Intelligent I/O Service (EI OS has the following advantages over the conventional method: •...
Page 91 Figure 3.7-1 Outline of Extended Intelligent I/O Service by IOA by BAP Note: • The area that can be specified by IOA is between 000000 • The area that can be specified by BAP is between 000000 • The maximum transfer count that can be specified by DCT is 65,536. Structure OS is handled by the following 4 sections: Internal resources...
Page 92: Extended Intelligent I/O Service Descriptor (Isd)
CHAPTER 3 INTERRUPTS 3.7.1 Extended Intelligent I/O Service Descriptor (ISD) The extended intelligent I/O service descriptor exists between 000100 internal RAM and consists of the following items: • Data transfer control data • Status data • Buffer address pointer Extended Intelligent I/O Service Descriptor (ISD) Figure 3.7-2 shows the configuration of the extended intelligent I/O service descriptor.
Page 93: Buffer Address Pointer (Bap)
I/O register address pointer (IOA) This is a 16-bit register that indicates the low-order address (A15 to A0) of the buffer and I/O register used for data transfer. The high-order address (A23 to A16) are all zeroes, and any I/O between addresses 000000 and 00FFFF Figure 3.7-4 I/O Register Address Pointer Configuration...
Page 94: Ei 2 Os Status Register (Iscs)
CHAPTER 3 INTERRUPTS 3.7.2 OS Status Register (ISCS) This eight-bit register indicates the update direction (increment/decrement), transfer data format (byte/word), and transfer direction of the buffer address pointer and the I/O register address pointer. This register also indicates whether the buffer address pointer or I/O register address pointer is updated or fixed.
Page 95: Operation Flow Of And Procedure For Using The Extended Intelligent I/O Service (Ei 2 Os)
Operation Flow of and Procedure for Using the Extended Intelligent I/O Service (EI Figure 3.8-1 is a diagram of the EI OS use procedure. OS Operation Flow Interrupt request issued from internal resource ISE = 1 Reading ISD/ISCS End request from resource DIR = 1 Data indicated by IOA (Data transfer)
Page 96 CHAPTER 3 INTERRUPTS Processing by CPU Setting of extended intelligent I/O service (Switching channels) Processing data in buffer The extended EI OS execution time for each flow is described below. When data transfer continues (when the stop condition is not satisfied) (Figure 3.8-1 + Table 3.8-2 ) machine cycles When a stop request is issued from a resource (36 + 6 ×...
Page 97 Table 3.8-2 Data Transfer Compensation Values for EI I/O address pointer Internal Buffer address pointer access B: Byte data transfer E: Even address word transfer O: Odd address word transfer Table 3.8-3 Interrupt Handling Time Address pointed to by the stack pointer External 8 bits External even-numbered address External odd-numbered address...
Page 98: Exceptions
Exception processing is fundamentally the same as interrupt processing. When an exception is detected between instructions, exception processing is performed separately from ordinary processing. In general, exception processing is performed as a result of an unexpected operation. Fujitsu recommends using exception processing for debugging or for activating emergency recovery software.
Page 99: Chapter 4 Delayed Interrupt Generation Module
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE This chapter explains the functions and operations of the delayed interrupt generation module. 4.1 Overview of Delayed Interrupt Generation Module 4.2 Block Diagram of Delayed Interrupt Generation Module 4.3 Configuration of Delayed Interrupt Generation Module 4.4 Explanation of Operation of Delayed Interrupt Generation Module 4.5 Precautions when Using Delayed Interrupt Generation Module 4.6 Program Example of Delayed Interrupt Generation Module...
Page 100: Overview Of Delayed Interrupt Generation Module
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE Overview of Delayed Interrupt Generation Module The delayed interrupt generation module generates the interrupt for task switching. The hardware interrupt request can be generated/cancelled by software. Overview of Delayed Interrupt Generation Module By using the delayed interrupt generation module, a hardware interrupt request can be generated or cancelled by software.
Page 101: Block Diagram Of Delayed Interrupt Generation Module
Block Diagram of Delayed Interrupt Generation Module The delayed interrupt generation module consists of the following blocks: • Interrupt request latch • Delayed interrupt request generate/cancel register (DIRR) Block Diagram of Delayed Interrupt Generation Module Figure 4.2-1 Block Diagram of Delayed Interrupt Generation Module Delayed interrupt request generate/cancel register (DIRR) −...
Page 102: Configuration Of Delayed Interrupt Generation Module
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE Configuration of Delayed Interrupt Generation Module This section lists registers and reset values in the delayed interrupt generation module. List of Registers and Reset Values Figure 4.3-1 List of Registers and Reset Values in Delayed Interrupt Generation Module Delayed interrupt request generate/cancel bit 15 register (DIRR)
Page 103: Delayed Interrupt Request Generate/Cancel Register (Dirr)
4.3.1 Delayed interrupt request generate/cancel register (DIRR) The delayed interrupt request generate/cancel register (DIRR) generates or cancels a delayed interrupt request. Delayed Interrupt Request Generate/cancel Register (DIRR) Figure 4.3-2 Delayed Interrupt Request Generate/cancel Register (DIRR) Address 00009F − − − −...
Page 104: Explanation Of Operation Of Delayed Interrupt Generation Module
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE Explanation of Operation of Delayed Interrupt Generation Module The delayed interrupt generation module has a function for generating or canceling an interrupt request by software. Explanation of Operation of Delayed Interrupt Generation Module Using the delayed interrupt generation module requires the setting shown in Figure 4.4-1 . Figure 4.4-1 Setting for Delayed Interrupt Generation Module −...
Page 105: Precautions When Using Delayed Interrupt Generation Module
Precautions when Using Delayed Interrupt Generation Module This section explains the precautions when using the delayed interrupt generation module. Precautions when Using Delayed Interrupt Generation Module • The interrupt processing is restarted at return from interrupt processing without setting the R0 bit in the delayed interrupt request generate/cancel register (DIRR) to "0"...
Page 106: Program Example Of Delayed Interrupt Generation Module
CHAPTER 4 DELAYED INTERRUPT GENERATION MODULE Program Example of Delayed Interrupt Generation Module This section gives a program example of the delayed interrupt generation module. Program Example of Delayed Interrupt Generation Module Processing specification The main program writes "1" to the R0 bit in the delayed interrupt request generate/cancel register (DIRR) to generate a delayed interrupt request and performs task switching.
Page 107: Chapter 5 Clocks
CHAPTER 5 CLOCKS This chapter explains the clocks used by MB90360 series microcontrollers. 5.1 Clocks 5.2 Block Diagram of the Clock Generation Block 5.3 Clock Selection Register (CKSCR) 5.4 PLL/Subclock Control Register (PSCCR) 5.5 Clock Mode 5.6 Oscillation Stabilization Wait Interval 5.7 Connection of an Oscillator or an External Clock to the Microcontroller...
Page 108: Clocks
CHAPTER 5 CLOCKS Clocks The clock generation block controls the operation of the internal clock that controls operation of the CPU and peripheral functions. The clock generated by the clock generation block is called the machine clock. One cycle of machine clock is called one machine cycle.
Page 109 Machine clock The machine clock controls the operation of the CPU and peripheral functions. One cycle of machine clock is regarded as one machine cycle (1/φ). An operating machine clock can be selected from among the main clock, sub-clock, and five types of PLL clock. Note: When the operating voltage is 5 V, the oscillation clock can be between 3 MHz and 16 MHz.
Page 110 CHAPTER 5 CLOCKS Clock Supply Map Since the machine clock generated in the clock generation block is supplied as the clock that controls the operation of the CPU and peripheral functions, the operation of the CPU and the peripheral functions is affected by switching between the main clock, the PLL clock and the subclock (clock mode) and by a change in the PLL clock multiplication ratio.
Page 111: Block Diagram Of The Clock Generation Block
Block Diagram of the Clock Generation Block The clock generation block consists of five blocks: • System clock generation circuit/sub-clock generation circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • PLL/sub-clock control register (PSCCR) • Oscillation stabilization wait interval selector Block Diagram of the Clock Generation Block Figure 5.2-1 shows a block diagram of the clock generation block.
Page 112 CHAPTER 5 CLOCKS Oscillation clock generation circuit This circuit generates an oscillation clock (HCLK) by connecting an oscillator or inputting an external clock to the high-speed oscillation pins. Sub-clock generation circuit This circuit generates a sub clock (SCLK) by connecting an oscillator or inputting an external clock to the low-speed oscillation pins (X0A, X1A).
Page 113: Register Of Clock Generation Block
5.2.1 Register of Clock Generation Block This section explains the register of the clock generation block. Clock Selection Register and List of Reset Value Figure 5.2-2 Clock Selection Register and List of Reset Value Clock selection register (CKSCR) PLL/subclock control register (PSCCR) CHAPTER 5 CLOCKS...
Page 114: Clock Selection Register (Ckscr)
CHAPTER 5 CLOCKS Clock Selection Register (CKSCR) The clock selection register (CKSCR) is used to switch among the main clock, PLL clocks and subclock, also used to select an oscillation stabilization wait interval and a PLL clock multiplier. Configuration of the Clock Selection Register (CKSCR) Figure 5.3-1 Configuration of the Clock Selection Register (CKSCR) Address 0000A1...
Page 115 Table 5.3-1 Functions of Clock Selection Register (CKSCR) (1/2) Bit name bit15 SCM: The bit indicates the main clock or subclock currently selected as the machine clock. Sub clock operation When the sub clock operation flag bit (CKSCR: SCM) is "0" and the sub clock select bit flag bit (CKSCR: SCS) is "1", it indicates that the machine clock is currently switching from subclock to main clock.
Page 116 CHAPTER 5 CLOCKS Table 5.3-1 Functions of Clock Selection Register (CKSCR) (2/2) Bit name bit10 MCS: This bit indicates the main clock or PLL clock to be selected as the machine clock. PLL clock select bit When the machine clock is switched from the main clock to the PLL clock (CKSCR: MCS = 1 →...
Page 117: Pll/Subclock Control Register (Psccr)
PLL/Subclock Control Register (PSCCR) PLL/Subclock control register selects the PLL multiplication rate and subclock division rate. This register is write only. Read value of all bits is set to "1". Configuration of the PLL/Subclock Control Register (PSCCR) Figure 5.4-1 shows the configuration of the PLL/Subclock control register (PSCCR). Table 5.4-1 shows the function of each bit in the PLL/subclock control register (PSCCR).
Page 118 CHAPTER 5 CLOCKS Table 5.4-1 Functional Description of Each Bit in the PLL/subclock Control Register (PSCCR) Bit name bit15 Unused These bits are not used. Writing to these bits has no effect to operation. bit12 Read value is always "1". bit11 Reserved bit Always write "0"...
Page 119: Clock Mode
Clock Mode Three clock modes are provided: main clock mode, PLL clock mode and sub-clock mode. Clock Mode Main clock mode In main clock mode, a clock with 2-frequency division of the clock generated by connecting on oscillator or by inputting from external to the high-speed oscillation pins (X0, X1) is used. Sub-clock mode In sub-clock mode, a clock with 4/2-frequency division of the clock generated by connecting an oscillator or inputting from external, or the internal CR oscillation clock to the low-speed oscillation pins (X0A,...
Page 120: Selection Of A Pll Clock Multiplier
CHAPTER 5 CLOCKS Transition from sub-clock mode to main clock mode When the SCS bit of the clock selection register (CKSCR) is rewritten from “0” to “1” in sub-clock mode, switching from the sub-clock to the main clock occurs after the main clock oscillation stabilization wait interval.
Page 121: Chapter 5 Clocks
Figure 5.5-1 shows the status change caused by machine clock switching. Figure 5.5-1 Status Change Diagram for Machine Clock Selection Main --> Sub MCS = 1 MCM = 1 SCS = 0 Main (10) SCM = 1 MCS = 1 (12) CS1, CS0 = xx MCM = 1...
Page 122 CHAPTER 5 CLOCKS (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) CS1, CS0 Notes: • The initial value for the machine clock setting is main clock (CKSCR: MCS = 1, SCS = 1). • If both the SCS and MCS bits are “0”, the SCS bit takes precedence, that is, the sub-clock is selected. •...
Page 123: Oscillation Stabilization Wait Interval
Oscillation Stabilization Wait Interval When the power is turned on during the oscillation clock is stopped or when stop mode is released, a time until the oscillation clock stabilizes (oscillation stabilization wait time is required immediately after oscillation starts. Also, the oscillation stabilization wait time is required when the clock mode is switched from main clock to PLL clock, main clock to sub-clock, sub-clock to main clock, and sub-clock to PLL clock.
Page 124: Connection Of An Oscillator Or An External Clock To The Microcontroller
CHAPTER 5 CLOCKS Connection of an Oscillator or an External Clock to the Microcontroller The MB90360 series microcontroller contains a system clock generation circuit. Connecting an external oscillator to this circuit generates the system clock. Alternatively, an externally generated clock can be input to the microcontroller. Connection of an Oscillator or an External Clock to the Microcontroller Example of connecting a crystal or ceramic oscillator to the microcontroller Figure 5.7-1 Example of Connecting a Crystal or Ceramic Oscillator to the Microcontroller...
Page 125: Chapter 6 Clock Supervisor
CHAPTER 6 CLOCK SUPERVISOR This chapter explains the function and the operation of the clock supervisor. Only the product with built-in clock supervisor of the MB90360 series is valid to this function. 6.1 Overview of Clock Supervisor 6.2 Block Diagram of Clock Supervisor 6.3 Clock Supervisor Control Register (CSVCR) 6.4 Operating Mode of Clock Supervisor...
Page 126: Overview Of Clock Supervisor
CHAPTER 6 CLOCK SUPERVISOR Overview of Clock Supervisor The clock supervisor checks the oscillation of the main clock or a sub-clock (without "S" suffix product). When the main clock or a sub-clock stops due to some breakdowns, the control circuit of the clock supervisor switches the clock source to built-in CR oscillation clock, sets the detection flag, and generates reset.
Page 127: Block Diagram Of Clock Supervisor
Block Diagram of Clock Supervisor The clock Supervisor is composed of the following block: • Main clock supervisor • Sub clock supervisor • Control circuit • Clock supervisor control register (CSVCR) • Main clock selector • Sub clock selector • CR oscillation circuit Block Diagram of Clock Supervisor Figure 6.2-1 shows the block diagram of clock supervisor.
Page 128 CHAPTER 6 CLOCK SUPERVISOR Main clock supervisor The oscillation of the main oscillation clock (HCLK) is supervised by using the clock from the CR oscillation circuit as a clock source. Sub clock supervisor The oscillation of the sub oscillation clock (SCLK) is supervised by using the clock from the CR oscillation circuit as a clock source.
Page 129: Clock Supervisor Control Register (Csvcr)
Clock Supervisor Control Register (CSVCR) This register switches main clock/sub clock/PLL clock, and selects the oscillation stabilization wait time and PLL clock multiplication rate. Clock Supervisor Control Register (CSVCR) Figure 6.3-1 Clock Supervisor Control Register (CSVCR) Address SCKS MM 007960 R/W R Read/Write Read only...
Page 130 CHAPTER 6 CLOCK SUPERVISOR Bit name bit7 SCKS This bit permits built-in CR oscillation clock to be used as a sub-clock. Only "S" suffix Sub clock select product is valid to this function. "1": It is possible to change to the sub clock mode with built-in CR oscillation clock. "0": It is not possible to change to the sub clock mode.
Page 131: Operating Mode Of Clock Supervisor
Operating Mode of Clock Supervisor This section explains all the operating modes of the Clock Supervisor. Operating Mode in Initialized State The CR oscillation circuit, the main clock supervisor and the sub-clock supervisor are enabled before the clock supervisor control register (CSVCR) is set by the user program. •...
Page 132: Sub-Clock Mode
CHAPTER 6 CLOCK SUPERVISOR • The sub-clock supervisor is operated by setting SSVE(CSVCR:bit2) to 1. Please note the programming of software to do after 10 µs or more has passed since the CR oscillation circuit was set enable. Sub-clock Mode The main clock supervisor automatically becomes disable at the sub-clock mode.
Page 133: Reset Check By Clock Supervisor
CHAPTER 6 CLOCK SUPERVISOR Reset Check By Clock Supervisor To check whether reset was executed by the clock supervisor, the WDTC register is read with software and the reset factor is checked. When ERSR (bit4 of WDTC) is set, the factor is a reset from an external terminal or a reset by the clock supervisor (include low voltage detection/CPU operating detection reset in "T"...
Page 134 CHAPTER 6 CLOCK SUPERVISOR...
Page 135: Chapter 7 Resets
CHAPTER 7 RESETS This chapter describes resets for the MB90360-series microcontrollers. 7.1 Resets 7.2 Reset Cause and Oscillation Stabilization Wait Times 7.3 External Reset Pin 7.4 Reset Operation 7.5 Reset Cause Bits 7.6 Status of Pins in a Reset...
Page 136: Resets
CHAPTER 7 RESETS Resets If a reset is generated, the CPU immediately stops the current execution process and waits for the reset to be cleared. The CPU then begins processing at the address indicated by the reset vector. The four causes of a reset are as follows •...
Page 137 stabilization wait time has elapsed, the reset is executed. External reset An external reset is generated by the L level input to an external reset pin (RST pin). The minimum required period of the L level is at least 500 ns. Reset operation is performed after oscillation stabilization wait time elapses.
Page 138 CHAPTER 7 RESETS CPU operation detection reset The CPU operation detection reset is 20-bit counter that the source oscillation is count-locked. If the CL bit of the low voltage/CPU operation detection reset is not cleared within a specified time after activation, the reset is generated.
Page 139: Reset Cause And Oscillation Stabilization Wait Times
Reset Cause and Oscillation Stabilization Wait Times The MB90360 series has seven reset causes. The oscillation stabilization wait time for a reset depends on the reset cause. Reset Causes and oscillation Stabilization Wait Times Table 7.2-1 summarizes reset causes and oscillation stabilization wait times. Table 7.2-1 Reset Causes and oscillation Stabilization Wait Times Reset Reset cause...
Page 140: Oscillation Stabilization Wait And Reset State
CHAPTER 7 RESETS Figure 7.2-1 Oscillation Stabilization Wait Times at a Power-on Reset operation Stabilization wait time of voltage step-down circuit Note: Ceramic and crystal oscillators generally require an oscillation stabilization wait time of several milliseconds to some tens of milliseconds, until stabilization at a natural frequency is attained after starts oscillation.
Page 141: External Reset Pin
External Reset Pin The external reset pin (RST pin) is an input pin used exclusively for a reset. Inputting an L level signal generates an internal reset. For the MB90360-series, resets are generated in synchronization with the CPU operating clock. However, initialization of external pin is asynchronous with the CPU operating clock.
Page 142: Reset Operation
CHAPTER 7 RESETS Reset Operation When the reset signal is inactivated, the reset vector and mode data is fetched from the predetermined locations depending on the setting of the mode pins. This operation, the mode fetch, then defines the operation mode of the CPU and the start address of the first instruction.
Page 143: Mode Fetch
Mode Fetch When the reset is cleared, the CPU transfers the reset vector and the mode data to the appropriate registers in the CPU core by hardware. The reset vector and mode data are allocated to the four bytes from "FFFFDC "...
Page 144: Reset Cause Bits
CHAPTER 7 RESETS Reset Cause Bits A reset cause can be identified by reading the watchdog timer control register (WDTC). Reset Cause Bits As shown in Figure 7.5-1 , a flip-flop is associated with each reset cause. The contents of the flip-flops are obtained by reading the watchdog timer control register (WDTC).
Page 145 Correspondence between reset cause bits and reset causes Figure 7.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC). Table 7.5-1 maps the correspondence between the reset cause bits and reset causes. See “Watchdog timer control register (WDTC)”...
Page 146 CHAPTER 7 RESETS Status of Reset Cause Bit and Low Voltage Detection Bit Figure 7.5-3 Status of Reset Cause Bit and Low Voltage Detection Bit Vcc=4V PONR bit (power-on) ERST bit (external reset input, CPU operation detection, or LVRF = 1) LVRF bit* (low voltage detection 0.3V)
Page 147: Notes About Reset Cause Bits
Notes about Reset Cause Bits Multiple reset causes generated at the same time When multiple reset causes are generated at the same time, the corresponding reset cause bits of the watchdog timer control register (WDTC) are also set to "1". If, for example, an external reset request via the RST pin and the watchdog timer overflow occur at the same time, the ERST and the WRST bits are both set to "1".
Page 148: Status Of Pins In A Reset
CHAPTER 7 RESETS Status of Pins in a Reset This section describes the status of pins when a reset occurs. Status of Pins during a Reset The status of pins during a reset depends on the settings of mode pins (MD2 to MD0). About status of each pins during reset, please see "8.7 Status of Pins in Standby Mode and during Hold and Reset".
Page 149: Chapter 8 Low-Power Consumption Mode
CHAPTER 8 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode of MB90360 series microcontrollers. 8.1 Overview of Low-Power Consumption Mode 8.2 Block Diagram of the Low-Power Consumption Control Circuit 8.3 Low-Power Consumption Mode Control Register (LPMCR) 8.4 CPU Intermittent Operation Mode 8.5 Standby Mode 8.6 Status Change Diagram 8.7 Status of Pins in Standby Mode and during Hold and Reset...
Page 150: Overview Of Low-Power Consumption Mode
CHAPTER 8 LOW-POWER CONSUMPTION MODE Overview of Low-Power Consumption Mode The MB90360 series has the following CPU operating modes, any of which can be used depending on operating clock selection and clock oscillation control: • Clock mode • CPU intermittent operating mode : main clock intermittent operating mode, PLL clock •...
Page 151: Standby Mode
Clock Mode PLL clock mode In this mode, a PLL clock that is a multiple of the oscillation clock (HCLK) is used to operate the CPU and peripheral functions. Main clock mode In this mode, the main clock, with the oscillation clock (HCLK) frequency divided by 2 is used to operate the CPU and peripheral functions.
Page 152 CHAPTER 8 LOW-POWER CONSUMPTION MODE Timebase timer mode The timebase timer mode operates the oscillation clock (HCLK), sub-clock (SCLK), timebase timer, watch timer, and low voltage detection circuit only. All peripheral functions other than the timebase timer, watch timer, and low voltage detection circuit stop. Stop mode The stop mode stops the oscillation clock (HCLK) and sub-clock (SCLK) during operation in each clock mode, and all functions other than low voltage detection circuit stop.
Page 153: Block Diagram Of The Low-Power Consumption Control Circuit
Block Diagram of the Low-Power Consumption Control Circuit This section shows the block diagram of the low-power consumption control circuit. Block Diagram of the Low-Power Consumption Control Circuit Figure 8.2-1 Block Diagram of the Low-Power Consumption Control Circuit Reset (cancellation) Interrupt (cancellation) Clock...
Page 154 CHAPTER 8 LOW-POWER CONSUMPTION MODE CPU clock control circuit This circuit controls clocks supplied to the CPU. Pin high-impedance control circuit This circuit makes I/O pins high-impedance in the watch mode, timebase timer mode and stop mode. Internal reset generation circuit This circuit generates an internal reset signal.
Page 155: Low-Power Consumption Mode Control Register (Lpmcr)
Low-Power Consumption Mode Control Register (LPMCR) This register switches to or releases the low-power consumption mode. This register also generates the internal reset signal and sets the halt cycle count during the CPU intermittent operation mode. Low-Power Consumption Mode Control Register (LPMCR) Figure 8.3-1 Configuration of the Low-power Consumption Mode Control Register (LPMCR) Address STP SLP SPL RST TMD CG1 CG0...
Page 156 CHAPTER 8 LOW-POWER CONSUMPTION MODE Table 8.3-1 Functions of Low-power Consumption Mode Control Register (LPMCR) Bit name bit7 STP: Stop mode bit bit6 SLP: Sleep mode bit bit5 SPL: Pin state specification bit bit4 RST: Internal reset signal generation bit bit3 TMD: Watch mode bit...
Page 157 Notes: • Switching to a low-power consumption mode is performed by writing the low-power consumption mode control register (LPMCR). Only the instructions listed in Table 8.3-2 should be used for this purpose. If other instructions are used for switching to a low-power consumption mode, operation cannot be assured. •...
Page 158: Cpu Intermittent Operation Mode
CHAPTER 8 LOW-POWER CONSUMPTION MODE CPU Intermittent Operation Mode This mode is used for intermittent operation of the CPU while operation clock is supplied to the CPU and peripheral functions. The purpose of this mode is to reduce power consumption. CPU Intermittent Operation Mode This mode halts the supply of the clock pulse to the CPU for a certain period.
Page 159: Standby Mode
Standby Mode The standby mode causes the standby control circuit to either stop supplying an operation clock to the CPU or peripheral functions or to stop the oscillation clock reducing power consumption. Operation Status during Standby Mode Table 8.5-1 shows operation status during standby mode. Table 8.5-1 Operation Status during Standby Mode Mode name Transition...
Page 160 CHAPTER 8 LOW-POWER CONSUMPTION MODE : operation, : stop, *1 : The timebase timer, watch timer, and low voltage detection function operate. *2 : The watch timer operates. *3 : The DTP/external interrupt input pin operates. *4 : Watch timer, timebase timer, and external interrupts *5 : Watch timer and external interrupts *6 : External interrupt MCS: PLL clock select bit in clock selection register (CKSCR)
Page 161: Sleep Mode
8.5.1 Sleep Mode This mode causes the CPU operating clock to stop during operation in each clock mode. The CPU stops, and peripheral function operates. Switching to Sleep Mode Writing 1 in the SLP bit and 0 in the STP bit of the low-power consumption mode control register (LPMCR) triggers a switch to a sleep mode according to setting of the MCS and SCS bits in the clock selection register (CKSCR).
Page 162 CHAPTER 8 LOW-POWER CONSUMPTION MODE Operation during an interrupt request Writing 1 in the SLP bit of the low-power consumption mode control register (LPMCR) during an interrupt request does not trigger a switch to a sleep mode. If the CPU does not accept the interrupt request, the CPU executes the next to currently executing instruction.
Page 163 Figure 8.5-1 Release of Sleep Mode by Interrupt Occurrence Set to interupt flag of resources INT generate (IL<7) I = 0 ILM<IL Execution of interrupt process Note: When interrupt processing is executed, the CPU normally executes the instruction that follows the instruction in which a sleep mode has been specified.
Page 164: Watch Mode
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.2 Watch Mode This mode causes all functions, excluding the subclock (SCLK), watch timer, and low voltage detection circuit, to stop. Main clock and PLL clock stop. Switching to the Watch Mode When 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the subclock run mode, switching to the watch mode occurs.
Page 165 identified according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR). In the sub-watch mode, no oscillation stabilization wait time is generated and the interrupt request is identified immediately after return from the watch mode.
Page 166: Timebase Timer Mode
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.3 Timebase Timer Mode This mode causes all functions, excluding oscillation clock (HCLK), subclock (SCLK), the timebase timer, the watch timer, and low voltage detection circuit, to stop. In this mode, only the timebase timer, watch timer, and low voltage detection circuit, operate. Switching to the Timebase Timer Mode When 0 is written to the TMD bit of the low-power consumption mode control register (LPMCR) in the PLL clock mode or main clock mode (CKSCR: SCM = 1), switching to the timebase timer mode occurs.
Page 167 Return by interrupt When an interrupt request higher than interrupt level (IL) of 7 is generated from the watch timer, timebase timer, and external interrupt in the timebase timer mode, the timebase timer mode is cancelled. After the timebase timer mode is cancelled, as with normal interrupt processing, the generated interrupt request is identified according to the settings of the I flag in the condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR).
Page 168: Stop Mode
CHAPTER 8 LOW-POWER CONSUMPTION MODE 8.5.4 Stop Mode Because this mode causes oscillation clock (HCLK) and subclock (SCLK) to stop during operation in each clock mode, data can be retained by the lowest power consumption. Stop Mode When 1 is written to the STP bit of the low-power consumption mode control register (LPMCR) during operation in the PLL clock mode (CKSCR: MCS=1, SCS=0), the mode transits to the stop mode according to the settings of the MCS bit and SCS bit in the clock selection register (CKSCR).
Page 169 Status of pins Whether the I/O pins in the stop mode retain the state they had immediately before switching to the stop mode or go to the high-impedance state can be controlled by the SPL bit of the low-power consumption mode control register (LPMCR).
Page 170 CHAPTER 8 LOW-POWER CONSUMPTION MODE Return by interrupt When an interrupt request higher than the interrupt level (IL) of 7 is generated from external interrupt in the stop mode, the stop mode is cancelled. In the stop mode, the main clock oscillation stabilization wait time or the sub clock oscillation stabilization wait time is generated after the stop mode is cancelled.
Page 171: Status Change Diagram
Status Change Diagram Figure 8.6-1 shows the operation status and status transition in the clock mode and standby mode of the MB90360 series. Status Change Diagram Drop power supply voltage (4.0 V) Power-on detection reset Power-on reset Terminate of oscillation stabilization wait oscillation stabilization CHAPTER 8 LOW-POWER CONSUMPTION MODE...
Page 172: Status Of Pins In Standby Mode And During Hold And Reset
CHAPTER 8 LOW-POWER CONSUMPTION MODE Status of Pins in Standby Mode and during Hold and Reset The status of I/O pins in the standby mode and during hold and reset are described for each memory access mode. Status of I/O Pins (Single-chip Mode) Table 8.7-1 Status of I/O Pins (Single-chip Mode) Pin Name P27 to P20...
Page 173: Usage Notes On Low-Power Consumption Mode
Usage Notes on Low-Power Consumption Mode This section explains the notes when using the low-power consumption modes. Transition to Standby Mode When an interrupt request is generated from the resource to the CPU, the mode does not transit to each standby mode even after setting the STP and SLP bits to 1 and the TMD bit to 0 in the low-power consumption mode control register (LPMCR) (and also even after interrupt processing).
Page 174: Clock Mode Switching
CHAPTER 8 LOW-POWER CONSUMPTION MODE PLL clock oscillation stabilization wait time In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is necessary to reserve the PLL clock oscillation stabilization wait time. The CPU runs in main clock mode till the PLL clock oscillation stabilization wait time has elapsed.
Page 175 The devices does not guarantee its operation after returning from the standby mode if you place an array of instructions other than the one enclosed in the line. To access the low-power consumption mode control register (LPMCR) with C language To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of the following methods 1.
Page 176 CHAPTER 8 LOW-POWER CONSUMPTION MODE...
Page 177: Chapter 9 Memory Access Modes
CHAPTER 9 MEMORY ACCESS MODES This chapter explains the functions and operations of the memory access modes. 9.1 Outline of Memory Access Modes...
Page 178: Outline Of Memory Access Modes
CHAPTER 9 MEMORY ACCESS MODES Outline of Memory Access Modes In the F MC-16LX, various modes are provided for access methods and access areas. Outline of Memory Access Modes Table 9.1-1 Mode Pin and Mode Operation mode RUN mode Flash programming Operation mode Operation mode means the mode for controlling the device operation status.
Page 179: Mode Pins
9.1.1 Mode Pins Table 9.1-2 lists the operations that can be specified by combining the three external pins MD2 to MD0. Mode Pins Table 9.1-2 Mode Pin and Mode Mode pin setting Mode name Internal vector mode Flash serial programming* Flash memory *: The serial programming of the flash memory cannot be written only by setting the mode pin.
Page 180: Mode Data
CHAPTER 9 MEMORY ACCESS MODES 9.1.2 Mode Data Mode data is stored at FFFFDF operation. This data is fetched during a reset sequence and stored in the mode register inside the device. The mode register value can be changed only by a reset sequence. The setting of this register is valid after the reset sequence.
Page 181: Memory Space In Each Bus Mode
9.1.3 Memory Space in Each Bus Mode Figure 9.1-2 shows the correspondence between the access areas and physical addresses for each bus mode. Memory Space in Each Bus Mode Figure 9.1-2 Relationship between Access Areas and Physical Addresses for Each Bus Mode FFFFFF Address #1 010000...
Page 182 CHAPTER 9 MEMORY ACCESS MODES Recommended Setting Table 9.1-4 lists an example of recommended settings for mode pins and mode data. Table 9.1-4 Recommended Setting Example of Mode Pin and Mode Data Setting example Single-chip External pins have signal functions that depend on each mode.
Page 183: Chapter 10 I/O Ports
CHAPTER 10 I/O PORTS This chapter explains the functions and operations of the I/O ports. 10.1 I/O Ports 10.2 I/O Port Registers...
Page 184: I/O Ports
CHAPTER 10 I/O PORTS 10.1 I/O Ports Each pin of the ports can be specified as input or output using the port direction register (DDR) if the corresponding peripheral does not use the pin. When a pin is specified as input, the logic level at the pin is read. When a pin is specified as output, the port data register value is read.
Page 185: I/O Port Registers
10.2 I/O Port Registers There are five types of I/O port registers: • Port data register (PDR2, PDR4 to PDR6, PDR8) • Port direction register (DDR2, DDR4 to DDR6, DDR8, DDRA) • Pull-up control register (PUCR2) • Analog input enable register (ADER5, ADER6) •...
Page 186: Port Data Register (Pdr)
CHAPTER 10 I/O PORTS 10.2.1 Port Data Register (PDR) Note that R/W for I/O ports differ from R/W for memory in the following points: • Input mode Read: The level at the corresponding pin is read. Write: Data is written to an output latch. •...
Page 187 Reading the port data register The value obtained when reading the port data register (PDR) depends on the status of the port direction register (DDR) and status of the peripheral function connected to the pin. The following shows the value obtained by each combination. Value of DDR 0 (input) 1 (output)
Page 188: Port Direction Register (Ddr)
CHAPTER 10 I/O PORTS 10.2.2 Port Direction Register (DDR) This register has following functions: • Setting the data direction of each pin that is used as a port. • Setting the input level of SIN -- Serial data input pin for LIN-UART. Port Direction Register (DDR) Figure 10.2-3 shows the Port Direction Registers (DDR).
Page 189 Table 10.2-1 SIN0/SIN1 Input Level Setting DDRA SIL0/SIL1 bit Note: SIL0, SIL1 are write-only, and “1” is always read from these bits. Therefore, instructions that perform a read-modify-write (RMW) operation such as the INC/DEC instruction, cannot be used at DDRA. DDRA: Bits 0 to 2, Bits 5 to 7 (unused bits) "1"...
Page 190: Pull-Up Control Register (Pucr)
CHAPTER 10 I/O PORTS 10.2.3 Pull-up Control Register (PUCR) Each pin of port2 has programmable pull-up resistor. Each bit of this register controls corresponding pull-up resistor whether to be used or not. Figure 10.2-4 shows the pull-up control register (PUCR), and Figure 10.2-5 is the block diagram.
Page 191: Analog Input Enable Register (Ader)
10.2.4 Analog Input Enable Register (ADER) Figure 10.2-6 shows the analog input enable register. Analog Input Enable Registers (ADER) Figure 10.2-6 Analog Input Enable Registers (ADER6, ADER5) ADER6 Address: 00000C ADE7 ADER5 Address: 00000B ADE15 ADE14 ADE13 ADE12 ADE11 ADE10 ADE9 R/W: Read/Write Each bit of ADER6/ADER5 sets to enable/disable the analog input of each pin in the port 6 and port 5.
Page 192: Input Level Select Register
CHAPTER 10 I/O PORTS 10.2.5 Input Level Select Register The input level select register allows to switch from Automotive Hysteresis input levels to CMOS Hysteresis input levels. Input Level Select Register (ILSR) The input level select register ILSR is located on addresses 0E Figure 10.2-7 Input Level Select Register (ILSR) Address ILSR1 : 00000F...
Page 193 Initial value of ILSR Initial value of each bit of ILSR is determined when external reset signal is released depending on the value of MD2, MD1, MD0 pin input, as shown in following table. About detail of each mode, please see "CHAPTER 9 MEMORY ACCESS MODES". Table 10.2-2 Relationship between Mode Pin and Initial Value of Input Level Select Register (ILSR) Initial value...
Page 194 CHAPTER 10 I/O PORTS...
Page 195: Chapter 11 Timebase Timer
CHAPTER 11 TIMEBASE TIMER This chapter explains the functions and operations of the timebase timer. 11.1 Overview of Timebase Timer 11.2 Block Diagram of Timebase Timer 11.3 Configuration of Timebase Timer 11.4 Interrupt of Timebase Timer 11.5 Explanation of Operations of Timebase Timer Functions 11.6 Precautions when Using Timebase Timer 11.7 Program Example of Timebase Timer...
Page 196: Overview Of Timebase Timer
CHAPTER 11 TIMEBASE TIMER 11.1 Overview of Timebase Timer The timebase timer is an 18-bit free-run counter (timebase timer counter) that increments in synchronization with the main clock (half frequency of main oscillation clock). • Four interval times can be selected and an interrupt request can be generated for each interval time.
Page 197 Clock Supply The timebase timer supplies an operation clock to the resources such as an oscillation stabilization wait time timer, PPG timer, and watchdog timer. Table 11.1-2 shows the clock cycles supplied from the timebase timer to each resource. Table 11.1-2 Clock Cycles Supplied from Timebase Timer Where to supply clock Oscillation stabilization wait time* Watchdog timer...
Page 198: Block Diagram Of Timebase Timer
CHAPTER 11 TIMEBASE TIMER 11.2 Block Diagram of Timebase Timer The timebase timer consists of the following blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) Block Diagram of Timebase Timer Figure 11.2-1 Block Diagram of Timebase Timer Timebase timer counter /HCLK...
Page 199 Timebase timer counter The timebase timer counter is an 18-bit up counter that uses a clock with a half frequency of the oscillation clock (HCLK) as a count clock. Counter clear circuit The counter clear circuit clears the value of the timebase timer counter by the following factors: •...
Page 200: Configuration Of Timebase Timer
CHAPTER 11 TIMEBASE TIMER 11.3 Configuration of Timebase Timer This section explains the registers and interrupt factors of the timebase timer. List of Registers and Reset Values of Timebase Timer Figure 11.3-1 List of Registers and Reset Values of Timebase Timer Timebase timer control register (TBTC) : Undefined...
Page 201: Timebase Timer Control Register (Tbtc)
11.3.1 Timebase timer control register (TBTC) The timebase timer control register (TBTC) provides the following settings: • Selecting the interval time of the timebase timer • Clearing the counter value of the timebase timer • Enabling or disabling the interrupt request when an overflow occurs •...
Page 202 CHAPTER 11 TIMEBASE TIMER Table 11.3-1 Functions of Timebase Timer Control Register (TBTC) Bit name bit15 Reserved: reserved bit Always set this bit to "1". bit14 Undefined bits Read: The value is undefined. bit13 Write: No effect bit12 TBIE: This bit enables or disables an interrupt when the interval timer bit in the timebase timer Overflow interrupt counter overflows.
Page 203: Interrupt Of Timebase Timer
11.4 Interrupt of Timebase Timer The timebase timer generates an interrupt request (interval timer function) when the interval time bit in the timebase timer counter corresponding to the interval time set by the timebase timer control register carries (overflows). Interrupt of Timebase Timer •...
Page 204: Explanation Of Operations Of Timebase Timer Functions
CHAPTER 11 TIMEBASE TIMER 11.5 Explanation of Operations of Timebase Timer Functions The timebase timer operates as an interval timer or an oscillation stabilization wait time timer. It also supplies a clock to peripherals. Interval Timer Function Interrupt generation at every interval time enables the timebase timer to be used as an interval timer. Operating the timebase timer as an interval timer requires the settings shown in Figure 11.5-1 .
Page 205 At transition to the stop mode, the timebase timer counter is cleared to stop counting up. At return from the stop mode, the timebase timer counts the oscillation stabilization wait time of the main clock. Figure 11.5-2 Example of Operation for Timebase Timer Counter value 3FFFF Oscillation...
Page 206 CHAPTER 11 TIMEBASE TIMER Operation as Oscillation Stabilization Wait Time Timer The timebase timer can be used as the oscillation stabilization wait time timer for the main clock and PLL clock. The oscillation stabilization wait time is the time elapsed from when the timebase timer counter increments from "0"...
Page 207 Table 11.5-1 Clearing Conditions and Oscillation Stabilization Wait Time of Timebase Timer (2/2) Operation Cancellation of stop modes Cancellation of main stop mode Cancellation of PLL stop mode Cancellation of sub-stop mode Cancellation of watch mode Cancellation of sub-watch mode Cancellation of timebase timer modes Return to main clock mode Return to sub clock mode...
Page 208: Precautions When Using Timebase Timer
CHAPTER 11 TIMEBASE TIMER 11.6 Precautions when Using Timebase Timer Precautions when using the timebase timer are shown below. Precautions when Using Timebase Timer Clearing interrupt request To clear the overflow interrupt request flag bit in the timebase timer control register (TBTC: TBOF = 0), disable interrupts (TBTC: TBIE = 0) or mask the timebase timer interrupt by using the interrupt level mask register in the processor status.
Page 209: Program Example Of Timebase Timer
11.7 Program Example of Timebase Timer Programming examples for the timebase timer are shown below. Program Example of Timebase Timer Processing specification The 2 /HCLK (HCLK: oscillation clock) interval interrupt is generated repeatedly. In this case, the interval time is approximately 1.0 ms (at 4-MHz operation). Coding example ICR07 TBTC...
Page 210 CHAPTER 11 TIMEBASE TIMER VECT ENDS WARI 0FFDCH ;Reset vector setting START ;Setting to single-chip mode START...
Page 211: Chapter 12 Watchdog Timer
CHAPTER 12 WATCHDOG TIMER This chapter describes the function and operation of the watchdog timer. 12.1 Overview of Watchdog Timer 12.2 Configuration of Watchdog Timer 12.3 Watchdog Timer Registers 12.4 Explanation of Operations of Watchdog Timer Functions 12.5 Precautions when Using Watchdog Timer 12.6 Program Examples of Watchdog Timer...
Page 212: Overview Of Watchdog Timer
CHAPTER 12 WATCHDOG TIMER 12.1 Overview of Watchdog Timer The watchdog timer is a 2-bit counter that uses the timebase timer or watch timer as a count clock. If the counter is not cleared within a set interval time, the CPU is reset. Functions of Watchdog Timer •...
Page 213 Table 12.1-1 Interval Time of Watchdog Timer Clock cycle External clock(@4MHz) Min. ± 2 Approx. 3.58 ms /HCLK ± 2 Approx. 14.33 ms /HCLK ± 2 Approx. 57.34 ms /HCLK ± 2 Approx. 458.75 ms /HCLK Clock cycle External clock (@32kHz, 4-frequency division) Min.
Page 214 CHAPTER 12 WATCHDOG TIMER Notes: • When the timebase timer output (carry signal) is used as a count clock to the watchdog timer, clearing the timebase timer may extend the time for a watchdog reset to occur. • When the subclock is used as the machine cock, be sure to set the watchdog timer clock source select bit (WDCS) in the watch timer control register (WTC) to "0"...
Page 215: Configuration Of Watchdog Timer
12.2 Configuration of Watchdog Timer The watchdog timer consists of the following blocks: • Count clock selector • Watchdog timer counter (2-bit counter) • Watchdog reset generator • Counter clear control circuit • Watchdog timer control register (WDTC) Block Diagram of Watchdog Timer Figure 12.2-1 Block Diagram of Watchdog Timer Watchdog timer control register (WDTC) PONR...
Page 216 CHAPTER 12 WATCHDOG TIMER Count clock selector The count clock selector selects a count clock input to the watchdog timer from the timebase timer or watch timer. Each timer output has four time intervals that can be set. Watchdog timer counter (2-bit counter) The watchdog timer counter is a 2-bit counter that uses the timebase timer output or watch timer output as a count clock.
Page 217: Watchdog Timer Registers
12.3 Watchdog Timer Registers This section explains the registers used for setting the watchdog timer. List of Registers and Reset Values of Watchdog Timer Figure 12.3-1 List of Registers and Reset Values of Watchdog Timer Watchdog timer control register (WDTC) : Undefined CHAPTER 12 WATCHDOG TIMER Address...
Page 218: Watchdog Timer Control Register (Wdtc)
CHAPTER 12 WATCHDOG TIMER 12.3.1 Watchdog timer control register (WDTC) The watchdog timer control register starts and clears the watchdog timer, sets the interval time, and holds reset factors. Watchdog Timer Control Register (WDTC) Figure 12.3-2 Watchdog Timer Control Register (WDTC) Address PONR WRST ERST SRST WTE WT1...
Page 219 Table 12.3-1 Functions of the Watching Timer Control Register (WDTC) Bit name bit0 WT1, WT0: These bits set the interval time of the watchdog timer. bit1 Interval time select The time interval when the watch timer is used as the bits clock source to the watchdog timer (watchdog clock select bit WDCS= 0) is different from when the main...
Page 220: Explanation Of Operations Of Watchdog Timer Functions
CHAPTER 12 WATCHDOG TIMER 12.4 Explanation of Operations of Watchdog Timer Functions After starting, when the watchdog timer reaches the set interval time without the counter being cleared, a watchdog reset occurs. Operations of Watchdog Timer The operation of the watchdog timer requires the settings shown in Figure 12.4-1 . Watchdog timer control register Watch timer control register : Used bit...
Page 221 Clearing watchdog timer • When "0" is written once again to the watchdog timer control bit (WDTC: WTE) within the interval time after starting the watchdog timer, the watchdog timer is cleared. If the watchdog timer is not cleared within the interval time, it overflows and the CPU is reset. •...
Page 222 CHAPTER 12 WATCHDOG TIMER Checking reset factors The reset factor bits in the watchdog timer control register (WDTC: PONR, WRST, ERST, SRST) can be read after a reset to check the reset factors. Reference: For details on the reset factor bit, see "CHAPTER 7 RESETS". Figure 12.4-2 Relationship between Clear Timing and Interval Time of Watchdog Timer [Watchdog timer block diagram] selector...
Page 223: Precautions When Using Watchdog Timer
12.5 Precautions when Using Watchdog Timer Take the following precautions when using the watchdog timer. Precautions when Using Watchdog Timer Stopping watchdog timer The watchdog timer is stopped by all the reset sources. Interval time • The interval time uses the carry signal of the timebase timer or watch timer as a count clock. If the timebase timer or watch timer is cleared, the interval time of the watchdog timer may become long.
Page 224: Program Examples Of Watchdog Timer
CHAPTER 12 WATCHDOG TIMER 12.6 Program Examples of Watchdog Timer Program example of watchdog timer is given below: Program Examples of Watchdog Timer Processing specification • The watchdog timer is cleared each time in the loop of the main program. •...
Page 225 CHAPTER 13 16-Bit I/O TIMER This chapter explains the function and operation of the 16- bit I/O timer. 13.1 Overview of 16-bit I/O Timer 13.2 Block Diagram of 16-bit I/O Timer 13.3 Configuration of 16-bit I/O Timer 13.4 Interrupts of 16-bit I/O Timer 13.5 Explanation of Operation of 16-bit Free-run Timer 13.6 Explanation of Operation of Input Capture 13.7 Precautions when Using 16-bit I/O Timer...
Page 226: Chapter 13 16-Bit I/O Timer
CHAPTER 13 16-Bit I/O TIMER 13.1 Overview of 16-bit I/O Timer The 16-bit I/O timer consists of one 16-bit free-run timer and 4 input capture. The timer can be performed the measurement of input pulse and external clock cycle based on the 16-bit free-run timer.
Page 227: Block Diagram Of 16-Bit I/O Timer
13.2 Block Diagram of 16-bit I/O Timer The 16-bit I/O timer consists of the following modules: • 16-bit free-run timer • Input capture Block Diagram of 16-bit I/O Timer Figure 13.2-1 Block Diagram of 16-bit I/O Timer 16-bit free-run timer The count value of the 16-bit free-run timer can be used as the base time for the input capture.
Page 228: Details Of Pins And Interrupt Number
CHAPTER 13 16-Bit I/O TIMER Details of Pins and Interrupt Number Table 13.2-1 shows the pins used by the 16-bit details of interrupt. Table 13.2-1 Details of Pins and Interrupt Number Input capture ch0 (using 16-bit free-run timer ch0) Input capture ch1 (using 16-bit free-run timer ch0) Input capture ch2 (using 16-bit free-run timer ch0) Input capture ch3 (using 16-bit free-run timer ch0) 16-bit free-run timer ch0 (overflow interrupt)
Page 229: Block Diagram Of 16-Bit Free-Run Timer
13.2.1 Block Diagram of 16-bit Free-run Timer The MB90360 series contains 1 channel of the 16-bit free-run timer, and it consists of the following block. Block Diagram of 16-bit Free-run Timer Figure 13.2-2 Block Diagram of 16-bit Free-run Timer External clock (FRCK0) φ...
Page 230: Block Diagram Of Input Capture
CHAPTER 13 16-Bit I/O TIMER 13.2.2 Block Diagram of Input Capture The input capture consist of the following blocks: Block Diagram of Input Capture Figure 13.2-3 Block Diagram of Input Capture Unit 0 Edge detection circuit Input capture control status register (ICS23) Input capture control status register (ICS01) LIN-UART1...
Page 231 Input capture data registers 0 to 3 (IPCP0 to IPCP3) • Input capture data register retains the counter value of the 16-bit free-run timer fetched by the capture operation. • Input capture data register 0 to 3 keep the counter value of the 16-bit free-run timer 0 Input capture control status registers 01 to 23 (ICS01 to ICS23) •...
Page 232: Configuration Of 16-Bit I/O Timer
CHAPTER 13 16-Bit I/O TIMER 13.3 Configuration of 16-bit I/O Timer This section explains the pins, registers, and interrupt factors of the 16-bit I/O timer. Pins of 16-bit I/O Timer The pins of the 16-bit I/O timer serve as general-purpose I/O ports. Table 13.3-1 shows the pin functions and the pin settings required to use the 16-bit I/O timer.
Page 233: Timer Control Status Register (Upper) (Tccsh)
13.3.1 Timer Control Status Register (Upper) (TCCSH) Timer control status register (upper) selects the count clock and the conditions for clearing the counter, enables the count operation and interrupt, and checks the interrupt request flag. Timer Control Status Register (Upper) (TCCSH) Figure 13.3-1 Timer Control Status Register (Upper) (TCCSH) Address TCCSH0 : 007943...
Page 234: Timer Control Status Register (Lower) (Tccsl)
CHAPTER 13 16-Bit I/O TIMER 13.3.2 Timer Control Status Register (Lower) (TCCSL) The timer control status register (Lower) selects the count clock and conditions for clearing the counter, clears the counter, enables the count operation or interrupt, and checks the interrupt request flag. Timer Control Status Register (Lower) (TCCSL) Figure 13.3-2 Timer Control Status Register (Lower) (TCCSL) Address...
Page 235 Table 13.3-3 Functions of Timer Control Status Register (Lower) (TCCSL) Bit name bit7 IVF: Timer overflow generation flag bit bit6 IVFE: Timer overflow interrupt enable bit bit5 STOP: Timer operation stop bit bit4 Reserved bit bit3 CLR: Timer clear bit bit2 CLK2, CLK1, CLK0: bit1...
Page 236: Timer Data Register (Tcdt)
CHAPTER 13 16-Bit I/O TIMER 13.3.3 Timer Data Register (TCDT) The timer data register is a 16-bit up counter. • The counter value of the 16-bit free-run timer is read. • The counter value can be set during stopping of the 16-bit free-run timer. Timer Data Register (TCDT) Address TCDT0 upper: 007941...
Page 237: Input Capture Control Status Registers (Ics)
13.3.4 Input Capture Control Status Registers (ICS) The function of the input capture control status register is shown below. The correspondence between ICS01 to ICS23 and input pin is as follows. • ICS01: IN0, IN1 input capture ch0, ch1 • ICS23: IN2, IN3 input capture ch2, ch3 Input Capture Control Status Registers (ICS01, ICS23) Figure 13.3-4 Input Capture Control Status Registers (ICS) Address...
Page 238 CHAPTER 13 16-Bit I/O TIMER Table 13.3-4 Functions of Input Capture Control Status Register (ICS) Bit name bit7 ICPm: Valid edge detection flag bit m bit6 ICPn: Valid edge detection flag bit n bit5 ICEm: Capture interrupt enable bit m bit4 ICEn: Capture interrupt enable bit n...
Page 239: Input Capture Register (Ipcp)
13.3.5 Input Capture Register (IPCP) Input capture register stores the counter value fetched from 16-bit free-run timer by the capture operation. The IPCP register is the 16-bit read-only register and has the input capture registers 0 to 3 (IPCP0 to IPCP3). Input Capture Register (IPCP) Figure 13.3-5 Input Capture Register (IPCP) IPCP0 (upper): 007921...
Page 240: Input Capture Edge Register (Ice)
CHAPTER 13 16-Bit I/O TIMER 13.3.6 Input Capture Edge Register (ICE) The input capture edge register has a function to indicate the selected edge direction and to select whether the input signal is inputted from either external pin or LIN-UART. By cooperating with the LIN-UART, the baud rate measurement at the LIN slave operation can be performed.
Page 241 Table 13.3-5 Functions of Input Capture Edge Register 01 (ICE01) Bit name bit15 Undefined bits bit13 bit12 ICUS1: Input signal selection bit 1 bit11 Undefined bit bit10 ICUS0: Input signal selection bit 0 bit9 IEI1: Detection edge indication bit 1 bit8 IEI0: Detection edge indication bit 0...
Page 242 CHAPTER 13 16-Bit I/O TIMER Table 13.3-6 Functions of Input Capture Edge Register 23 (ICE23) Bit name bit15 Undefined bits bit10 bit9 IEI3: Detection edge indication bit 3 bit8 IEI2 : Detection edge indication bit 2 Note: In the input capture 0 and 1, if the input signal is selected to the LIN-UART (ICE01:ICUS), the input capture is used to calculate the baud rate when the LIN-UART operates the LIN slave.
Page 243: Interrupts Of 16-Bit I/O Timer
13.4 Interrupts of 16-bit I/O Timer The interrupt factors of the 16-bit I/O timer has overflow of the counter value in the 16- bit free-run timer, trigger edge input to the input capture input pin, and trigger edge input for the LIN slave baud rate measurement from the LIN-UART. The EI OS can be started by the interrupt of the input capture.
Page 244 CHAPTER 13 16-Bit I/O TIMER 16-bit I/O Timer Interrupt and EI Reference: For details of the interrupt number, interrupt control register, and interrupt vector address, see "CHAPTER 3 INTERRUPTS". Correspondence to EI OS Function The input capture corresponds to the EI However, to use the EI control register (ICR).
Page 245: Explanation Of Operation Of 16-Bit Free-Run Timer
13.5 Explanation of Operation of 16-bit Free-run Timer After a reset, the 16-bit free-run timer starts incrementing from "0000 value of the 16-bit free-run timer is the base time of the input capture. Explanation of Operation of 16-bit Free-run Timer Operation of the 16-bit free-run timer requires the setting shown in Figure 13.5-1 .
Page 246 CHAPTER 13 16-Bit I/O TIMER Figure 13.5-2 shows counter clearing at an overflow. Figure 13.5-2 Counter Clearing at an Overflow Counter value F F F F BFFF 7 F F F 3 F F F 0 0 0 0 Reset Overflow Time...
Page 247: Explanation Of Operation Of Input Capture
13.6 Explanation of Operation of Input Capture The input capture stores the counter value of the 16-bit free-run timer to the input capture register at the timing that is detected the input signal of the valid edge from the external input pin or that the trigger edge for the LIN slave baud rate measurement is inputted, the interrupt request is generated.
Page 248 CHAPTER 13 16-Bit I/O TIMER Figure 13.6-2 Timing of Fetching Data for Input Capture φ Counter value Input capture input Capture signal Capture register φ : Machine clock Figure 13.6-3 Operation of Input Capture (Rising edge/falling edge) Counter value F F F F B F F F 7 F F F 3 F F F...
Page 249: Precautions When Using 16-Bit I/O Timer
13.7 Precautions when Using 16-bit I/O Timer This section explains the precautions when using the 16-bit I/O timer. Precautions when Using 16-bit I/O Timer Precautions when setting 16-bit free-run timer • Do not change the count clock select bits (TCCSL: CLK2, CLK1, CLK0) during the operation in the 16- bit free-run timer (TCCSL: STOP = 0).
Page 250: Program Example Of 16-Bit I/O Timer
CHAPTER 13 16-Bit I/O TIMER 13.8 Program Example of 16-bit I/O Timer This section gives a program example of the 16-bit I/O timer. Program Example of 16-bit I/O Timer Processing specification • The cycle of a signal input to the IN0 pin is measured. •...
Page 251 I:ICS01,#00010001B ;IN0 pin selection, External trigger, ILM,#07H CCR,#40H LOOP: User processing LOOP ;---------Interrupt program--------------------------------------------- WARI0: CLRB I:ICP0 User processing OV_CNT,A RETI WARI1: CLRB I:IVF0 OV_CNT User processing RETI CODE ENDS ;---------Vector setting------------------------------------------------ VECT CSEG ABS=0FFH 00FF78H WARI0 00FF84H WARI1 00FFDCH START VECT ENDS...
Page 252 CHAPTER 13 16-Bit I/O TIMER...
Page 253: Chapter 14 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER This chapter describes the functions and operation of the 16-bit reload timer. 14.1 Overview of the 16-bit Reload Timer 14.2 Block Diagram of 16-bit Reload Timer 14.3 Configuration of 16-bit Reload Timer 14.4 Interrupts of 16-bit Reload Timer 14.5 Explanation of Operation of 16-bit Reload Timer 14.6 Precautions when Using 16-bit Reload Timer 14.7 Sample Program of 16-bit Reload Timer...
Page 254: Overview Of The 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER 14.1 Overview of the 16-bit Reload Timer The 16-bit reload timer has the following functions: • The count clock can be selected from three internal clocks and external event clocks. • A software trigger or external trigger can be selected as the start trigger. •...
Page 255: Operation At Underflow
Operation at Underflow When the start trigger is inputted, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16- bit timer register, starting decrementing in synchronization with the count clock. When the 16-bit timer register (TMR) is decremented from "0000 •...
Page 256: Block Diagram Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER 14.2 Block Diagram of 16-bit Reload Timer The 16-bit reload timers 2 and 3 composed of the following seven blocks: • Count clock generator • Reload controller • Output controller • Operation controller • 16-bit timer register (TMR) •...
Page 257 Details of pins in block diagram There are two channels for 16-bit reload timer. The actual pin names, outputs to resources, and interrupt request numbers for each channel are as follows: Table 14.2-1 Pin Names, Outputs to Resources, and Interrupt Request Numbers of 16-bit Reload Timer TIN pin TOT pin...
Page 258: Configuration Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER 14.3 Configuration of 16-bit Reload Timer This section explains the pins, registers, and interrupt factors of the 16-bit reload timer. Pins of 16-bit Reload Timer The pins of the 16-bit reload timer serve as general-purpose I/O ports. Table 14.3-1 shows the pin functions and the pin settings required to use the 16-bit reload timer.
Page 259: Bit Reload Timer Registers And Reset Value
16-bit Reload Timer Registers and Reset Value 16-bit reload timer 2 register Figure 14.3-1 List of 16-bit Reload Timer 2 Register and Reset Value Timer Control Status Register Upper (TMCSR2) Timer Control Status Register Lower (TMCSR2) 16-bit Timer Register Upper (TMR2) 16-bit Timer Register Lower (TMR2) 16-bit Reload Register Upper (TMRLR2) 16-bit Reload Register Lower (TMRLR2)
Page 260 CHAPTER 14 16-BIT RELOAD TIMER Generation of Interrupt Request from 16-bit Reload Timer When the 16-bit reload timer is started and the count value of the 16-bit timer register is decremented from "0000 " to "FFFF status register is set to 1 (TMCSR:UF). If an underflow interrupt is enabled (TMCSR:INTE = 1), an interrupt request is generated.
Page 261: Timer Control Status Registers (High) (Tmcsr:h)
14.3.1 Timer Control Status Registers (High) (TMCSR:H) The timer control status registers (High) (TMCSR:H) set the operation mode and count clock. This section also explains the bit 7 in the timer control status registers (Low) (TMCSR:L). Timer Control Status Registers (High) (TMCSR:H) Figure 14.3-3 Timer Control Status Registers (High) (TMCSR:H) Address: TMCSR2 : 000065...
Page 262 CHAPTER 14 16-BIT RELOAD TIMER Table 14.3-2 Functions of Timer Control Status Registers (High) (TMCSR: H) Bit name bit15 Undefined bits bit12 bit11 CSL1, CSL0: bit10 Count clock select bits bit9 MOD2, MOD1, MOD0: Operating mode select bit7 bits Function Read: The value is undefined.
Page 263: Timer Control Status Registers (Low) (Tmcsr: L)
14.3.2 Timer Control Status Registers (Low) (TMCSR: L) The timer control status registers (Low) (TMCSR:L) enables or disable the timer operation, check the generation of a software trigger or an underflow, enables or disable an underflow interrupt, select the reload mode, and set the output of the TOT pin.
Page 264 CHAPTER 14 16-BIT RELOAD TIMER Table 14.3-3 Timer Control Status Registers (Low) (TMCSR: L) Bit Name bit6 OUTE: TOT pin Output enable bit bit5 OUTL: TOT Pin output level select bit4 RELD: Reload select bit bit3 INTE: Underflow interrupt enable bit2 Underflow generating flag bit1...
Page 265: 16-Bit Timer Registers (Tmr)
14.3.3 16-bit Timer Registers (TMR) The 16-bit timer registers are 16-bit down counters. At read, the value being counted is read. 16-bit Timer Registers (TMR) Address: TMR2 : 00794D TMR3 : 00794F Address: TMR2 : 00794C TMR3 : 00794E : Read only : Undefined When the timer operation is enabled (TMCSR:CNTE = 1) and the start trigger is inputted, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count...
Page 266: 16-Bit Reload Registers (Tmrlr)
CHAPTER 14 16-BIT RELOAD TIMER 14.3.4 16-bit Reload Registers (TMRLR) The 16-bit reload registers set the value to be reloaded to the 16-bit timer register (TMR). When the start trigger is inputted, the value set in the 16-bit reload registers is reloaded to the TMR, starting the TMR count operation.
Page 267: Interrupts Of 16-Bit Reload Timer
14.4 Interrupts of 16-bit Reload Timer The 16-bit reload timer generates an interrupt request when the 16-bit timer register (TMR) underflows. Interrupts of 16-bit Reload Timer When the value of the TMR is decremented from "0000 underflow occurs. When an underflow occurs, the underflow generating flag bit in the timer control status register (TMCSR:UF) is set to l.
Page 268: Explanation Of Operation Of 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER 14.5 Explanation of Operation of 16-bit Reload Timer This section explains the setting of the 16-bit reload timer and the operation state of the counter. Setting of 16-bit Reload Timer Setting of internal clock mode Counting the internal clock requires the setting shown in Figure 14.5-1 .
Page 269: Operating State Of 16-Bit Timer Register
Operating State of 16-bit Timer Register The operating state of the 16-bit timer register is determined by the timer operation enable bit in the timer control status register (TMCSR:CNTE) and the WAIT signal. The operating states include the stop state, start trigger input wait state (WAIT state), and RUN state.
Page 270: Operation In Internal Clock Mode
CHAPTER 14 16-BIT RELOAD TIMER 14.5.1 Operation in Internal Clock Mode In the internal clock mode, three operation modes can be selected by setting the operating mode select bits in the timer control status register (TMCSR:MOD2 to MOD0).When the operation mode and reload mode are set, a rectangular wave or a toggle wave is outputted from the TOT pin.
Page 271 Operation as 16-bit Timer Register Underflows When the value of the 16-bit timer register (TMR) is decremented from "0000 TMR count operation, an underflow occurs. • When an underflow occurs, the underflow generating flag bit in the timer control status register (TMCSR:UF) is set to 1.
Page 272 CHAPTER 14 16-BIT RELOAD TIMER Figure 14.5-4 Count Operation in Software Trigger Mode (One-shot Mode) Counter clock Counter Rel o ad data Data load signal UF bit CNTE bit TRG bit TOT pin T: Machine cycle * : It takes 1 machine cycle (time) to load data of reload register from trigger input. Figure 14.5-5 Count Operation in Software Trigger Mode (Reload Mode) Count clock Counter...
Page 273 [External trigger mode (MOD2 to MOD0="001 When the external trigger mode is set, the 16-bit reload timer is started by inputting the external valid edge to the TIN pin. When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR), starting the TMR count operation.
Page 274 CHAPTER 14 16-BIT RELOAD TIMER [External gate input mode (MOD2 to MOD0="1x0 When the external gate input mode is set, start the 16-bit reload timer by setting the software trigger bit in the timer control status register (TMCSR:TRG) to 1. When the 16-bit reload timer is started, the value set in the 16-bit reload register (TMRLR) is reloaded to the 16-bit timer register (TMR).
Page 275: Operation In Event Count Mode
14.5.2 Operation in Event Count Mode In the event count mode, after the 16-bit reload timer is started, the edge of the signal input to the TIN pin is detected to perform the count operation of the 16-bit timer register (TMR). When the operation mode and the reload mode are set, a rectangular wave or a toggle wave is outputted from the TOT pin.
Page 276 CHAPTER 14 16-BIT RELOAD TIMER Operation as 16-bit Timer Register Underflows When the value of the 16-bit timer register (TMR) is decremented from "0000 TMR count operation, an underflow occurs. • When an underflow occurs, the underflow generating flag bit in the timer control status register (TMCSR:UF) is set to 1.
Page 277 Operation in Event Count Mode The operation of the 16-bit reload timer is enabled by setting the timer operation enable bit in the timer control status register (TMCSR:CNTE) to 1. When the software trigger bit in the timer control status register (TMCSR:TRG) is set to 1, the 16-bit reload timer is started.
Page 278: Precautions When Using 16-Bit Reload Timer
CHAPTER 14 16-BIT RELOAD TIMER 14.6 Precautions when Using 16-bit Reload Timer This section explains the precautions when using the 16-bit reload timer. Precautions when Using 16-bit Reload Timer Precautions when setting by program • Set the 16-bit reload register (TMRLR) after disabling the timer operation (TMCSR:CNTE = 0) •...
Page 279: Sample Program Of 16-Bit Reload Timer
14.7 Sample Program of 16-bit Reload Timer This section gives a program example of the 16-bit reload timer operated in the internal clock mode and the event count mode: Program Example in Internal Clock Mode Processing specification • The 24 ms interval timer interrupt is generated by the 16-bit reload timer 2. •...
Page 280: Program Example In Event Counter Mode
CHAPTER 14 16-BIT RELOAD TIMER ;---------Interrupt program----------------------------------- WARI: Processing by user RETI CODE ENDS ;---------Vector setting---------------------------------------- VECT CSEG ABS=0FFH VECT ENDS Program Example in Event Counter Mode Processing specification • An interrupt is generated when rising edges of the pulse input to the external event input pin are counted 10000 times by the 16-bit reload timer 2.
Page 281 CCR,#0BFH I:ICR04,#00H I:DDR8,00H CLRB I:CNTE0 MOVW I:TMRLR2,#2710H;Reload value set to 10000 times MOVW I:TMCSR2,#0000110001001011B ILM,#07H CCR,#40H LOOP: Processing by user LOOP ;---------Interrupt program----------------------------------- WARI: I:UF2 Processing by user RETI CODE ENDS ;---------Vector setting---------------------------------------- VECT CSEG ABS=0FFH 00FFB0H WARI 00FFDCH START VECT ENDS START...
Page 282 CHAPTER 14 16-BIT RELOAD TIMER...
Page 283: Chapter 15 Watch Timer
CHAPTER 15 WATCH TIMER This chapter describes the functions and operations of the watch timer. 15.1 Overview of Watch Timer 15.2 Block Diagram of Watch Timer 15.3 Configuration of Watch Timer 15.4 Watch Timer Interrupt 15.5 Explanation of Operation of Watch Timer 15.6 Program Example of Watch Timer...
Page 284: Overview Of Watch Timer
CHAPTER 15 WATCH TIMER 15.1 Overview of Watch Timer The watch timer is a 15-bit free-run counter that increments in synchronization with the subclock. • Eight interval times can be selected and an interrupt request can be generated for each interval time. •...
Page 285 Cycle of Clock Supply The watch timer supplies an operation clock to the oscillation stabilization wait time timer of the subclock and the watchdog timer. Table 15.1-2 shows the cycles of clocks supplied from the watch timer. Table 15.1-2 Cycle of Clock Supplied from Watch Timer Where to Supply Clock Timer for oscillation stabilization wait time of subclock Watchdog timer...
Page 286: Block Diagram Of Watch Timer
CHAPTER 15 WATCH TIMER 15.2 Block Diagram of Watch Timer The watch timer consists of the following blocks: • Watch timer counter • Counter clear circuit • Interval timer selector • Watch timer control register (WTC) Block Diagram of Watch Timer Figure 15.2-1 Block Diagram of Watch Timer Watch timer counter ×...
Page 287 Interval timer selector The interval timer selector sets the overflow flag bit when the watch timer counter reaches the interval time set in the watch timer control register (WTC). Watch timer control register (WTC) The watch timer control register (WTC) selects the interval time, clears the watch timer counter, enables or disables an interrupt, checks the overflow (carry) state, and clears the overflow flag bit.
Page 288: Configuration Of Watch Timer
CHAPTER 15 WATCH TIMER 15.3 Configuration of Watch Timer This section explains the registers and interrupt factors of the watch timer. List of Registers and Reset Values of Watch Timer Figure 15.3-1 List of Registers and Reset Values of Watch Timer Watch timer control register (WTC) Address: 0000AA : Undefined...
Page 289: Watch Timer Control Register (Wtc)
15.3.1 Watch Timer Control Register (WTC) This section explains the functions of the watch timer control register (WTC). Watch Timer Control Register (WTC) Figure 15.3-2 Watch Timer Control Register (WTC) Address WDCS WTIE WTOF 0000AA : Read/Write : Read only : Undefined SCLK : Subclock : Reset value...
Page 290 CHAPTER 15 WATCH TIMER Table 15.3-1 Functions of Watch Timer Control Register (WTC) Bit Name bit7 WDCS: Watchdog clock select bit bit6 SCE: Oscillation stabilization wait time end bit bit5 WTIE: Overflow interrupt enable bit bit4 WTOF: Overflow flag bit bit3 WTR: Watch timer clear bit...
Page 291: Watch Timer Interrupt
15.4 Watch Timer Interrupt When the interval time is reached with the watch timer interrupt enabled, the overflow flag bit is set to "1" and an interrupt request is generated. Watch Timer Interrupt Table 15.4-1 shows the interrupt control bits and interrupt factors of the watch timer. Table 15.4-1 Interrupt Control Bits of Watch Timer Interrupt factor Interrupt request flag bit...
Page 292: Explanation Of Operation Of Watch Timer
CHAPTER 15 WATCH TIMER 15.5 Explanation of Operation of Watch Timer The watch timer operates as an interval timer or an oscillation stabilization wait time timer of subclock. It also supplies an operation clock to the watchdog timer. Watch Timer Counter The watch timer counter continues incrementing in synchronization with the subclock (SCLK) while the subclock (SCLK) is operating.
Page 293: Setting Operation Clock Of Watchdog Timer
Clearing overflow flag bit (WTC:WTOF) When the mode is switched to the stop mode, the watch timer is used as an oscillation stabilization wait time timer of subclock. The WTOF bit is cleared concurrently with mode switching. Setting Operation Clock of Watchdog Timer The watchdog clock select bit (WDCS) in the watch timer control register (WTC) can be used to set the clock input source of the watchdog timer.
Page 294: Program Example Of Watch Timer
CHAPTER 15 WATCH TIMER 15.6 Program Example of Watch Timer This section gives a program example of the watch timer. Program Example of Watch Timer Processing specifications An interval interrupt at 2 approximately 1.0 s (when subclock operates at 8.192 kHz). Coding example ICR08 WTOF...
Page 295 00FFDCH START VECT ENDS START CHAPTER 15 WATCH TIMER ;Reset vector set ;Set to single-chip mode...
Page 296 CHAPTER 15 WATCH TIMER...
Page 297: Chapter 16 8-/16-Bit Ppg Timer
CHAPTER 16 8-/16-BIT PPG TIMER This chapter describes the functions and operations of the 8-/16-bit PPG timer. 16.1 Overview of 8-/16-bit PPG Timer 16.2 Block Diagram of 8-/16-bit PPG Timer 16.3 Configuration of 8-/16-bit PPG Timer 16.4 Interrupts of 8-/16-bit PPG Timer 16.5 Explanation of Operation of 8-/16-bit PPG Timer 16.6 Precautions when Using 8-/16-bit PPG Timer...
Page 298: Overview Of 8-/16-Bit Ppg Timer
CHAPTER 16 8-/16-BIT PPG TIMER 16.1 Overview of 8-/16-bit PPG Timer The 8-/16-bit PPG timer is a reload timer module with two channels (PPGC and PPGD) that outputs a pulse in any cycle and at any duty ratio. A combination of two channels provides: •...
Page 299: Operation Modes Of 8-/16-Bit Ppg Timer
Operation Modes of 8-/16-bit PPG Timer 8-bit PPG output 2-channel independent operation mode The 8-bit PPG output 2-channel independent operation mode causes the 2-channel modules (PPGC and PPGD) to operate as each independent 8-bit PPG timer. Table 16.1-1 shows the interval times in the 8-bit PPG output 2-channel independent operation mode. Table 16.1-1 Interval Times in 8-bit PPG Output 2-channel Independent Operation Mode Count Clock Cycle 1/φ(41.7 ns)
Page 300 CHAPTER 16 8-/16-BIT PPG TIMER 8+8-bit PPG output operation mode The 8 + 8-bit PPG output operation mode causes the PPGC of the 2-channel modules to operate as an 8-bit prescaler and the underflow output of the PPGC to operate as the count clock of the PPGD. Table 16.1-3 shows the interval times in this mode.
Page 301: Block Diagram Of 8-/16-Bit Ppg Timer
16.2 Block Diagram of 8-/16-bit PPG Timer The MB90360 series contains two 8-/16-bit PPG timers (each with 2 channels). One 8-/16-bit PPG timer consists of 8-bit PPG timers with two channels. This section shows the block diagrams for the 8-/16-bit PPG timer C and 8-/16-bit PPG timer D.
Page 302: Block Diagram For 8-/16-Bit Ppg Timer C
CHAPTER 16 8-/16-BIT PPG TIMER 16.2.1 Block Diagram for 8-/16-bit PPG Timer C The 8-/16-bit PPG timer C consists of the following blocks. Block Diagram of 8-/16-bit PPG Timer C Figure 16.2-2 Block Diagram of 8-/16-bit PPG Timer C PPGC reload register PRLHC (High level side)
Page 303 Details of pins in block diagram Table 16.2-1 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 16.2-1 Pins and Interrupt Request Numbers in Block Diagram Channel PPGC PPGD PPGE PPGF PPG operation mode control register C (PPGCC) This register enables or disables operation of the 8-/16-bit PPG timer, pin output and an underflow interrupt.
Page 304: Block Diagram Of 8-/16-Bit Ppg Timer D
CHAPTER 16 8-/16-BIT PPG TIMER 16.2.2 Block Diagram of 8-/16-bit PPG Timer D The 8-/16-bit PPG timer D consists of the following blocks. Block Diagram of 8-/16-bit PPG Timer D Figure 16.2-3 Block Diagram of 8-/16-bit PPG Timer D PPGD reload register PRLHD (High level side)
Page 305 Details of pins in block diagram Table 16.2-2 lists the actual pin names and interrupt request numbers of the 8-/16-bit PPG timer. Table 16.2-2 Pins and Interrupt Request Numbers in Block Diagram Channel PPGC PPGD PPGE PPGF PPG operation mode control register D (PPGCD) This register sets the operation mode of the 8-/16-bit PPG timer, enables or disables the operation of the 8-/ 16-bit PPG timer D, the pin output and an underflow interrupt, and also indicates the generation of an underflow.
Page 306: Configuration Of 8-/16-Bit Ppg Timer
CHAPTER 16 8-/16-BIT PPG TIMER 16.3 Configuration of 8-/16-bit PPG Timer This section explains the pins, registers and interrupt factors of the 8-/16-bit PPG timer. Pins of 8-/16-bit PPG Timer The pins of the 8-/16-bit PPG timer serve as general-purpose I/O ports. Table 16.3-1 indicates the pin functions and pin settings required to use the 8-/16-bit PPG timer.
Page 307 List of Registers and Reset Values of 8-/16-bit PPG Timer Figure 16.3-1 List of Registers and Reset Values of 8-/16-bit PPG Timer PPGm operation mode control register: H (PPGCm) PPGn operation mode control register: L (PPGCn) PPGn/m count clock select register (PPGnm) PPGn reload register: H(PRLHn) PPGn reload register: L(PRLLn)
Page 308: Ppgc Operation Mode Control Register (Ppgcc)
CHAPTER 16 8-/16-BIT PPG TIMER 16.3.1 PPGC Operation Mode Control Register (PPGCC) The PPGC operation mode control register (PPGC0) provides the following settings for the operation of 8-/16-bit PPG timer C: • Enabling or disabling operation of 8-/16-bit PPG timer C •...
Page 309 Table 16.3-2 Functions of PPGC Operation Mode Control Register (PPGCC) Bit Name bit7 PEN0: PPG0 operation enable bit bit6 Undefined bit bit5 PE0: PPG0 pin output enable bit bit4 PIE0: Underflow interrupt enable bit3 PUF0: Underflow generation flag bit2 Undefined bits bit1 bit0 Reserved: Reserved bit...
Page 310: Ppgd Operation Mode Control Register (Ppgcd)
CHAPTER 16 8-/16-BIT PPG TIMER 16.3.2 PPGD Operation Mode Control Register (PPGCD) The PPGD operation mode control register provides the following settings about operation of 8-/16-bit PPG timer D: • Enabling or disabling operation of 8-/16-bit PPG timer D • Switching between pin functions (enabling or disabling pulse output) •...
Page 311 Table 16.3-3 Functions of PPGD Operation Mode Control Register (PPGCD) Bit name bit15 PEN1: PPG1 operation enable bit bit14 Undefined bit bit13 PE1: PPG1 Pin output enable bit bit12 PIE1: Underflow interrupt enable bit11 PUF1: Underflow generation flag bit10 MD1, MD0: bit9 Operation mode select bits bit8...
Page 312: Ppgc/D Count Clock Select Register (Ppgcd)
CHAPTER 16 8-/16-BIT PPG TIMER 16.3.3 PPGC/D Count Clock Select Register (PPGCD) The PPGC/D count clock select register selects the count clock of the 8-/16-bit PPG timers C and D and the output pin. This section explains the PPGCD function only. The PPGEF has the same function as the PPGCD, and the 8-/16-bit PPG timers E and F are set.
Page 313 Table 16.3-4 Functions of PPGC/D Count Clock Select Register (PPGCD) Bit Name bit7 PCS2 to PCS0: PPGD count clock select bits bit5 bit4 PCM2 to PCM0: PPGC count clock select bits bit2 bit1 Undefined bit bit0 REV: PPG output pin select bit CHAPTER 16 8-/16-BIT PPG TIMER Function These bits set the count clock of the 8-/16-bit PPG timer D.
Page 314: Ppg Reload Registers (Prllc/Prlhc, Prlld/Prlhd)
CHAPTER 16 8-/16-BIT PPG TIMER 16.3.4 PPG Reload Registers (PRLLC/PRLHC, PRLLD/PRLHD) The value (reload value) from which the PPG down counter starts counting is set in the PPG reload registers, which are an 8-bit register at Low level and an 8-bit register at High level.
Page 315: Interrupts Of 8-/16-Bit Ppg Timer
16.4 Interrupts of 8-/16-bit PPG Timer The 8-/16-bit PPG timer can generate an interrupt request when the PPG down counter underflows. It also not corresponds to the EI Interrupts of 8-/16-bit PPG Timer Table 16.4-1 shows the interrupt control bits and interrupt factor of the 8-/16-bit PPG timer. Table 16.4-1 Interrupt Control Bits of 8-/16-bit PPG Timer Interrupt request flag bit Interrupt request enable bit...
Page 316: Explanation Of Operation Of 8-/16-Bit Ppg Timer
CHAPTER 16 8-/16-BIT PPG TIMER 16.5 Explanation of Operation of 8-/16-bit PPG Timer The 8-/16-bit PPG timer outputs a pulse width at any frequency and at any duty ratio continuously. Operation of 8-/16-bit PPG Timer Output operation of 8-/16-bit PPG timer •...
Page 317: 8-Bit Ppg Output 2-Channel Independent Operation Mode
16.5.1 8-bit PPG Output 2-channel Independent Operation Mode In the 8-bit PPG output 2-channel independent operation mode, the 8-/16-bit PPG timer is set as an 8-bit PPG timer with two independent channels. PPG output operation and interrupt request generation can be performed independently for each channel. Setting for 8-bit PPG Output 2-channel Independent Operation Mode Operating the 8-/16-bit PPG timer in the 8-bit PPG output 2-channel independent operation mode requires the setting shown in Figure 16.5-2 .
Page 318 CHAPTER 16 8-/16-BIT PPG TIMER Operation in 8-bit PPG output 2-channel independent operation mode • The 8-bit PPG timer with two channels performs an independent PPG operation. • When the pin output is enabled (PPGCn: PEC=1, PPGCm: PED=1), if the PPG output pin selection is set to standard (PPGnm:REV=0), the PPGn pulse wave is outputted from the PPGn pin and the PPGm pulse wave is outputted from the PPGm pin.
Page 319 Output waveform in 8-bit PPG output 2-channel independent operation mode The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register is "00 ", the pulse width has one count clock cycle, and if the value is "FF clock cycles.
Page 320: 16-Bit Ppg Output Operation Mode
CHAPTER 16 8-/16-BIT PPG TIMER 16.5.2 16-bit PPG Output Operation Mode In the 16-bit PPG output operation mode, the 8-/16-bit PPG timer is set as a 16-bit PPG timer with one channel. Setting for 16-bit PPG Output Operation Mode Operating the 8-/16-bit PPG timer in the 16-bit PPG output operation mode requires the setting shown in Figure 16.5-4 .
Page 321 Operation in 16-bit PPG output operation mode • When either PPGn pin output or PPGm pin output is enabled (PPGCn:PEC=1, PPGCm: PED=1), the same pulse wave is outputted from both the PPGn and PPGm pins. • When the reload value is set in the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) to enable operation of the PPG timer (PPGCn:PENC=1 and PPGCm: PEND=1), the PPG down counters start counting as 16-bit down counters (PCNTn + PCNTm).
Page 322 CHAPTER 16 8-/16-BIT PPG TIMER Output waveform in 16-bit PPG output operation mode The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle. For example, if the value in the PPG reload register is "0000 ", the pulse width has one count clock cycle, and if the value is "FFFF count clock cycles.
Page 323: 8+8-Bit Ppg Output Operation Mode
16.5.3 8+8-bit PPG Output Operation Mode In the 8 + 8-bit PPG output operation mode, the 8-/16-bit PPG timer is set as an 8-bit PPG timer. The PPGC operates as an 8-bit prescaler and the PPG operates using the PPG output of the PPGC as a clock source. Setting for 8+8-bit PPG Output Operation Mode Operating the 8-/16-bit PPG timer in the 8+8-bit PPG output operation mode requires the setting shown in Figure 16.5-6 .
Page 324 CHAPTER 16 8-/16-BIT PPG TIMER Operation in 8+8-bit PPG output operation mode • The PPGn operates as the prescaler of the PPGm timer and the PPGm operates using the PPGn output as a clock source. • When the pin output is enabled (PPGCn: PE0=1, PPGCm: PE1=1) if PPG output pin selection is set to standard (PPGnm:REV=0), PPGn pulse wave is outputted from the PPGn pin and the PPGm pulse wave is outputted from the PPGm pin.
Page 325 Output waveform in 8+8-bit PPG output operation mode The High and Low pulse widths to be outputted are determined by adding 1 to the value in the PPG reload register and multiplying it by the count clock cycle. The equations for calculating the pulse width are shown below: PL=T ×...
Page 326: Precautions When Using 8-/16-Bit Ppg Timer
CHAPTER 16 8-/16-BIT PPG TIMER 16.6 Precautions when Using 8-/16-bit PPG Timer This section explains the precautions when using the 8-/16-bit PPG timer. Precautions when Using 8-/16-bit PPG Timer Effect on 8-/16-bit PPG timer when using timebase timer output • If the output signal of the timebase timer is used as the input signal for the count clock of the 8-/16-bit PPG timer (PPGnm: PCM2 to PCM0="111 count cycle in which the PPG timer is started by trigger input or in the count cycle immediately after the PPG timer is stopped.
Page 327 Figure 16.6-1 Waveform when Values in PPG Reload Registers Rewritten Using Byte Instruction PRLL PRLH A + B A + B PPG pin <1>: Change the value (A → C) of PPG reload register (PRLL) <2>: Change the value (B → D) of PPG reload register (PRLH) Setting of PPG reload registers when using 16-bit PPG timer Use a long-word instruction to set the PPG reload registers (PRLLn/PRLHn, PRLLm/PRLHm) or a word instruction to set the word instruction to set the PPGn and PPGm (PRLLn -->...
Page 328 CHAPTER 16 8-/16-BIT PPG TIMER Figure 16.6-2 Reload Timing in 16-bit PPG Output Operation Mode Reload value of PPGn Write to PPGn except 16-bit PPG output operation mode Note: n = C, E m = n+1 Only 16-bit PPG output operation mode Temporary latch Transfers synchronously with writing to PPGm...
Page 329: Chapter 17 Dtp/External Interrupts
CHAPTER 17 DTP/EXTERNAL INTERRUPTS This chapter explains the functions and operations of DTP/external interrupt. 17.1 Overview of DTP/External Interrupt 17.2 Block Diagram of DTP/External Interrupt 17.3 Configuration of DTP/External Interrupt 17.4 Explanation of Operation of DTP/External Interrupt 17.5 Precautions when Using DTP/External Interrupt 17.6 Program Example of DTP/External Interrupt Function...
Page 330: Overview Of Dtp/External Interrupt
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.1 Overview of DTP/External Interrupt The DTP/external interrupt sends interrupt requests from external peripheral devices or data transfer requests to the CPU to generate an external interrupt request, or starts the DTP/External Interrupt Function The DTP/external interrupt follows the same procedure as resource interrupts to send interrupt requests from external peripheral devices to the CPU to generate an external interrupt request, or starts the EI If the EI OS is disabled in the interrupt control register (ICR: ISE=0), the external interrupt function is...
Page 331: Block Diagram Of Dtp/External Interrupt
17.2 Block Diagram of DTP/External Interrupt The block diagram of the DTP/external interrupt is shown below. Block Diagram of DTP/External Interrupt Figure 17.2-1 Block Diagram of DTP/External Interrupt Detection level setting register (ELVR1) LB15 LA15 INT15R INT14R INT13 INT12R DTP/external interrupt input detection circuit Interrupt request signal...
Page 332: Details Of Pins And Interrupt Numbers
CHAPTER 17 DTP/EXTERNAL INTERRUPTS DTP/external interrupt input detection circuit This circuit detects interrupt requests or data transfer requests generated from external peripheral devices. The interrupt request flag bit corresponding to the pin whose level or edge set by the detection level setting register (ELVR) is detected is set to "1"...
Page 333: Configuration Of Dtp/External Interrupt
17.3 Configuration of DTP/External Interrupt This section lists and details the pins, interrupt factors, and registers in the DTP/ external interrupt. Pins of DTP/External Interrupt The pins used by the DTP/external interrupt serve as general-purpose I/O ports. Table 17.3-1 lists the pin functions and the pin setting required for use in the DTP/external interrupt. Table 17.3-1 Pins of DTP/External Interrupt Pin Name P54/AN12/TOT3...
Page 334 CHAPTER 17 DTP/EXTERNAL INTERRUPTS List of Registers and Reset Values in DTP/External Interrupt Figure 17.3-1 List of Registers and Reset Values in DTP/External Interrupt ENIR1 Address: 0000CA EN15 EN14 EIRR1 Address: 0000CB ER15 ER14 ELVR1 Address: 0000CC LB11 ELVR1 Address: 0000CD LB15 LA15 EISSR Address: 0000CE...
Page 335: Dtp/External Interrupt Factor Register (Eirr1)
17.3.1 DTP/External Interrupt Factor Register (EIRR1) The DTP/external interrupt factor register holds DTP/external interrupt factors. When a valid signal is inputted to the DTP/external interrupt pin, the corresponding DTP/external interrupt request flag bit is set to "1". The EIRR1 register is corresponding to INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R, and INT15R.
Page 336 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.3-2 Function of DTP/External Interrupt Factor Register (EIRR1) Bit Name bit8 ER15 to ER8(EIRR1), DTP/External interrupt bit15 request flag bits Function These bits are set to "1" when the edges or level signals set by the detection condition select bits in the detection level setting register (ELVR1:LB, LA) are inputted to the DTP/external interrupt pins.
Page 337: Dtp/External Interrupt Enable Register (Enir1)
17.3.2 DTP/External Interrupt Enable Register (ENIR1) The DTP/external interrupt enable register (ENIR1) enables/disables the DTP/external interrupt request in the external peripheral devices. ENIR1 is corresponding to INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R and INT15R. DTP/External Interrupt Enable Register (ENIR1) Figure 17.3-3 DTP/External Interrupt Enable Register (ENIR1) Address EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8...
Page 338 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.3-4 Correspondence between DTP/External Interrupt Pins, DTP/External Interrupt Request Flag Bits, and DTP/External Interrupt Request Enable Bits DTP/external interrupt pin INT8 INT9R INT10 INT11 INT12R INT13 INT14R INT15R DTP/external interrupt DTP/external interrupt request flag bit ER10 ER11 ER12...
Page 339: Detection Level Setting Register (Elvr1)
17.3.3 Detection Level Setting Register (ELVR1) The detection level setting register sets the level or edge of input signals that cause the interrupt factors of the DTP/external interrupt pin. ELVR1 is corresponding to INT8, INT9R, INT10, INT11, INT12R, INT13, INT14R and INT15R.
Page 340 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.3-6 Correspondence between Detection Level Setting Register and Channels DTP/External Interrupt Pin INT8 INT9R INT10 INT11 INT12R INT13 INT14R INT15R Register Name Bit Name LB8, LA8 LB9, LA9 LB10, LA10 LB11, LA11 ELVR1 LB12, LA12 LB13, LA13 LB14, LA14 LB15, LA15...
Page 341: External Interrupt Factor Select Register (Eissr)
17.3.4 External Interrupt Factor Select Register (EISSR) The external interrupt factor select register (EISSR) can change the assignment of the external interrupt pin. This allows the external interrupt. Also, the function such as CAN wakeup is implemented. Selection of External Interrupt Factor The external interrupt pin of the upper 8-bit is assigned to INT13, INT11, INT10, and INT8 normally and shares the port 5 and pin.
Page 342 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Table 17.3-8 External Interrupt Factor Select (Upper 8-bit) EISSR Bit INT8R INT9R INT10R INT11R INT12R INT13R INT14R INT15R "0" (Initial Value) INT8: P54 (AN12/TOT3) INT10: P55 (AN13) INT11: P56 (AN14) INT13: P57 (AN15) "1" INT9R: P42 (RX1) INT12R: P80 (ADTG) INT14R: P82 (SIN0/TIN2) INT15R: P84 (SCK0)
Page 343: Explanation Of Operation Of Dtp/External Interrupt
17.4 Explanation of Operation of DTP/External Interrupt The DTP/external interrupt has an external interrupt function and a DTP function. The setting and operation of each function are explained. Setting of DTP/External Interrupt Using the DTP/external interrupt requires, the setting shown in Figure 17.4-1 . Figure 17.4-1 Setting of DTP/External Interrupt ICR interrupt control register At DTP (EI...
Page 344 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Setting procedure To use the DTP/external interrupt, set each register by using the following procedure: 1. Set the input port to the general-purpose I/O port, which is shared with the terminal to be used as external interrupt input. 2.
Page 345 DTP/External Interrupt Operation The control bits and the interrupt factors for the DTP/external interrupt are shown in Table 17.4-1 . Table 17.4-1 Control Bits and Interrupt Factors for DTP/External Interrupt Interrupt request flag bit Interrupt request enable bit Interrupt factor If the interrupt request signal from the DTP/external interrupt is output to the interrupt controller and the OS enable bit in the interrupt control register (ICR:ISE) is set to "0", the interrupt processing is executed.
Page 346 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Figure 17.4-2 Operation of DTP/External Interrupt DTP/external interrupt circuit ELVR1 EIRR1 ENIR1 Factor DTP/external interrupt request generating Interrupt controller reception judge CPU interrupt reception judge Interrupt processing microprogram starting ICR:ISE External interrupt starting Processing and interrupt flag clear Recovery from external interrupt Other...
Page 347: External Interrupt Function
17.4.1 External Interrupt Function The DTP/external interrupt has an external interrupt function for generating an interrupt request by detecting the signal (edge or level) in the DTP/external interrupt pin. External Interrupt Function • When the signal (edge or level) set in the detection level setting register is detected in the DTP/external interrupt pin, the interrupt request flag bit in the DTP/external interrupt factor register (EIRR1:ER) is set to "1".
Page 348: Dtp Function
CHAPTER 17 DTP/EXTERNAL INTERRUPTS 17.4.2 DTP Function The DTP/external interrupt has the DTP function that detects the signal of the external peripheral device from the DTP/external interrupt pin to start the EI DTP Function The DTP function detects the signal level set by the detection level setting register of the DTP/external interrupt function to start the EI •...
Page 349: Precautions When Using Dtp/External Interrupt
17.5 Precautions when Using DTP/External Interrupt This section explains the precautions when using the DTP/external interrupt. Precautions when Using DTP/External Interrupt Condition of external-connected peripheral device when DTP function is used • When using the DTP function, the peripheral device must automatically clear a data transfer request when data transfer is performed.
Page 350 CHAPTER 17 DTP/EXTERNAL INTERRUPTS Precautions on interrupts • When the DTP/external interrupt is used as the external interrupt function, no return from interrupt processing can be made with the DTP/external interrupt request flag bit set to "1" (EIRR1:ER) and the DTP/external interrupt request set to "enabled"...
Page 351: Program Example Of Dtp/External Interrupt Function
17.6 Program Example of DTP/External Interrupt Function This section gives a program example of the DTP/external interrupt function. Program Example of DTP/External Interrupt Function Processing specifications An external interrupt is generated by detecting the rising edge of the pulse input to the INT8 pin. Coding example ICR07 DDR5...
Page 352: Program Example Of Dtp Function
CHAPTER 17 DTP/EXTERNAL INTERRUPTS ÅE Processing by user ÅE RETI CODE ENDS ;---------Vector setting------------------------------------------ VECT CSEG VECT ENDS Program Example of DTP Function Processing specification • Channel 0 of the EI • RAM data is outputted to port 5 by performing DTP processing (EI Coding example ICR07 DDR6...
Page 353 ;---------Main program------------------------------------- CODE CSEG START: ;Stack pointer (SP) already initialized I:ADER5,#00000000B ;Set analog input of port5 to disable I:ADER6,#00000000B ;Set analog input of port6 to disable I:DDR6,#11111111B I:DDR5,#00000000B CCR,#0BFH I:ICR07,#08H ;Data bank register (DTB) = 00H BAPL,#00H BAPM,#06H BAPH,#00H ISCS,#12H IOAL,#00H IOAH,#00H DCTL,#0AH...
Page 354 CHAPTER 17 DTP/EXTERNAL INTERRUPTS VECT ENDS #26(1A WARI 00FFDCH ;Reset vector set START ;Set to single-chip mode START...
Page 355: Chapter 18 8-/10-Bit A/D Converter
CHAPTER 18 8-/10-BIT A/D CONVERTER This chapter explains the functions and operation of 8-/ 10-bit A/D converter. 18.1 Overview of 8-/10-bit A/D Converter 18.2 Block Diagram of 8-/10-bit A/D Converter 18.3 Configuration of 8-/10-bit A/D Converter 18.4 Interrupt of 8-/10-bit A/D Converter 18.5 Explanation of Operation of 8-/10-bit A/D Converter 18.6 Precautions when Using 8-/10-bit A/D Converter...
Page 356: Overview Of 8-/10-Bit A/D Converter
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.1 Overview of 8-/10-bit A/D Converter The 8-/10-bit A/D converter converts the analog input voltage to a 8- or 10-bit digital value by using the RC sequential-comparison converter system. • An input signal can be selected from the input signals of the analog input pins for 16 channels.
Page 357: Block Diagram Of 8-/10-Bit A/D Converter
18.2 Block Diagram of 8-/10-bit A/D Converter The 8-/10-bit A/D converter consists of following blocks. Block Diagram of 8-/10-bit A/D Converter Figure 18.2-1 Block Diagram of 8-/10-bit A/D Converter A/D control status BUSY INTE register (ADCS0/ ADCS1) ADTG Analog AN0 to AN7 channel AN15 to AN8 selector...
Page 358 CHAPTER 18 8-/10-BIT A/D CONVERTER Details of pins in block diagram Table 18.2-1 shows the actual pin names and interrupt request numbers of the 8-/10-bit A/D converter. Table 18.2-1 Pins and Interrupt Request Numbers in Block Diagram Pin Name/Interrupt Request Number in Block ADTG AN0 to AN7 AN8 to AN15...
Page 359 Analog channel selector This selector selects the pin to be used for A/D conversion from the 16-channel analog input pins by receiving a signal from the decoder. Sample & hold circuit This circuit holds the input voltage selected by the analog channel selector. By holding the input voltage immediately after A/D conversion is started, A/D conversion is performed without being affected by the fluctuation of the input voltage during A/D conversion.
Page 360: Configuration Of 8-/10-Bit A/D Converter
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3 Configuration of 8-/10-bit A/D Converter This section explains the pins, registers, and interrupt factors of the A/D converter. Pins of 8-/10-bit A/D Converter The pins of the 8-/10-bit A/D converter serve as general-purpose I/O ports. Table 18.3-1 shows the pin functions and the setting required for use of the 8-/10-bit A/D converter.
Page 361: Generation Of Interrupt From 8-/10-Bit A/D Converter
List of Registers and Reset Values of 8-/10-bit A/D Converter Figure 18.3-1 List of Register and Reset Value of 8-/10-bit A/D Converter A/D control status register (High) ADCS1 BUSY INT Address :000069 A/D control status register (Low) ADCS0 :000068 Address Data register (High) ADCR1 Address...
Page 362: A/D Control Status Register (High) (Adcs1)
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.1 A/D Control Status Register (High) (ADCS1) The A/D control status register (High) (ADCS1) provides the following settings: • Starting A/D conversion function by software • Selecting start trigger for A/D conversion • Storing A/D conversion results in A/D data register to enable or disable interrupt request •...
Page 363 Table 18.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS1) (1/2) Bit name bit15 BUSY: This bit forcibly terminates the 8-/10-bit A/D converter. When read, this A/D conversion-on bit indicates whether the 8-/10-bit A/D converter is operating or flag bit stopped.
Page 364 CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-2 Function of Each Bit of A/D Control Status Register (High) (ADCS1) (2/2) Bit name bit12 PAUS: Pause flag bit bit11, STS1, STS0: bit10 A/D conversion start trigger select bits bit9 STRT: A/D conversion software start bit bit8 Undefined bit...
Page 365: A/D Control Status Register (Low) (Adcs0)
18.3.2 A/D Control Status Register (Low) (ADCS0) The A/D control status register (Low) (ADCS0) provides the following settings: • Selecting A/D conversion mode • Selecting start channel and end channel of A/D conversion A/D Control Status Register (Low) (ADCS0) Figure 18.3-3 A/D Control Status Register (Low) (ADCS0) Address 000068 MD1 MD0 S10...
Page 366 CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-3 Function of Each Bit of A/D Control Status Register (Low) (ADCS0) Bit Name bit7 MD1, MD0: These bits set the A/D conversion mode. bit6 A/D conversion Single-shot conversion mode 1: mode select bits •...
Page 367: A/D Data Register (Adcr0/Adcr1)
18.3.3 A/D Data Register (ADCR0/ADCR1) The A/D data register (ADCR0/ADCR1) stores the digital value generated as the conversion result. The ADCR0 stores the lower 8-bit, and ADCR1 stores the most significant 2-bit of the conversion result. This register is rewritten each time the conversion complete and stores last conversion value normally.
Page 368: A/D Setting Register (Adsr0/Adsr1)
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.4 A/D Setting Register (ADSR0/ADSR1) A/D setting register (ADSR0/ADSR1) can set as following. • Setting of A/D conversion time (sampling time and comparing time) • Setting of sampling channel (starting channel and end channel) • Displaying the present sampling channels A/D Setting Register (ADSR0/ADSR1) Figure 18.3-5 A/D Setting Register (ADSR0/ADSR1) Address...
Page 369 Table 18.3-5 Function of A/D Setting Register (ADSR0/ADSR1) (1/2) Bit Name bit15 ST2, ST1, ST0: These bits set the sampling time of A/D conversion. Sampling time select • These bits set the time when the A/D conversion is started and bit13 bits •...
Page 370 CHAPTER 18 8-/10-BIT A/D CONVERTER Table 18.3-5 Function of A/D Setting Register (ADSR0/ADSR1) (2/2) Bit Name bit3 ANE3 to ANE0: A/D conversion end bit0 channel select bits Note: Do not set the A/D conversion mode set bits (MD1 and MD0) and A/D conversion end channel select bits (ANE3, ANE2, ANE1 and ANE0) through read-modify-write commands after the start channel is set in the A/D conversion start channel select bits (ANS3, ANS2, ANS1 and ANS0).
Page 371 The sampling time must be set according to drive impedance R following condition is not met, the conversion accuracy will not be guaranteed. ≤ 1.5kΩ : • R •- 4.5 V ≤ AV < 5.5 V: The sampling time must be set greater than 0.5 µs. •...
Page 372: Analog Input Enable Register (Ader5, Ader6)
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.3.5 Analog Input Enable Register (ADER5, ADER6) The analog input enable register enables or disables the analog input pins to be used in the 8-/10-bit A/D converter. Analog Input Enable Register (ADER5, ADER 6) Figure 18.3-6 Analog Input Enable Register (ADER5 to 6) Address ADER5 00000B ADE15...
Page 373 Notes: • When using as the analog input pin, write "1" to the bit of the analog input enable register (ADER5, ADER6) corresponding to the pin to be used and set to the analog input. • Setting the analog input pin to ADERx = "0" is disabled. Always set it to ADERx = "1". •...
Page 374: Interrupt Of 8-/10-Bit A/D Converter
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.4 Interrupt of 8-/10-bit A/D Converter When A/D conversion is terminated and its results are stored in the A/D data register (ADCR), the 8-/10-bit A/D converter generates an interrupt request. The EI can be used. Interrupt of A/D Converter When A/D conversion of the analog input voltage is terminated and its results are stored in the A/D data register (ADCR), the interrupt request flag bit in the A/D control status register (ADCS:INT) is set to "1".
Page 375: Explanation Of Operation Of 8-/10-Bit A/D Converter
18.5 Explanation of Operation of 8-/10-bit A/D Converter The 8-/10-bit A/D converter has the following A/D conversion modes. Set each mode according to the setting of the A/D conversion mode select bits in the A/D control status register (ADCS:MD1, MD0). •...
Page 376: Single-Shot Conversion Mode
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.1 Single-shot Conversion Mode In the single-shot conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. The A/D conversion stops at the termination of A/D conversion for the end channel. Setting of Single-shot Conversion Mode Operating the 8-/10-bit A/D converter in the single-shot conversion mode requires the setting shown in Figure 18.5-1 .
Page 377 Operation of Single-shot Conversion Mode • When the start trigger is inputted, A/D conversion starts from the channel set by the A/D conversion start channel select bits (ANS3 to ANS0) and is performed continuously up to the channel set by the A/ D conversion end channel select bits (ANE3 to ANE0).
Page 378: Continuous Conversion Mode
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.2 Continuous Conversion Mode In the continuous conversion mode, A/D conversion is performed sequentially from the start channel to the end channel. When A/D conversion for the end channel is terminated, it is continued after returning to the start channel. Setting of Continuous Conversion Mode Operating the 8-/10-bit A/D converter in the continuous conversion mode requires the setting shown in Figure 18.5-2 .
Page 379 Operation of Continuous Conversion Mode • When the start trigger is inputted, A/D conversion starts from the channel set by the A/D conversion start channel select bits (ANS3 to ANS0) and is performed continuously up to the channel set by the A/ D conversion end channel select bits (ANE3 to ANE0).
Page 380: Pause-Conversion Mode
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.3 Pause-conversion Mode In the pause-conversion mode, A/D conversion starts and pauses repeatedly for each channel. When the start trigger is inputted after the A/D conversion pauses at the termination of the A/D conversion for the end channel, A/D conversion is continued after returning to the start channel.
Page 381: Operation Of Pause-Conversion Mode
Operation of Pause-conversion Mode • When the start trigger is inputted, A/D conversion starts at the channel set by the A/D conversion start channel select bits (ANS3 to ANS0). The A/D conversion pauses at the termination of the A/D conversion for one channel. When the start trigger is inputted while A/D conversion pauses, A/D conversion for the next channel is performed.
Page 382: Conversion Using Ei 2 Os Function
CHAPTER 18 8-/10-BIT A/D CONVERTER 18.5.4 Conversion Using EI The 8-/10-bit A/D converter can transfer the A/D conversion result to memory by using the EI OS function. Conversion Using EI The use of the EI memory without the loss of converted data even if A/D conversion is performed continuously. The conversion flow when the EI Figure 18.5-4 Flow of Conversion when Using EI *: The specified count depends on the setting of the EI...
Page 383: A/D-Converted Data Protection Function
18.5.5 A/D-converted Data Protection Function A/D conversion with the output of an interrupt request enabled activates the A/D conversion data protection function. A/D-converted Data Protection Function in 8-/10-bit A/D Converter The 8-/10-bit A/D converter has only one A/D data register (ADCR) where A/D-converted data is stored. When the A/D conversion results are determined after the termination of A/D conversion, data in the A/D data register is rewritten.
Page 384 CHAPTER 18 8-/10-BIT A/D CONVERTER Figure 18.5-5 Processing Flow of A/D Conversion Data Protection Function when Using EI A/D continuous conversion First conversion terminates Data in A/D data register stored Second conversion terminates Data in A/D data register stored Entire conversion terminates Note: The operation flow of when the A/D converter is stopped is omitted.
Page 385: Precautions When Using 8-/10-Bit A/D Converter
18.6 Precautions when Using 8-/10-bit A/D Converter Precautions when using the 8-/10-bit A/D converter are given below: Precautions when Using 8-/10-bit A/D Converter Analog input pin • The analog input pins serve as general-purpose I/O ports of port 5 and port 6. When using the pin as an analog input pin, switch the pin to "analog input pin"...
Page 386 CHAPTER 18 8-/10-BIT A/D CONVERTER...
Page 387 LOW VOLTAGE DETECTION/ CHAPTER 19 CPU OPERATING DETECTION RESET This chapter explains the function and operating the low voltage detection/CPU operating detection reset. This function can use only the product with "T" suffix of MB90360 series. 19.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit 19.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit 19.3 Low Voltage/CPU Operating Detection Reset Circuit Register...
Page 388: Chapter 19 Low Voltage Detection/Cpu Operating Detection Reset
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.1 Overview of Low Voltage/CPU Operating Detection Reset Circuit The low voltage detection reset circuit watches the power-supply voltage and has the function to detect the power-supply voltages falling lower than the detection voltage values.
Page 389: Chapter 19 Low Voltage Detection/Cpu Operating Detection Reset
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET CPU Operating Detection Reset Circuit CPU operating detection reset circuit is a counter for preventing the program out of control. After power-on reset, it starts automatically. After it starts, it is necessary to keep clearing regularly within the fixed time. Internal reset is generated when not cleared during the fixed time by an program infinite loop, etc.
Page 390: Configuration Of Low Voltage/Cpu Operating Detection Reset Circuit
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.2 Configuration of Low Voltage/CPU Operating Detection Reset Circuit Low voltage/CPU operating detection reset circuit has following three blocks. • CPU operating detection circuit • Voltage comparison circuit • Low voltage/CPU operating detection reset control register (LVRC) Block Diagram of Low Voltage/CPU Operating Detection Reset Circuit Figure 19.2-1 Block Diagram of Low Voltage/CPU operating Detection Reset Circuit CPU operating detection circuit...
Page 391 CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET CPU operating detection circuit It is a counter for preventing the program out of control. After it starts, it is necessary to keep clearing regularly within the fixed time. Voltage comparison circuit When the detection voltage is compared with the power-supply voltage, the output is set to "H"...
Page 392: Low Voltage/Cpu Operating Detection Reset Circuit Register
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.3 Low Voltage/CPU Operating Detection Reset Circuit Register This register clears the low voltage/CPU operating detection reset flag and the counter of CPU operating detection circuit. Low Voltage/CPU Operating Detection Reset Control Register (LVRC) Figure 19.3-1 Low Voltage/CPU operating Detection Reset Control Register (LVRC) Address...
Page 393: Chapter 19 Low Voltage Detection/Cpu Operating Detection Reset
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET Table 19.3-1 Functional Description of Low Voltage/CPU operating Detection Reset Control Register Bit name bit7/ Reserved: bit6 Reserved bits bit5/ Reserved: bit4 Reserved bits bit3 CPU operating detection clear bit bit2 LVRF: Low voltage detection flag bit bit1...
Page 394: Operating Of Low Voltage/Cpu Operating Detection Reset Circuit
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.4 Operating of Low Voltage/CPU Operating Detection Reset Circuit The circuit watches the power-supply voltage. When the power supply voltage is lower than the set value, internal reset is generated. In CPU operating detecting function, internal reset is generated without the counter clear at constant intervals.
Page 395: Notes On Using Low Voltage/Cpu Operating Detection Reset Circuit
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.5 Notes on Using Low Voltage/CPU Operating Detection Reset Circuit This section explains the note on using the low voltage/CPU operating detection reset circuit. Notes on Using Low Voltage Detection Reset Circuit Disabled operating stop from program The low voltage detection reset circuit operates continuously after the power supply is turned on and the operating stabilization wait time passes.
Page 396: Sample Program For Low Voltage/Cpu Operating Detection Reset Circuit
CHAPTER 19 LOW VOLTAGE DETECTION/CPU OPERATING DETECTION RESET 19.6 Sample Program for Low Voltage/CPU Operating Detection Reset Circuit This section shows the sample program for low voltage/CPU operating detection reset circuit. Sample Program for Low Voltage/CPU Operating Detection Reset Circuit Processing specification The counter of CPU operating detecting function is cleared.
Page 397: Chapter 20 Lin-Uart
CHAPTER 20 LIN-UART This chapter explains the functions and operation of LIN-UART. 20.1 Overview of LIN-UART 20.2 Configuration of LIN-UART 20.3 LIN-UART Pins 20.4 LIN-UART Registers 20.5 LIN-UART Interrupts 20.6 LIN-UART Baud Rates 20.7 Operation of LIN-UART 20.8 Notes on Using LIN-UART...
Page 398: Overview Of Lin-Uart
CHAPTER 20 LIN-UART 20.1 Overview of LIN-UART The LIN-UART with LIN (Local Interconnect Network) - Function is a general-purpose serial data communication interface for performing synchronous or asynchronous communication (start-stop synchronization) with external devices. LIN-UART provides bidirectional communication function (normal mode), master-slave communication function (multiprocessor mode in master/slave systems), and special features for LIN- bus systems.
Page 399 Table 20.1-1 LIN-UART Functions (2/2) LIN bus option Synchronous serial clock Clock delay option • Master device operation • Slave device operation • LIN Synch break detection • LIN Synch break generation • Detection of start/stop edges in LIN Synch field connected to input capture 0 and 1 Synchronous serial clock can be continuously outputted to SCK pin for synchronous communication with start/stop bits.
Page 400 CHAPTER 20 LIN-UART LIN-UART operation modes The LIN-UART operates in four different modes, which are determined by the MD0- and the MD1-bit of the serial mode register (SMR). Mode 0 and 2 are used for bidirectional serial communication, mode 1 for master/slave communication and mode 3 for LIN master/slave communication.
Page 401 LIN-UART interrupt and EI Table 20.1-4 LIN-UART Interrupt and EI Channel Interrupt number LIN-UART0 reception #35(23 LIN-UART0 #36(24 transmission LIN-UART1 reception #37(25 LIN-UART1 #38(26 transmission *1: EI OS service is usable if the other interrupt (s) which shares the ICR12 to ICRB and same interrupt vector is (are) not enabled.
Page 402: Configuration Of Lin-Uart
CHAPTER 20 LIN-UART 20.2 Configuration of LIN-UART This section provides a short overview on the building blocks of LIN-UART. LIN-UART consists of the following blocks: • Reload Counter • Reception Control Circuit • Reception Shift Register • Reception Data Register (RDR) •...
Page 403: Block Diagram Of Lin-Uart
Block Diagram of LIN-UART Figure 20.2-1 Block Diagram of LIN-UART Reload counter SCKn SINn Restart reception reload counter Over- sampling unit Internal signal LIN break/ to capture SynchField detection circuit To EI Error detection SSRn RDRF register REST TDRE UPCL USCKE USOE n = 0, 1...
Page 404 CHAPTER 20 LIN-UART Explanation of the different blocks Reload Counter The reload counter is a 15-bit reload counter that functions as the dedicated baud rate generator. It can select external clock or internal clock for the transmitting and receiving clocks. The reload counter has a 15-bit register for the reload value.
Page 405 Oversampling Circuit The oversampling circuit oversamples the incoming data at the SINn pin for five times in the asynchronous mode. The received value is determined by majority decision of sampling time. It is switched off in synchronous operation mode. Interrupt Generation Circuit The interrupt generation circuit administers all cases of generating a reception or transmission interrupt.
Page 406 CHAPTER 20 LIN-UART Serial Control Register (SCR) This register performs the following operations: • Specifying whether to provide parity bits • Selecting parity bits • Specifying a stop bit length • Specifying a data length • Selecting a frame data format in mode 1 •...
Page 407: Lin-Uart Pins
20.3 LIN-UART Pins This section describes the LIN-UART pins and provides a pin block diagram. LIN-UART Pins The LIN-UART pins also serve as general ports. Table 20.3-1 lists the pin functions, I/O formats, and settings required to use LIN-UART. Table 20.3-1 LIN-UART Pin Pin Name Pin Function P82/SIN0...
Page 408: Lin-Uart Registers
CHAPTER 20 LIN-UART 20.4 LIN-UART Registers The following figure shows the LIN-UART registers. LIN-UART Registers • LIN-UART0 Address: bit 15 000021 000020 SCR0 (serial control register) 000023 000022 SSR0 (serial status register) 000025 000024 ESCR0 (Extended status control register) 000027 000026 BGR01 (Baud rate generator register) •...
Page 409: Serial Control Register (Scr)
20.4.1 Serial Control Register (SCR) This register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable transmission and reception. Serial Control Register (SCR) Figure 20.4-2 Configuration of the Serial Control Register (SCR) Address bit14 bit13 bit12 bit11...
Page 410 CHAPTER 20 LIN-UART Table 20.4-1 Function of Each Bit in Serial Control Register (SCR) Bit Name bit15 PEN: This bit selects whether to add a parity bit during transmission or detect it during reception. Parity enable bit Note: Parity bit is only provided in mode 0 and in mode 2 if SSM of the ECCR is selected to 1. This bit is fixed to 0 (no parity) in mode 3 (LIN).
Page 411: Lin-Uart Serial Mode Register (Smr)
20.4.2 LIN-UART Serial Mode Register (SMR) This register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin. LIN-UART Serial Mode Register (SMR) Figure 20.4-3 Configuration of the Serial Mode Register (SMR) Address bit15 SMR0:000020...
Page 412 CHAPTER 20 LIN-UART Table 20.4-2 Function of Each Bit in Serial Mode Register (SMR) Bit name bit7, MD1, MD0: bit6 Operation mode setting bits bit5 OTO: One-to-one external clock input enable bit bit4 EXT: External serial clock source selection bit bit3 REST: Restart of dedicated reload...
Page 413: Serial Status Register (Ssr)
20.4.3 Serial Status Register (SSR) This register checks the transmission and reception status and error status, and enables and disables the transmission and reception interrupts. Serial Status Register (SSR) Figure 20.4-4 Configuration of the Serial Status Register (SSR) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 SSR0:000023 PE ORE FRE RDRF TDRE BDS RIE TIE SSR1:00002B...
Page 414 CHAPTER 20 LIN-UART Table 20.4-3 Function of Each Bit in Serial Status Register (SSR) Bit name • bit15 This bit is set to 1 when a parity error occurs during reception at PE=1 and is cleared Parity error flag bit when 1 is written to the CRE bit of the LIN-UART serial control register (SCR).
Page 415: Reception And Transmission Data Register (Rdr/Tdr)
20.4.4 Reception and Transmission Data Register (RDR/TDR) Both RDR and TDR registers are located at the same address. At reading, it functions as the reception data register. At writing, it functions as the transmission data register. Reception Data Register (RDR) Figure 20.4-5 Transmission and Reception Data Registers (RDR/TDR) Address RDR0/TDR0: 000022...
Page 416: Transmission Data Register (Tdr)
CHAPTER 20 LIN-UART Transmission Data Register (TDR) TDR is the data buffer register for serial data transmission. When data to be transmitted is written to the transmission data register (TDR) in transmission enable state (SCR: TXE=1), it is transferred to the transmission shift register, then converted to serial data, and transmitted from the serial data output pin (SOTn pin).
Page 417: Extended Status/Control Register (Escr)
20.4.5 Extended Status/Control Register (ESCR) This register provides several LIN functions, direct access to the SINn and SOTn pins and setting of continuous clock output and sampling clock edge in LIN-UART synchronous clock mode. Extended Status/control Register (ESCR) Figure 20.4-6 shows the Configuration of the extended status/control register (ESCR), and Table 20.4-4 shows the function of each bit.
Page 418 CHAPTER 20 LIN-UART Table 20.4-4 Function in Each Bit of the Extended Status/control Register (ESCR) Bit name bit15 LBIE: LIN synch break detection interrupt enable bit bit14 LBD: LIN synch break detected flag bit bit13, LBL1/0: bit12 LIN synch break length selection bits bit11 SOPE:...
Page 419: Extended Communication Control Register (Eccr)
20.4.6 Extended Communication Control Register (ECCR) The extended communication control register (ECCR) provides bus idle detection, synchronous clock settings, and the LIN synch break generation. Extended Communication Control Register (ECCR) Figure 20.4-7 shows the configuration of the extended communication control register (ECCR), and Table 20.4-6 shows the function of each bit.
Page 420 CHAPTER 20 LIN-UART Table 20.4-6 Function of Each Bit in the Extended Communication Control Register (ECCR) Bit name bit7 Unused bit bit6 LBR: Lin Synch break Generating bit bit5 Master/Slave mode selection bit in mode 2 bit4 SCDE: Serial clock delay enable bit in mode 2 bit3 SSM: Start/Stop bit mode enable bit in mode...
Page 421: Baud Rate Generator Register 0 And 1 (Bgr0/1)
20.4.7 Baud Rate Generator Register 0 and 1 (BGR0/1) The baud rate generator registers set the division ratio for the serial clock. Also, the actual count of the transmission reload counter can be read. Baud Rate Generator Register (BGRn0/n1) Figure 20.4-8 shows the configuration of the baud rate generator register (BGRn0/n1). Figure 20.4-8 Configuration of Baud Rate Generator Register (BGRn0/n1) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9...
Page 422: Lin-Uart Interrupts
CHAPTER 20 LIN-UART 20.5 LIN-UART Interrupts LIN-UART uses both reception and transmission interrupts. An interrupt request can be generated for either of the following causes: • Receive data is set in the reception data register (RDR), or a reception error occurs. •...
Page 423 Reception Interrupt If one of the following events occurs in reception mode, the corresponding flag bit of the serial status register (SSR) is set to "1": • Data reception is completed, i. e. the received data was transferred from the serial input shift register to the reception data register (RDR) and data can be read: RDRF •...
Page 424 CHAPTER 20 LIN-UART LIN Synchronization Field Edge Detection Interrupts This paragraph is only relevant, if LIN-UART operates in mode 3 as a LIN slave. After LIN synch break detection, the internal signal is set to "1" at first falling edge of the LIN synch field and to "0" after fifth falling edge.
Page 425: Reception Interrupt Generation And Flag Set Timing
20.5.1 Reception Interrupt Generation and Flag Set Timing The following are the reception interrupt causes: completion of reception (SSR: RDRF) and occurrence of a reception error (SSR: PE, ORE, or FRE). Reception Interrupt Generation and Flag Set Timing The received data is stored in the RDR register if the first stop bit is detected in mode 0, 1, 2 (if SSM = 1), 3, or the last data bit was read in mode 2 (if SSM = 0).
Page 426 CHAPTER 20 LIN-UART Reception data RDRF Figure 20.5-2 ORE Flag Set Timing:...
Page 427: Transmission Interrupt Generation And Flag Set Timing
20.5.2 Transmission Interrupt Generation and Flag Set Timing A transmission interrupt is generated when the transmission data is transferred from transmission data register (TDR) to transmission shift register and transmission is started. Transmission Interrupt Generation and Flag Set Timing When the data written to the TDR register is transferred to the transmission shift register and the transmission is started, next data to be written is enabled (SSR: TDRE=1).
Page 428 CHAPTER 20 LIN-UART Transmission interrupt request generation timing If the TDRE flag is set to "1" when a transmission interrupt is enabled (SSR: TIE=1), transmission interrupt is generated. Note: A transmission interrupt is generated immediately after the transmission interrupt is enabled (SSR: TIE=1) because the TDRE bit is set to 1 as its initial value.
Page 429: Lin-Uart Baud Rates
20.6 LIN-UART Baud Rates One of the following can be selected for the LIN-UART transmission/reception clock source: • Dedicated baud rate generator (Reload Counter) • Input external clock to baud rate generator (Reload Counter) • External clock (directly use SCKn pin input clock) LIN-UART Baud Rate Selection The baud rate selection circuit is designed as shown below.
Page 430 CHAPTER 20 LIN-UART Figure 20.6-1 Baud Rate Selection Circuit of LIN-UART SCKn (external clock input) REST n=0,1 Reload Value: v Rxc = 0? Reception Reload 15-bit Reload Counter Rxc = v/2? Reload Value: v Txc = 0? Transmission 15-bit Reload Counter Reload Count Value: T Txc = v/2?
Page 431: Setting The Baud Rate
20.6.1 Setting the Baud Rate This section describes how the baud rates are set and the resulting serial clock frequency is calculated. Calculating the Baud Rate The both 15-bit reload counters are programmed by the baud rate generator registers 1, 0 (BGR1/BGR0). The following calculation formula should be used to set the desired baud rate: Reload Value: v = [Φ...
Page 432 CHAPTER 20 LIN-UART Suggested division ratios for different machine speeds and baud rates The following settings are suggested for different MCU clock speeds and baud rates: Table 20.6-1 Suggested Baud Rates and Reload Values at Different Machine Speeds. 8 MHz Baud rate value...
Page 433 Using external clock If the EXT bit of the SMR is set to 1, an external clock is selected, which has to be connected to the SCKn pin. The external clock is used in the same way as the internal clock to the baud rate generator. If One-to-one External Clock Input Mode (SMR: OTO=1) is selected the SCKn signal is directly connected to the LIN-UART serial clock inputs.
Page 434: Restarting The Reload Counter
CHAPTER 20 LIN-UART 20.6.2 Restarting the Reload Counter The reload counter is a 15-bit reload counter that functions as dedicated baud rate generator. The transmission/reception clock is generated by the external or internal clock. Also, the count value of the transmission reload counter can be read by the baud rate generator register (BGR1, BGR0).
Page 435 Note: If LIN-UART is reset by setting SMR:UPCL to "1", the Reload Counters will restart too. • Automatic restart (reception reload counter only) In asynchronous LIN-UART mode, if a falling edge of a start bit is detected, the Reception Reload Counter is restarted.
Page 436: Operation Of Lin-Uart
CHAPTER 20 LIN-UART 20.7 Operation of LIN-UART LIN-UART operates in operation mode 0 for normal bidirectional serial communication, in mode 2 and 3 in bidirectional communication as master or slave, and in mode 1 as master or slave in multiprocessor communication. Operation of LIN-UART Operation modes There are four LIN-UART operation modes: modes 0 to 3.
Page 437: Inter-Cpu Connection Method
Inter-CPU Connection Method External Clock One-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can be selected. For either connection method, the data length, whether to enable parity, and the synchronization method must be common to all CPUs. Select an operation mode as follows: •...
Page 438: Operation In Asynchronous Mode (Op. Modes 0 And 1)
CHAPTER 20 LIN-UART 20.7.1 Operation in Asynchronous Mode (Op. Modes 0 and 1) When LIN-UART is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. Operation in Asynchronous Mode Transfer data format Generally each data transfer in the asynchronous mode operation begins with the start bit (low-level) and ends with at least one stop bit (high-level).
Page 439 Figure 20.7-1 Transfer Data Format (operation Modes 0 and 1) [Operation mode 0] ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 SP ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0 D1 D2 D3 D4 D5 D6 D7 ST D0...
Page 440 CHAPTER 20 LIN-UART Transmission operation If the Transmission Data Register Empty (TDRE) flag bit of the Serial Status Register (SSR) is "1", transmission data is allowed to be written to the Transmission Data Register (TDR). When data is written, the TDRE flag goes "0". If the transmission operation is enabled by the TXE-Bit ("1") of the Serial Control Register (SCR), the data is written next to the transmission shift register and the transmission starts at the next clock cycle of the serial clock, beginning with the start bit.
Page 441 Stop bit 1- or 2-stop bit can be selected at the transmission. When 2-stop bit is selected, both stop bits is detected at the reception. When first stop bit is detected, the RDRF bit of SSR is "1". Then, when the start bit is not detected, the RBI bit of ECCR is set to "1", indicating no reception operation.
Page 442: Operation In Synchronous Mode (Operation Mode 2)
CHAPTER 20 LIN-UART 20.7.2 Operation in Synchronous Mode (Operation Mode 2) The clock synchronous transfer method is used for LIN-UART operation mode 2 (normal mode). Operation in Synchronous Mode (Operation mode 2) Transfer data format In the synchronous mode, 8-bit data is transferred without start or stop bits if the SSM bit of the Extended Communication Control Register (ECCR) is 0.
Page 443 Clock supply: In operation mode 2, the number of clock cycles for the clock signal must be the same as the number of bits for the transmission and reception. If the start/stop bits are enabled, it must be matched the additional start/ stop bits.
Page 444 CHAPTER 20 LIN-UART Communication: For initialization of the synchronous mode, following settings have to be done: Baud rate generator registers (BGR0/BGR1): Set the desired reload value for the dedicated baud rate reload counter. Serial mode register (SMR): MD1, MD0: "10 SCKE: "1"...
Page 445: Operation With Lin Function (Operation Mode 3)
20.7.3 Operation with LIN Function (Operation Mode 3) LIN-UART can be used either as LIN-Master or LIN-Slave. For this LIN function a special mode is provided. Setting the LIN-UART to mode 3 configures the data format to 8N1- LSB-first format. Operation in Asynchronous LIN Mode (Operation mode 3) LIN-UART as LIN master In LIN master mode, the master determines the baud rate of the whole bus, therefore slaves devices have to...
Page 446 CHAPTER 20 LIN-UART where a is the value of the ICU data register after the first interrupt where b is the value of the ICU data register after the second interrupt Note: As shown in the LIN slave mode, when the BGR value newly calculated by synch field generates ±15% or more baud rate error, do not set the baud rate.
Page 447 Figure 20.7-8 LIN-UART Behavior as Slave in LIN Mode Serial clock Serial input (LIN bus) ICU input Synch break (at 14-bit setting) signal (LSYN) LIN bus timing Figure 20.7-9 LIN Bus Timing and LIN-UART Signals Old serial clock (SIN) (IRQ0) LBIE ICU input (LSYN)
Page 448: Direct Access To Serial Pins
CHAPTER 20 LIN-UART 20.7.4 Direct Access to Serial Pins LIN-UART allows the user to directly access to the transmission pin (SOTn) or the reception pin (SINn). LIN-UART Direct Pin Access The LIN-UART provides the ability for the software to access directly to serial input or output pin. The software can always monitor the incoming serial input pin (SINn) by reading the SIOP bit of the ESCR.
Page 449: Bidirectional Communication Function (Normal Mode)
20.7.5 Bidirectional Communication Function (Normal Mode) In operation mode 0 or 2, normal serial bidirectional communication is available. Select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. Bidirectional Communication Function The settings shown in Figure 20.7-10 are required to operate LIN-UART in normal mode (operation mode 0 or 2).
Page 450 CHAPTER 20 LIN-UART Communication procedure Communication starts at arbitrary timing from the transmission side when the transmission data is provided. When the transmission data is received at the reception side, ANS (per one byte in example) is returned periodically. Figure 20.7-12 shows an example of the bi-directional communication flowchart. Figure 20.7-12 Example of Master-slave Communication Flowchart (Transmission side) Start...
Page 451: Master-Slave Communication Function (Multiprocessor Mode)
20.7.6 Master-Slave Communication Function (Multiprocessor Mode) LIN-UART communication with multiple CPUs connected in master-slave mode is available for both master or slave systems in the operation mode 1. Master-slave Communication Function The settings shown in Figure 20.7-13 are required to operate LIN-UART in multiprocessor mode (operation mode 1).
Page 452 CHAPTER 20 LIN-UART Function selection Select the operation mode and data transfer mode for master-slave communication as shown in Table 20.7- Table 20.7-3 Selection of the Master-slave Communication Function Operation mode Master Slave Address Mode 1 Mode 1 transmission (transmit/ (transmit/ receive AD- receive AD-...
Page 453 Figure 20.7-15 Master-slave Communication Flowchart (Master CPU) Start Set operation mode 1 Set SINn pin as the serial data input pin. Set SOTn pin as the serial data output pin. Set 7 or 8 data bits. Set 1 or 2 stop bits. Set "1"...
Page 454: Lin Communication Function
CHAPTER 20 LIN-UART 20.7.7 LIN Communication Function LIN-UART communication with LIN devices is available for both LIN master or LIN slave systems. LIN-master-slave Communication Function The settings shown in the figure below are required to operate LIN-UART in LIN communication mode (operation mode 3).
Page 455: Sample Flowcharts For Lin-Uart In Lin Communication (Operation Mode 3)
20.7.8 Sample Flowcharts for LIN-UART in LIN communication (Operation Mode 3) This section contains sample flowcharts for LIN-UART in LIN communication. LIN-UART as LIN Master Device Figure 20.7-18 LIN-UART LIN Master Flowchart Start Initial setting : Set operation mode 3 Serial data output enabled, Baud rate setting, Synch break length setting TXE = 1, TIE = 0, RXE = 1, RIE = 1...
Page 456 CHAPTER 20 LIN-UART LIN-UART as LIN slave device Figure 20.7-19 LIN-UART LIN Slave Flowchart Start Initial setting : Set operation mode 3 Serial data output enabled TXE = 1, TIE = 0, RXE = 0, RIE = 1 Connection with LIN-UART and ICU Reception prohibited ICU interrupt enabled Synch break interrupt...
Page 457: Notes On Using Lin-Uart
20.8 Notes on Using LIN-UART Notes on using LIN-UART are given below. Notes on Using LIN-UART Enabling operations In LIN-UART, the serial control register (SCR) has TXE (transmission) and RXE (reception) operation enable bits. Both, transmission and reception operations, must be enabled before the communication starts because they have been disabled as the default value (initial value).
Page 458 CHAPTER 20 LIN-UART predefined value. Bus idle function The bus idle function cannot be used in synchronous mode 2. AD bit (serial control register (SCR): address/data type select bit) Special care has to be taken when using the AD bit (Address-Data-Bit for multiprocessor mode 1) of the Serial Control Register.
Page 459: Chapter 21 Can Controller
CHAPTER 21 CAN CONTROLLER This chapter explains the functions and operations of the CAN controller. 21.1 Features of CAN Controller 21.2 Block Diagram of CAN Controller 21.3 List of Overall Control Registers 21.4 Classifying CAN Controller Registers 21.5 Transmission of CAN Controller 21.6 Reception of CAN Controller 21.7 Reception Flowchart of CAN Controller 21.8 How to Use CAN Controller...
Page 460: Features Of Can Controller
CHAPTER 21 CAN CONTROLLER 21.1 Features of CAN Controller The CAN (Controller Area Network) is the standard protocol for serial communication between automobile controllers and is widely used in industrial applications. Features of CAN Controller • Conforms to CAN Specification Version 2.0 Part A and B Supports transmission/reception in standard frame and extended frame formats •...
Page 461: Block Diagram Of Can Controller
21.2 Block Diagram of CAN Controller Figure 21.2-1 shows a block diagram of the CAN controller. Block Diagram of CAN Controller Figure 21.2-1 Block Diagram of CAN Controller MC-16LX bus Prescaler Clock 1 to 64 frequency division HALT Node status change interrupt generation NS1, 0 RTEC...
Page 462: List Of Overall Control Registers
CHAPTER 21 CAN CONTROLLER 21.3 List of Overall Control Registers Following Table lists the register. List of overall Control Registers Table 21.3-1 List of overall Control Register (1 / 2) Address Register CAN1 000080 Message buffer valid register 000081 000082 Transmit request register 000083 000084...
Page 463 Table 21.3-1 List of overall Control Register (2 / 2) Address Register CAN1 007D0C Remote frame receive waiting register 007D0D 007D0E Transmit interrupt enable register 007D0F 007D10 007D11 Acceptance mask select register 007D12 007D13 007D14 007D15 Acceptance mask register 0 007D16 007D17 007D18...
Page 464: List Of Message Buffers (Id Registers)
CHAPTER 21 CAN CONTROLLER List of Message Buffers (ID registers) Table 21.3-2 List of Message Buffers (ID registers) (1 / 2) Address Register CAN1 007C00 General-purpose RAM 007C1F 007C20 007C21 ID register 0 007C22 007C23 007C24 007C25 ID register 1 007C26 007C27 007C28...
Page 465 Table 21.3-2 List of Message Buffers (ID registers) (2 / 2) Address Register CAN1 007C3C 007C3D ID register 7 007C3E 007C3F 007C40 007C41 ID register 8 007C42 007C43 007C44 007C45 ID register 9 007C46 007C47 007C48 007C49 ID register 10 007C4A 007C4B 007C4C...
Page 466 CHAPTER 21 CAN CONTROLLER List of Message Buffers (DLC registers and data registers) Table 21.3-3 List of Message Buffer (DLC register and data register) Address Register CAN1 007C60 DLC register 0 007C61 007C62 DLC register 1 007C63 007C64 DLC register 2 007C65 007C66 DLC register 3...
Page 467 List of Message Buffer (data register) Table 21.3-4 List of Message Buffer (data register) Address Register CAN1 007C80 Data register 0 007C87 (8 bytes) 007C88 Data register 1 007C8F (8 bytes) 007C90 Data register 2 007C97 (8 bytes) 007C98 Data register 3 007C9F (8 bytes) 007CA0...
Page 468: Classifying Can Controller Registers
CHAPTER 21 CAN CONTROLLER 21.4 Classifying CAN Controller Registers There are 3 types of CAN controller registers; • Overall control registers • Message buffer control registers • Message buffers Overall Control Registers The overall control registers are the following 4 registers; •...
Page 469: Configuration Of Control Status Register (Csr)
21.4.1 Configuration of Control Status Register (CSR) This register indicates bus operation, node status, transmit output enable and transmit/ receive status. The lower 8-bit with the control status register (CSR) is prohibited from executing any bit manipulation instructions (Read-Modify-Write instructions). Only in the case of HALT bits unchanged (initialization of the macro instructions etc.), there is no problem even if any bit manipulation instructions is used.
Page 470: Function Of Control Status Register (Csr)
CHAPTER 21 CAN CONTROLLER 21.4.2 Function of Control Status Register (CSR) The operating status of the register’s each bit is confirmed by following; • Setting "0" or "1" • Function control by writing • Read Control Status Register (CSR-lower) Table 21.4-1 Function of Each Bit of the Control Status Register (CSR:L) Bit Name bit7 TOE:...
Page 471 Control status register (CSR-upper) Table 21.4-2 Function of Each Bit of the Control Status Register (CSR:H) Bit Name bit15 This bit indicates whether a message is being transmitted. Transmit status At read: 0: Message not being transmitted 1: Message being transmitted This bit is set 0 even while error and overload frames are transmitted.
Page 472: Correspondence Between Node Status Bit And Node Status
CHAPTER 21 CAN CONTROLLER 21.4.3 Correspondence between Node Status Bit and Node Status Node status bit shows the node status by two bits (NS1 and NS0). Correspondence between Node Status Bit and Node Status Table 21.4-3 Correspondence between NS1 and NS0 and Node Status Note: Warning (error active) is included in the error active in CAN Specification 2.0B for the node status, however, indicates that the transmit error counter or receive error counter has exceeded 96.
Page 473: Notes On Using Bus Operation Stop Bit (Halt = 1)
21.4.4 Notes on Using Bus Operation Stop Bit (HALT = 1) The bus operation stop bit is set by writing to the bit, hardware reset and the node status. The stop operation of the bus operation is different according to the state of the message buffer.
Page 474: Last Event Indicator Register (Leir)
CHAPTER 21 CAN CONTROLLER 21.4.5 Last Event Indicator Register (LEIR) This register indicates the last event. The NTE, TCE, and RCE bits are exclusive. When the corresponding bit of the last event is set to 1, other bits are set to 0. Last Event Indicator Register (LEIR) Figure 21.4-4 Configuration of the Last Event Indicator Register (LEIR) Address:...
Page 475 Last Event Indicator Register (LEIR) Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (LEIR) (1 / 2) Bit Name bit7 NTE: Node status transition event bit bit6 TCE: Transmit completion event bit bit5 RCE: Receive completion event bit bit4 Undefined bit...
Page 476 CHAPTER 21 CAN CONTROLLER Table 21.4-4 Function of Each Bit of the Last Event Indicator Register (LEIR) (2 / 2) Bit Name bit3 MBP3 to MBP0: Message buffer bit0 pointer bits When TCE bit or RCE bit is "1", these bits show the message buffer number (x) to generating of corresponding the last event.
Page 477: Receive And Transmit Error Counters (Rtec)
21.4.6 Receive and Transmit Error Counters (RTEC) The receive and transmit error counters indicate the counts for transmission errors and reception errors defined in the CAN specifications. These registers can only be read. Register Configuration Figure 21.4-5 Configuration of the Receive and Transmit Error Counters Address bit15 CAN1:...
Page 478: Bit Timing Register (Btr)
CHAPTER 21 CAN CONTROLLER 21.4.7 Bit Timing Register (BTR) Bit timing register (BTR) sets the prescaler and bit timing setting. Register Configuration Figure 21.4-6 Configuration of the Bit Timing Register (BTR) Address bit15 − CAN1: 007D07 − Address bit7 CAN1: 007D06 RSJ1 R/W :...
Page 479: Prescaler Setting By Bit Timing Register (Btr)
21.4.8 Prescaler Setting by Bit Timing Register (BTR) The setting of bit timing register (BTR) corresponds to the bit time of prescaler in the CAN specification and the CAN controller segment. Prescaler Settings The bit time segments defined in the CAN specification, and the CAN controller are shown in Figure 21.4-7 and Figure 21.4-8 respectively.
Page 480 CHAPTER 21 CAN CONTROLLER The relationship between PSC = PSC5 to PSC0, TSI = TS1.3 to TS1.0, TS2 = TS2.2 to TS2.0, and RSJ = RSJ1, RSJ0 For correct operation, the following conditions should be met. In order to meet the bit timing requirements defined in the CAN specification, additions have to be met, e.g.
Page 481: Message Buffer Valid Register (Bvalr)
21.4.9 Message Buffer Valid Register (BVALR) Message buffer valid register (BVALR) stores the validity of the message buffers or displays their state. Register Configuration Figure 21.4-9 Configuration of the Message Buffer Valid Register (BVALR) Address bit15 CAN1: 000081 BVAL15 Address bit7 CAN1: 000080...
Page 482: Ide Register (Ider)
CHAPTER 21 CAN CONTROLLER 21.4.10 IDE Register (IDER) This register stores the frame format used by the message buffers (x) during transmission/reception. Register Configuration Figure 21.4-10 Configuration of the IDE Register (IDER) Address bit15 CAN1: 007D09 IDE15 Address bit7 CAN1: 007D08 IDE7 R/W : Read/Write...
Page 483: Transmission Request Register (Treqr)
21.4.11 Transmission Request Register (TREQR) Transmission request register (TREQR) stores transmission requests to the message buffers (x) or displays their state. Register Configuration Figure 21.4-11 Configuration of the Transmission Request Register (TREQR) Address bit15 CAN1: 000083 TREQ15 Address bit7 CAN1: 000082 TREQ7 R/W : Read/Write...
Page 484: Transmission Rtr Register (Trtrr)
CHAPTER 21 CAN CONTROLLER 21.4.12 Transmission RTR Register (TRTRR) This register stores the RTR (Remote Transmission Request) bits for the message buffers (x). Register Configuration Figure 21.4-12 Configuration of the Transmission RTR Register (TRTRR) Address bit15 CAN1: 007D0B TRTR15 Address bit7 CAN1: 007D0A...
Page 485: Remote Frame Receiving Wait Register (Rfwtr)
21.4.13 Remote Frame Receiving Wait Register (RFWTR) Remote frame receiving wait register (RFWTR) sets the conditions for starting transmission when a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmitting RTR register (TRTRR) is 0).
Page 486: Transmission Cancel Register (Tcanr)
CHAPTER 21 CAN CONTROLLER 21.4.14 Transmission Cancel Register (TCANR) This register cancels a pending request for transmission to the message buffer (x). Register Configuration Figure 21.4-14 Configuration of the Transmission Cancel Register (TCANR) Address bit15 CAN1: 000085 TCAN15 Address bit7 CAN1: 000084 TCAN7...
Page 487: Transmission Complete Register (Tcr)
21.4.15 Transmission Complete Register (TCR) At completion of transmission by the message buffer (x), the corresponding TCx becomes 1. If TIEx of the transmission complete interrupt enable register (TIER) is 1, an interrupt occurs. Register Configuration Figure 21.4-15 Configuration of the Transmission Complete Register (TCR) Address bit15 CAN1:...
Page 488: Transmission Interrupt Enable Register (Tier)
CHAPTER 21 CAN CONTROLLER 21.4.16 Transmission Interrupt Enable Register (TIER) This register enables or disables the transmission interrupt by the message buffer (x). The transmission interrupt is generated at transmission completion (when TCx of the transmission complete register (TCR) is 1). Register Configuration Figure 21.4-16 Configuration of the Transmission Interrupt Enable Register (TIER) Address...
Page 489: Reception Complete Register (Rcr)
21.4.17 Reception Complete Register (RCR) At completion of storing received message in the message buffer (x), RCx becomes 1. If RIEx of the reception complete interrupt enable register (RIER) is 1, an interrupt occurs. Register Configuration Figure 21.4-17 Configuration of the Reception Complete Register (RCR) Address bit15 CAN1:...
Page 490: Remote Request Receiving Register (Rrtrr)
CHAPTER 21 CAN CONTROLLER 21.4.18 Remote Request Receiving Register (RRTRR) After a remote frame is stored in the message buffer (x), RRTRx becomes 1 (at the same time as RCx setting to 1). Register Configuration Figure 21.4-18 Configuration of the Remote Request Receiving Register (RRTRR) Address bit15 CAN1:...
Page 491: Receive Overrun Register (Rovrr)
21.4.19 Receive Overrun Register (ROVRR) If RCx of the reception complete register (RCR) is 1 when completing storing of a received message in the message buffer (x), ROVRx becomes 1, indicating that reception has overrun. Register Configuration Figure 21.4-19 Configuration of the Receive overrun Register (ROVRR) Address bit15 CAN1:...
Page 492: Reception Interrupt Enable Register (Rier)
CHAPTER 21 CAN CONTROLLER 21.4.20 Reception Interrupt Enable Register (RIER) Reception interrupt enable register (RIER) enables or disables the reception interrupt by the message buffer (x). The reception interrupt is generated at reception completion (when RCx of the reception completion register (RCR) is 1). Register Configuration Figure 21.4-20 Configuration of the Reception Interrupt Enable Register (RIER) Address...
Page 493: Acceptance Mask Select Register (Amsr)
21.4.21 Acceptance Mask Select Register (AMSR) This register selects masks (acceptance mask) for comparison between the received message ID’s and the message buffer ID. Register Configuration Figure 21.4-21 Configuration of the Acceptance Mask Select Register (AMSR) Address bit7 CAN1: 007D10 AMS3.1 Address bit15...
Page 494 CHAPTER 21 CAN CONTROLLER Register Function Table 21.4-7 Selection of Acceptance Mask AMSx.1 AMSx.0 Notes: • AMSx.1 and AMSx.0 should be set when the message buffer (x) is invalid (BVALx of the message buffer valid register (BVALR) is 0). Setting when the buffer is valid (BVALx = 1) may cause unnecessary received messages to be stored.
Page 495: Acceptance Mask Registers 0 And 1 (Amr0 And Amr1)
21.4.22 Acceptance Mask Registers 0 and 1 (AMR0 and AMR1) There are two acceptance mask registers, which are available either in the standard frame format or extended frame format. AM28 to AM18 (11 bits) are used for acceptance masks in the standard frame format and AM28 to AM0 (29 bits) are used for acceptance masks in the extended format.
Page 496 CHAPTER 21 CAN CONTROLLER Figure 21.4-23 Configuration of the Acceptance Mask Register 1 (AMR1) Address bit7 CAN1: 007D18 AM28 Address bit15 CAN1: 007D19 AM20 Address bit7 CAN1: 007D1A AM12 Address bit15 CAN1: 007D1B : Read/Write : Undefined − : Unused : Used bit in typical frame format Register Function 0: Compare...
Page 497: Message Buffers
21.4.23 Message Buffers There are 16 message buffers. Message buffer x (x = 0 to 15) consists of an ID register (IDRx), DLC register (DLCRx), and data register (DTRx). Message Buffers Register Configuration • ID register x (x = 0 to 15) (IDRx) This register is a ID register of the message buffer.
Page 498 CHAPTER 21 CAN CONTROLLER Message buffer that can be used as multi level message buffer When the same receipt filter is set in 1 or more message buffers, the message buffer can be used as a multi level message buffer. As a result, the reserve to the reception time is given.
Page 499: Id Register X (X = 0 To 15) (Idrx)
21.4.24 ID Register x (x = 0 to 15) (IDRx) This register is the ID register for message buffer (x). Register Configuration Figure 21.4-24 Configuration of the ID Registers (IDRx) Address + 4 × x CAN1: 007C20 Address + 4 × x CAN1: 007C21 Address...
Page 500 CHAPTER 21 CAN CONTROLLER Register Function When using the message buffer (x) in the standard frame format (IDEx of the IDE register (IDER) = 0), use 11 bits of ID28 to ID18. When using the buffer in the extended frame format (IDEx = 1), use 29 bits of ID28 to ID0.
Page 501: Dlc Register X (X = 0 To 15) (Dlcrx)
21.4.25 DLC Register x (x = 0 to 15) (DLCRx) This register is the DLC register for message buffer (x). Register Configuration Figure 21.4-25 Configuration of the DLC Registers (DLCRx) Address + 2 × x CAN1: 007C60 R/W : Read/Write : Undefined −...
Page 502: Data Register X (X = 0 To 15) (Dtrx)
CHAPTER 21 CAN CONTROLLER 21.4.26 Data Register x (x = 0 to 15) (DTRx) This register is the data register for message buffer (x). This register is used only in transmitting and receiving a data frame but not in transmitting and receiving a remote frame. Register Configuration Figure 21.4-26 Configuration of the Data Registers (DTRx) Address...
Page 503 Register Function Sets transmitted message data (any of 0 to 8 bytes). Data is transmitted in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. Stores received message data. Data is stored in the order of BYTE0, BYTE1, ..., BYTE7, starting with the MSB. Even if the received message data is less than 8 bytes, the remaining bytes of the data register (DTRx), to which data are stored, are undefined.
Page 504: Transmission Of Can Controller
CHAPTER 21 CAN CONTROLLER 21.5 Transmission of CAN Controller When 1 is written to TREQx of the transmission request register (TREQR), transmission by the message buffer (x) starts. At this time, TREQx becomes 1 and TCx of the transmission complete register (TCR) becomes 0. Starting Transmission of CAN Controller If RFWTx of the remote frame receiving wait register (RFWTR) is 0, transmission starts immediately.
Page 505: Transmission Flowchart Of Can Controller
Completing Transmission of CAN Controller When transmission is successful, RRTRx becomes 0, TREQx becomes 0, and TCx of the transmission complete register (TCR) becomes 1. If the transmission complete interrupt is enabled (TIEx of the transmission complete interrupt enable register (TIER) is 1), an interrupt occurs. Transmission Flowchart of CAN Controller Figure 21.5-1 Transmission Flowchart of the CAN Controller A data frame is transmitted.
Page 506: Reception Of Can Controller
CHAPTER 21 CAN CONTROLLER 21.6 Reception of CAN Controller Reception starts when the start of data frame or remote frame (SOF) is detected on the CAN bus. Acceptance Filtering The received message in the standard frame format is compared with the message buffer (x) set in the standard frame format (IDEx of the IDE register (IDER) is 0).
Page 507: Receive Overrun
Figure 21.6-1 shows a flowchart for determining the message buffer (x) where received messages are to be stored. It is recommended that message buffers be arranged in the following order: message buffers in which each AMSR bit is set to All Bits Compare, message buffers using AMR0 or AMR1, and message buffers in which each AMSR bit is set to All Bits Mask.
Page 508: Completing Reception
CHAPTER 21 CAN CONTROLLER Completing Reception RCx of the reception complete register (RCR) becomes 1 after storing the received message. If a reception interrupt is enabled (RIEx of the reception interrupt enable register (RIER) is 1), an interrupt occurs. Note: This CAN controller will not receive any messages transmitted by itself.
Page 509: Reception Flowchart Of Can Controller
21.7 Reception Flowchart of CAN Controller Figure 21.7-1 shows a reception flowchart of the CAN controller. Reception Flowchart of the CAN Controller Figure 21.7-1 Reception Flowchart of the CAN Controller Data frame RRTRx:=0 Detection of start of data frame or remote frame (SOF) Is any message buffer (x) passing to the acceptance filter found? Is reception...
Page 510: How To Use Can Controller
CHAPTER 21 CAN CONTROLLER 21.8 How to Use CAN Controller The following settings are required to use the CAN controller; • Bit timing • Frame format • ID • Acceptance filter • Low-power consumption mode Setting Bit Timing The bit timing register (BTR) should be set during bus operation stop (when the bus operation stop bit (HALT) of the control status register (CSR) is 1).
Page 511 Setting Low-power Consumption Mode To set the F MC-16LX in a low-power consumption mode (Stop and Timebase timer), write 1 to the bus operation stop bit (HALT) of the control status register (CSR), and then check that the bus operation has stopped (HALT = 1).
Page 512: Procedure For Transmission By Message Buffer (X)
CHAPTER 21 CAN CONTROLLER 21.9 Procedure for Transmission by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, set BVALx to 1 to activate the message buffer (x). Procedure for Transmission by Message Buffer (x) Setting transmit data length code Set the transmit data length code (byte count) to DLC3 to DLC0 of the DLC register (DLCRx).
Page 513 Setting conditions for starting transmission (only for transmission of data frame) Set RFWTx of the remote frame receiving wait register (RFWTR) to 0 to start transmission immediately after a request for data frame transmission is set (TREQx of the transmission request register (TREQR) is 1 and TRTRx of the transmission RTR register (TRTRR) is 0).
Page 514: Procedure For Reception By Message Buffer (X)
CHAPTER 21 CAN CONTROLLER 21.10 Procedure for Reception by Message Buffer (x) After setting the bit timing, frame format, ID, and acceptance filter, make the settings described below. Procedure for Reception by Message Buffer (x) Setting reception interrupt To enable reception interrupt, set RIEx of the reception interrupt enable register (RIER) to 1. To disable reception interrupt, set RIEx to 0.
Page 515 Figure 21.10-1 Example of Receive Interrupt Handling Interrupt with RCx = 1 Read received messages. A:=ROVRx ROVRx:=0 A = 0? RCx:=0...
Page 516: 21.11 Setting Configuration Of Multi-Level Message Buffer
CHAPTER 21 CAN CONTROLLER 21.11 Setting Configuration of Multi-level Message Buffer If the receptions are performed frequently, or if several different ID’s of messages are received, in other words, if there is insufficient time for handling messages, more than 1 message buffer can be combined into a multi-level message buffer to provide allowance for processing time of the received message by CPU.
Page 517 Figure 21.11-1 Examples of Operation of Multi-level Message Buffer Initialization AMS15, AMS14, AMS13 AMSR 10 10 10 . . . AM28 to AM18 Select AMR0. AMS0 0000 1111 111 ID28 to ID18 . . . Message buffer 13 0101 0000 000 Message buffer 14 0101 0000 000 Message buffer 15...
Page 518: 21.12 Setting The Can Direct Mode Register
CHAPTER 21 CAN CONTROLLER 21.12 Setting the CAN Direct Mode Register To operate CAN normally, this register must be set correctly. CAN Direct Mode Register (CDMR) (Only MB90V340) Figure 21.12-1 Configuration of the CAN Direct Mode Register (CDMR) (Only MB90V340) Address: CAN0: 00796E R/W : Readable and writable...
Page 519: 21.13 Precautions When Using Can Controller
21.13 Precautions when Using CAN Controller Use of the CAN Controller requires the following cautions. Caution for Disabling Message Buffers by BVAL Bits The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set disabled while CAN Controller is participating in CAN communication.
Page 520: Setting Of Can Direct Mode
CHAPTER 21 CAN CONTROLLER Setting of CAN Direct Mode MB90360 does not provide the clock modulation function. For this reason, ensure that the DIRECT bit of the CAN direct mode register (CDMR) is set to 1 when CAN is used. Note that the CAN controller will not normally operate without correct setting of the DIRECT bit.
Page 521: Chapter 22 Address Match Detection Function
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and its operation. 22.1 Overview of Address Match Detection Function 22.2 Block Diagram of Address Match Detection Function 22.3 Configuration of Address Match Detection Function 22.4 Explanation of Operation of Address Match Detection Function 22.5 Program Example of Address Match Detection Function...
Page 522: Overview Of Address Match Detection Function
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.1 Overview of Address Match Detection Function If the address of the instruction to be processed next to the instruction currently processed by the program matches the address set in the detect address setting registers, the address match detection function forcibly replaces the next instruction to be processed by the program with the INT9 instruction to branch to the interrupt processing program.
Page 523: Block Diagram Of Address Match Detection Function
22.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Address detection control register (PACSR0/PACSR1) • Detect address setting registers (PADR0 to PADR5) Block Diagram of Address Match Detection Function Figure 22.2-1 shows the block diagram of the address match detection function.
Page 524: Configuration Of Address Match Detection Function
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.3 Configuration of Address Match Detection Function This section lists and details the registers used by the address match detection function. List of Registers and Reset Values of Address Match Detection Function Figure 22.3-1 List of Registers and Reset Values of Address Match Detection Function Address detection control register 0(PACSR0) Address detection control register 1(PACSR1) Detection address setting register 0(PADR0): Low...
Page 525: Address Detection Control Register (Pacsr0/Pacsr1)
22.3.1 Address Detection Control Register (PACSR0/PACSR1) The address detection control register enables or disables output of an interrupt at an address match. When an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is generated. Address Detection Control Register 0 (PACSR0) Figure 22.3-2 Address Detection Control Register 0 (PACSR0) Address...
Page 526 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Table 22.3-1 Functions of Address Detection Control Register (PACSR0) Bit Name bit7, Reserved: reserved bits bit6 bit5 AD2E: Address match detec- tion enable bit 2 bit4 Reserved: reserved bit bit3 AD1E: Address match detection enable bit 1 bit2 Reserved: reserved bit bit1...
Page 527 Address Detection Control Register 1 (PACSR1) Figure 22.3-3 Address Detection Control Register 1 (PACSR1) Address AD5E AD4E 0 0 0 0 3 B served served served Read/Write : Reset value CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Reset value AD3E 0 0 0 0 0 0 0 0 served served bit 8...
Page 528 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Table 22.3-2 Functions of Address Detection Control Register (PACSR1) Bit Name bit15, Reserved: reserved bit bit14 bit13 AD5E: Address match detec- tion enable bit 5 bit12 Reserved: reserved bit bit11 AD4E: Address match detection enable bit 4 bit10 Reserved: reserved bit bit9...
Page 529: Detect Address Setting Registers (Padr0 To Padr5)
22.3.2 Detect Address Setting Registers (PADR0 to PADR5) The value of an address to be detected is set in the detect address setting registers. When the address of the instruction processed by the program matches the address set in the detect address setting registers, the next instruction is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed.
Page 530 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Functions of Detect Address Setting Registers • There are six detect address setting registers (PADR0 to PADR5) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits. Table 22.3-3 Address Setting of Detect Address Setting Registers Register Name Detect address setting register 0...
Page 531 Figure 22.3-5 Setting of Starting Address of Instruction Code to be Replaced by INT9 Instruction Instruction Address code FF001C : A8 00 00 FF001F : 4A 00 00 FF0022 : 4A 80 08 Notes: • When an address of other than the first byte is set to the detect address setting registers (PADR0 to PADR5), the instruction code is not replaced by INT9 instruction and a program of an interrupt processing is not be performed.
Page 532: Explanation Of Operation Of Address Match Detection Function
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.4 Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the detection address setting registers (PADR0 to PADR5), the address match detection function will replace the first instruction code executed by the CPU with the INT9 instruction (01 ) to branch to the interrupt processing program.
Page 533: Example Of Using Address Match Detection Function
22.4.1 Example of using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function. System Configuration and E System configuration Figure 22.4-2 gives an example of the system configuration using the address match detection function. Figure 22.4-2 Example of System Configuration Using Address Match Detection Function MC16LX CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION...
Page 534 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION PROM Memory Map Figure 22.4-3 shows the allocation of the patch program and data at storing the patch program in E Figure 22.4-3 Allocation of E PADR0 PADR1 PADR5 Patch program byte count The total byte count of the patch program (main body) is stored. If the byte count is "00 no patch program is provided.
Page 535 Setting and Operating State Initialization PROM data are all cleared to "00 Occurrence of program error • By using the connector (UART), information about the patch program is transmitted to the MCU MC16LX) from the outside according to the allocation of the E •...
Page 536: Flow Of Patch Processing For Patch Program
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION Operation of Address Match Detection Function at Storing Patch Program in E Figure 22.4-4 shows the operation of the address match detection function at storing the patch program in PROM. Figure 22.4-4 Operation of Address Match Detection Function at Storing Patch Program in E 000000 FFFFFF (1) Execution of detection address setting of reset sequence and normal program...
Page 537 Figure 22.4-5 Flow of Patch Processing for Patch Program MB90360 000000 I/O area Register/RAM area 000100 000400 Patch program RAM area 000480 Stack area 000900 Detection address setting register FF0000 Program error FF8000 FF8050 FFFFFF Reset Read the 00 PROM PROM : 0000 Read detect address...
Page 538: Program Example Of Address Match Detection Function
CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION 22.5 Program Example of Address Match Detection Function This section gives a program example for the address match detection function. Program Example for Address Match Detection Function Processing specifications If the address of the instruction to be executed by the program matches the address set in the detection address setting register (PADR0), the INT9 instruction is executed.
Page 539 RETI CODE ENDS ;---------Vector setting------------------------------------------ VECT CSEG ABS=0FFH 00FFD8H WARI 00FFDCH START VECT ENDS START CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION ;Return from interrupt processing ;Set reset vector ;Set to single-chip mode...
Page 540 CHAPTER 22 ADDRESS MATCH DETECTION FUNCTION...
Page 541: Chapter 23 Rom Mirroring Module
CHAPTER 23 ROM MIRRORING MODULE This chapter describes the functions and operations of the ROM mirroring function select module. 23.1 Overview of ROM Mirroring Function Select Module 23.2 ROM Mirroring Function Select Register (ROMM)
Page 542: Overview Of Rom Mirroring Function Select Module
CHAPTER 23 ROM MIRRORING MODULE 23.1 Overview of ROM Mirroring Function Select Module The ROM mirroring function select module provides a setting so that ROM data in the FF bank can be read by access to the 00 bank. Block Diagram of ROM Mirroring Function Select Module Figure 23.1-1 Block Diagram of ROM Mirroring Function Select Module Address Data...
Page 543 Memory Space when ROM Mirroring Function Enabled/Disabled Figure 23.1-3 shows the availability of access to memory space when the ROM mirroring function is enabled or disabled. Figure 23.1-3 Memory Space when ROM Mirroring Function Enabled/Disabled FFFFFF Address #1 010000 008000 007900 Address #2 000100...
Page 544: Rom Mirroring Function Select Register (Romm)
CHAPTER 23 ROM MIRRORING MODULE 23.2 ROM Mirroring Function Select Register (ROMM) The ROM mirroring function select register (ROMM) enables or disables the ROM mirroring function. When the ROM mirroring function is enabled, ROM data in the FF bank can be read by access to the 00 bank. ROM Mirroring Function Select Register (ROMM) Figure 23.2-1 ROM Mirroring Function Select Register (ROMM) Address...
Page 545: Chapter 24 512K-Bit Flash Memory
CHAPTER 24 512K-BIT FLASH MEMORY This chapter explains the functions and operation of the 512K-bit flash memory. The following three methods are available for writing data to and erasing data from the flash memory: • Parallel programmer • Serial programmer •...
Page 546: Overview Of 512K-Bit Flash Memory
CHAPTER 24 512K-BIT FLASH MEMORY 24.1 Overview of 512K-bit Flash Memory The 512K-bit flash memory is mapped to the FF functions of the flash memory interface circuit enable read-access and program-access from the CPU in the same way as mask ROM. Instructions from the CPU can be used via the flash memory interface circuit to write data to and erase data from the flash memory.
Page 547: Block Diagram Of The Entire Flash Memory And Sector Configuration Of The Flash Memory
24.2 Block Diagram of the Entire Flash Memory and Sector Configuration of the Flash Memory Figure 24.2-1 shows a block diagram of the entire flash memory with the flash memory interface circuit included. Figure 24.2-2 shows the sector configuration of the flash memory.
Page 548 CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.2-2 Sector Configuration of the 512K-bit Flash Memory *: The programmer address is equivalent to the CPU address when data is written to the flash memory using a paral- lel programmer. When a general programmer is used for writing/erasing, this address is used for writing/erasing. MB90F362/T(S), Programmer address*...
Page 549: Write/Erase Modes
24.3 Write/Erase Modes The flash memory can be accessed in 2 different ways: Flash memory mode and alternative mode. Flash memory mode enables data to be directly written to or erased from the external pins. Alternative mode enables data to be written to or erased from the CPU via the internal bus.
Page 550 CHAPTER 24 512K-BIT FLASH MEMORY Table 24.3-1 Flash Memory Control Signals (Developing: it is possible to change) MB90F362/T(S), MB90F367/T(S) Pin number Normal function LQFP 41 (45) P42(P44) 12 to 19 P50 to P57 3 to 10 P60 to P67 29 to 36 P27 to P20 MBM29LV200 Flash memory mode...
Page 551: Flash Memory Control Status Register (Fmcs)
24.4 Flash Memory Control Status Register (FMCS) This section shows the function of the flash memory control status register (FMCS). Flash Memory Control Status Register (FMCS) Figure 24.4-1 Flash Memory Control Status Register (FMCS) Address: 0000AE INTE WE RDY served R/W R/W R/W R/W : Read/Write : Read only...
Page 552 CHAPTER 24 512K-BIT FLASH MEMORY Table 24.4-1 Functions of Control Status Register (FMCS) Bit Name bit7 INTE: This bit enables or disables an interrupt as programming/erasing flash memory is Flash memory terminated. programming/erasing When set to 1: If the flash memory operation flag bit is set to 1 (FMCS: RDYINT=1), interrupt enable bit bit6 RDYINT:...
Page 553 CHAPTER 24 512K-BIT FLASH MEMORY Figure 24.4-2 Transitions of the RDYINT and RDY Bits Automatic algorithm end timing RDYINT bit RDY bit 1 Machine cycle...
Page 554: Starting The Flash Memory Automatic Algorithm
CHAPTER 24 512K-BIT FLASH MEMORY 24.5 Starting the Flash Memory Automatic Algorithm Three types of commands are available for starting the flash memory automatic algorithm: Read/Reset, Write, and Chip Erase. Command Sequence Table Table 24.5-1 lists the commands used for flash memory write/erase. All of the data written to the command register is in bytes, but use word access to write.
Page 555: Confirming The Automatic Algorithm Execution State
24.6 Confirming the Automatic Algorithm Execution State Because the write/erase flow of the flash memory is controlled using the automatic algorithm, the flash memory has hardware for posting its internal operating state and completion of operation. This automatic algorithm enables confirmation of the operating state of the built-in flash memory using the following hardware sequences flag.
Page 556 CHAPTER 24 512K-BIT FLASH MEMORY To determine whether automatic writing or chip erase is being executed, the hardware sequence flags can be checked or the status can be determined from the RDY bit of the flash memory control status register (FMCS) that indicates whether writing has been completed.
Page 557: Data Polling Flag (Dq7)
24.6.1 Data Polling Flag (DQ7) The data polling flag (DQ7) uses the data polling function to post that the automatic algorithm is being executed or has terminated Data Polling Flag (DQ7) Table 24.6-3 and Table 24.6-4 list the state transitions of the data polling flag. Table 24.6-3 State Transition of Data Polling Flag (State change at normal operation) Operating State Table 24.6-4 State Transition of Data Polling Flag (State change at abnormal operation)
Page 558: Toggle Bit Flag (Dq6)
CHAPTER 24 512K-BIT FLASH MEMORY 24.6.2 Toggle Bit Flag (DQ6) Like the data polling flag (DQ7), the toggle bit flag (DQ6) uses the toggle bit function to post that the automatic algorithm is being executed or has terminated. Toggle Bit Flag (DQ6) Table 24.6-5 and Table 24.6-6 list the state transitions of the toggle bit flag.
Page 559: Timing Limit Exceeded Flag (Dq5)
24.6.3 Timing Limit Exceeded Flag (DQ5) The timing limit exceeded flag (DQ5) is used to post that execution of the automatic algorithm has exceeded the time (internal pulse count) prescribed in the flash memory. Timing Limit Exceeded Flag (DQ5) Table 24.6-7 and Table 24.6-8 list the state transitions of the timing limit exceeded flag. Table 24.6-7 State Transition of Timing Limit Exceeded Flag (State change at normal operation) Operating State...
Page 560: Detailed Explanation Of Writing To And Erasing Flash Memory
CHAPTER 24 512K-BIT FLASH MEMORY 24.7 Detailed Explanation of Writing to and Erasing Flash Memory This section describes each operation procedure of flash memory Read/Reset, Write, Chip Erase when a command that starts the automatic algorithm is issued. Detailed Explanation of Flash Memory Write/erase The flash memory executes the automatic algorithm by issuing a command sequence (see Table 24.5-1 ) for a write cycle to the bus to perform Read/Reset, Write, or Chip Erase operations.
Page 561: Setting The Read/Reset State
24.7.1 Setting The Read/Reset State This section describes the procedure for issuing the Read/Reset command to set the flash memory to the read/reset state. Setting the Flash Memory to the Read/reset State The flash memory can be set to the read/reset state by sending the Read/Reset command in the command sequence table (see Table 24.5-1 ) continuously to the target sector in the flash memory.
Page 562: Writing Data
CHAPTER 24 512K-BIT FLASH MEMORY 24.7.2 Writing Data This section describes the procedure for issuing the Write command to write data to the flash memory. Writing Data to the Flash Memory The data write automatic algorithm of the flash memory can be started by sending the Write command in the command sequence table (see Table 24.5-1 ) continuously to the target sector in the flash memory.
Page 563 Figure 24.7-1 Example of the Flash Memory Write Procedure FMCS: WE (bit 5) Flash programming enabled Program command sequence (1) FxAAAA ← XXAA (2) Fx5554 ← XX55 (3) FxAAAA ← XXA0 (4) Program address ← Program data Internal address read Timing limit (DQ5) Internal address read DATA...
Page 564: Erasing All Data (Erasing Chips)
CHAPTER 24 512K-BIT FLASH MEMORY 24.7.3 Erasing All Data (Erasing Chips) This section describes the procedure for issuing the Chip Erase command to erase all data in the flash memory. Erasing all Data in the Flash Memory (Erasing chips) All data can be erased from the flash memory by sending the Chip Erase command in the command sequence table (see Table 24.5-1 ) continuously to the target sector in the flash memory.
Page 565 Figure 24.7-2 Example of the Flash Memory Chip Procedure Start writing FMCS: WE (bit 5) Flash programming enabled Erase command sequence (1) FFAAAA ← XXAA (2) FF5554 ← XX55 (3) FFAAAA ← XX80 (4) FFAAAA ← XXAA (5) FF5554 ← XX55 (6) FFAAAA ←...
Page 566: Notes On Using 512K-Bit Flash Memory
CHAPTER 24 512K-BIT FLASH MEMORY 24.8 Notes on Using 512K-bit Flash Memory This section contains notes on using 512K-bit flash memory. Notes on Using Flash Memory Input of a hardware reset (RST) To input a hardware reset when the automatic algorithm has not been started and reading is in progress, a minimum "L"...
Page 567: Flash Security Feature
24.9 Flash Security Feature Flash security feature provides possibilities to protect the content of the flash memory. Abstract By writing the protection code of "01 is restricted. Once the flash memory is protected, performing the chip erase operation only can unlock the function.
Page 568 CHAPTER 24 512K-BIT FLASH MEMORY...
Page 569: Chapter 25 Examples Of Mb90F362/T(S), Mb90F367/T(S)Serial Programming Connection
MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CHAPTER 25 EXAMPLES OF CONNECTION This chapter shows an example of a serial programming connection using the AF220/AF210/AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer Corporation when the AF220/AF210/AF120/ AF110 flash serial microcontroller programer from Yokogawa Digital Computer Corporation is used. 25.1 Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) 25.2 Example of Serial Programming Connection (User Power Supply...
Page 570: Basic Configuration Of Serial Programming Connection With Mb90F362/T(S), Mb90F367/T(S)
ROM. This section provides the related specifications. Basic Configuration of Serial Programming Connection with MB90F362/T(S), MB90F367/T(S) Fujitsu standard serial on-board writing uses the Yokogawa Digital Computer Corporation AF220/AF210/ AF120/AF110 flash microcontroller programmer. Figure 25.1-1 shows the basic configuration for the example serial programming connection of MB90F362/ T(S), MB90F367/T(S).
Page 571 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION Table 25.1-1 Pin Used for Fujitsu Standard Serial on-board Programming Function MD2, Mode pins MD1, X0, X1 Oscillation pins P83, P84 Programming activation pins Reset pin SIN1 Serial data input pin...
Page 572 RS232C cable for programmer PC/AT AZ210 Standard target probe (a) cable length: 1 m FF201 Fujitsu F AZ290 Remote controller 2MB PC Card (optional) for flash memory sizes up to 128 KB 4MB PC Card (optional) for flash memory sizes up to 512 KB...
Page 573: Example Of Serial Programming Connection (User Power Supply Used)
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.2 Example of Serial Programming Connection (User Power Supply Used) Figure 25.2-1 shows an example of a serial programming connection when the user power supply is used. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer.
Page 574 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P83. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) AF220/AF210/AF120/AF110 write control pin...
Page 575: Example Of Serial Programming Connection (Power Supplied From Programmer)
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.3 Example of Serial Programming Connection (Power Supplied from Programmer) Figure 25.3-1 shows an example of a serial programming connection when power is supplied from the programmer. The value 1 and 0 are input to mode pins MD2 and MD0 from TAUX3 and TMODE of the AF220/AF210/AF120/AF110 programmer.
Page 576 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required in the same way that it is for P83. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) AF220/AF210/AF120/AF110 write control pin...
Page 577: Example Of Minimum Connection To Flash Microcontroller Programmer (User Power Supply Used)
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.4 Example of Minimum Connection to Flash Microcontroller Programmer (User Power Supply Used) Figure 25.4-1 shows an example of the minimum connection to the flash microcontroller programmer when the user power supply is used. Serial reprogramming mode: MD2, MD1, MD0 = 110.
Page 578 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) AF220/AF210/AF120/AF110 write control pin...
Page 579: Example Of Minimum Connection To Flash Microcontroller Programmer (Power Supplied From Programmer)
CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION 25.5 Example of Minimum Connection to Flash Microcontroller Programmer (Power Supplied from Programmer) Figure 25.5-1 shows an example of the minimum connection to the MB90F362/T(S), MB90F367/T(S) flash microcontroller programmer when power is supplied from the Programmer.
Page 580 CHAPTER 25 EXAMPLES OF MB90F362/T(S), MB90F367/T(S) SERIAL PROGRAMMING CONNECTION • Even if the SIN1, SOT1, and SCK1 pins are used for the user system, the control circuit shown in the figure below is required. (The /TICS signal of the flash microcontroller programmer can be used to disconnect the user circuit during serial programming.) AF220/AF210/AF120/AF110 write control pin...
Page 581: Chapter 26 Rom Security Function
CHAPTER 26 ROM SECURITY FUNCTION This chapter explains the ROM security function. 26.1 Overview of ROM Security Function...
Page 582: Overview Of Rom Security Function
The ROM security function protects the content of ROM. Overview of ROM Security Function The ROM security function is a function to prevent ROM data being read to the third party by limiting the access to ROM. Please contact to Fujitsu about details of this function.
Page 583: Appendix
APPENDIX The appendixes provide I/O maps, instructions, and other information. APPENDIX A I/O Maps APPENDIX B Instructions APPENDIX C Timing Diagrams in Flash Memory Mode APPENDIX D List of Interrupt Vectors...
Page 584: Appendix A I/O Maps
APPENDIX APPENDIX A I/O Maps Table A-1 lists addresses to be assigned to the registers in the peripheral blocks. I/O Maps (00XX Addresses) Table A-1 I/O Map (1/5) Address Register 000000 Reserved 000001 000002 Port 2 data register 000003 Reserved 000004 Port 4 data register 000005...
Page 585 Table A-1 I/O Map (2/5) Address Register 000019 Reserved 00001A Port A direction register 00001B Reserved 00001D 00001E Port 2 pull-up control register 00001F Reserved 000020 Serial mode register 0 000021 Serial control register 0 000022 Reception/transmission data register 0 000023 Serial status register 0 Extended communication control...
Page 586 APPENDIX Table A-1 I/O Map (3/5) Address Register 00004B Reserved 00004C PPGE operation mode control register 00004D PPGF operation mode control register PPGCF 00004E PPGE/F count clock selection register PPGEF 00004F Reserved 000050 Input capture control status 0/1 000051 Input capture edge 0/1 000052 Input capture control status 2/3 000053...
Page 587 Table A-1 I/O Map (4/5) Address Register 00009F Delayed interrupt/release register 0000A0 Low-power mode control register 0000A1 Clock selection register 0000A2 Reserved 0000A7 0000A8 Watchdog timer control register 0000A9 Time base timer control register 0000AA Watch timer control register 0000AB Reserved 0000AD Flash control status...
Page 588 APPENDIX Table A-1 I/O Map (5/5) Address Register 0000CA External interrupt enable 1 0000CB External interrupt request 1 0000CC External interrupt level 1 0000CD External interrupt level 1 0000CE External interrupt 1 source select 0000CF PLL/subclock control register 0000D0 Reserved 0000FF Abbreviation Access...
Page 589 I/O map (79XX - 7FXX addresses) Table A-2 I/O Map (7900 - 7FFF Address Register 7900 Reserved 7917 7918 Reload register LC 7919 Reload register HC 791A Reload register LD 791B Reload register HD 791C Reload register LE 791D Reload register HE 791E Reload register LF 791F...
Page 590 APPENDIX Table A-2 I/O Map (7900 - 7FFF Address Register 7950 Reserved 795F 7960 Clock supervisor control register 7961 Reserved 796D CAN direct mode register 796E (For only MB90V340) 796F Reserved 79DF 79E0 Detection address setting 0 79E1 Detection address setting 0 79E2 Detection address setting 0 79E3...
Page 591 Table A-2 I/O Map (7900 - 7FFF Address Register 7D00 Reserved for CAN interface 1. (For more information, see Table 21.3-2 .) 7DFF 7E00 Reserved 7FFF Note: Any write access to reserved addresses in I/O map should not be perfoermed. A read access to reserved address results in reading "X".
Page 592: Appendix B Instructions
APPENDIX APPENDIX B Instructions Appendix B describes the instructions used by the F B.1 Instruction Types B.2 Addressing B.3 Direct Addressing B.4 Indirect Addressing B.5 Execution Cycle Count B.6 Effective address field B.7 How to Read the Instruction List B.8 F MC-16LX Instruction List B.9 Instruction Map MC-16LX.
Page 593: Instruction Types
Instruction Types The F MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. Instruction Types The F MC-16LX supports the following 351 types of instructions: •...
Page 594: Addressing
APPENDIX Addressing With the F MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used.
Page 595 Effective Address Field Table B.2-1 lists the address formats specified by the effective address field. Table B.2-1 Effective Address Field Code Representation @RW0 @RW1 @RW2 @RW3 @RW0+ @RW1+ @RW2+ @RW3+ @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 @RW0+RW7...
Page 596: Direct Addressing
APPENDIX Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. Direct Addressing Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of Immediate Addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution After execution Register direct addressing...
Page 597 Figure B.3-2 Example of Register Direct Addressing (This instruction transfers the eight low-order bits of A to the general-purpose MOV R0, A register R0.) Before execution After execution Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space.
Page 598 APPENDIX Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of Direct Branch Addressing (addr24) (This instruction causes an unconditional branch by direct branch 24-bit JMPP 333B20H addressing.)
Page 599 Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB).
Page 600 APPENDIX I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000 where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O Direct Bit Addressing (io:bp) SETB I:0C1H:0 Before execution After execution...
Page 601 Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of Vector Addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.)
Page 602: Indirect Addressing
APPENDIX Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. Indirect Addressing Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used.
Page 603 Figure B.4-2 Example of Register Indirect Addressing with Post Increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ Before execution After execution Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of general-purpose register RWj.
Page 604 APPENDIX Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): •...
Page 605 Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-Kbyte bank.
Page 606 APPENDIX POPW RW0, RW4 Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of Accumulator Indirect Addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Page 607 Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB).
Page 608 APPENDIX Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of Indirect Specification Branch Addressing (@eam) (This instruction causes an unconditional branch by register indirect addressing.) JMP @RW0 Before execution After execution...
Page 609: Execution Cycle Count
Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value"...
Page 610 APPENDIX Calculating the execution cycle count Table B.5-1 lists execution cycle counts and Table B.5-2 and Table B.5-3 summarize correction value data. Table B.5-1 Execution Cycle Counts in Each Addressing Mode Code @RWj @RWj+ @RWi+disp8 @RWi+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 *: (a) is used for Operand Execution cycle count in each...
Page 611 Table B.5-2 Cycle Count Correction Values for Counting Execution Cycles Operand Cycle count Internal register Internal memory Even address Internal memory Odd address External data bus 16-bit even address External data bus 16-bit odd address External data bus 8-bits *1: (b), (c), and (d) are used for Instruction List".
Page 612: Effective Address Field
APPENDIX Effective address field Table B.6-1 shows the effective address field. Effective Address Field Table B.6-1 Effective Address Field Code @RW0 @RW1 @RW2 @RW3 @RW0+ @RW1+ @RW2+ @RW3+ @RW0+disp8 @RW1+disp8 @RW2+disp8 @RW3+disp8 @RW4+disp8 @RW5+disp8 @RW6+disp8 @RW7+disp8 @RW0+disp16 @RW1+disp16 @RW2+disp16 @RW3+disp16 @RW0+RW7 @RW1+RW7 @PC+disp16...
Page 613: How To Read The Instruction List
How to Read the Instruction List Table B.7-1 describes the items used in the F describes the symbols used in the same list. Description of Instruction Presentation Items and Symbols Table B.7-1 Description of Items in the Instruction List (1/2) Item Mnemonic Operation...
Page 614 APPENDIX Table B.7-1 Description of Items in the Instruction List (2/2) Item Table B.7-2 Explanation on Symbols in the Instruction List (1/2) Symbol brg1 brg2 addr16 addr24 ad24 0-15 ad24 16-23 Description Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory).
Page 615 Table B.7-2 Explanation on Symbols in the Instruction List (2/2) Symbol #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16 16-bit displacement...
Page 616: F 2 Mc-16Lx Instruction List
APPENDIX MC-16LX Instruction List Table B.8-1 to Table B.8-18 list the instructions used by the F MC-16LX Instruction List Table B.8-1 41 Transfer Instructions (byte) Mnemonic MOV A,dir MOV A,addr16 MOV A,Ri MOV A,ear MOV A,eam MOV A,io MOV A,#imm8 MOV A,@A MOV A,@RLi+disp8 MOVN A,#imm4...
Page 617 Table B.8-2 38 Transfer Instructions (byte) Mnemonic MOVW A,dir MOVW A,addr16 MOVW A,SP MOVW A,RWi MOVW A,ear MOVW A,eam MOVW A,io MOVW A,@A MOVW A,#imm16 MOVW A,@RWi+disp8 MOVW A,@RLi+disp8 MOVW dir,A MOVW addr16,A MOVW SP,A MOVW RWi,A MOVW ear,A MOVW eam,A MOVW io,A MOVW @RWi+disp8,A MOVW @RLi+disp8,A...
Page 618 APPENDIX Table B.8-3 42 Addition/subtraction Instructions (byte, word, long word) Mnemonic A,#imm8 A,dir A,ear A,eam 4 + (a) ear,A eam,A 5 + (a) ADDC ADDC A,ear ADDC A,eam 4 + (a) ADDDC A,#imm8 A,dir A,ear A,eam 4 + (a) ear,A eam,A 5 + (a) SUBC...
Page 619 Table B.8-4 12 Increment/decrement Instructions (byte, word, long word) Mnemonic 5+(a) 5+(a) INCW INCW 5+(a) DECW DECW 5+(a) INCL INCL 9+(a) DECL DECL 9+(a) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-5 11 Compare Instructions (byte, word, long word) Mnemonic A,ear...
Page 620 APPENDIX Table B.8-6 11 Unsigned Multiplication/division Instructions (word, long word) Mnemonic DIVU DIVU A,ear DIVU A,eam DIVUW A,ear DIVUW A,eam MULU MULU A,ear MULU A,eam MULUW MULUW A,ear MULUW A,eam *1: 3: Division by 0 7: Overflow 15: Normal *2: 4: Division by 0 8: Overflow 16: Normal *3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4: 4: Division by 0 7: Overflow 22: Normal *5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal...
Page 621 Table B.8-7 11 Signed Multiplication/division Instructions (word, long word) Mnemonic A,ear A,eam DIVW A,ear DIVW A,eam A,ear A,eam MULW MULW A,ear MULW A,eam *1: 3: Division by 0, 8 or 18: Overflow, 18: Normal *2: 4: Division by 0, 11 or 22: Overflow, 23: Normal *3: 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal *4: When dividend is positive;...
Page 622 APPENDIX Table B.8-8 39 Logic 1 Instructions (byte, word) Mnemonic A,#imm8 A,ear A,eam 4+(a) ear,A eam,A 5+(a) A,#imm8 A,ear A,eam 4+(a) ear,A eam,A 5+(a) A,#imm8 A,ear A,eam 4+(a) ear,A eam,A 5+(a) 5+(a) ANDW ANDW A,#imm16 ANDW A,ear ANDW A,eam 4+(a) ANDW ear,A ANDW...
Page 623 Table B.8-9 6 Logic 2 Instructions (long word) Mnemonic ANDL A,ear ANDL A,eam 7+(a) A,ear A,eam 7+(a) XORL A,ear XORL A,eam 7+(a) Note: See Table B.5-1 and Table B.5-2 for information on (a) to (d) in the table. Table B.8-10 6 Sign Inversion Instructions (byte, word) Mnemonic 5+(a) NEGW...
Page 624 APPENDIX Table B.8-12 18 Shift Instructions (byte, word, long word) Mnemonic RORC ROLC RORC RORC 5+(a) ROLC ROLC 5+(a) A,R0 A,R0 A,R0 ASRW LSRW A/SHRW A LSLW A/SHLW A ASRW A,R0 LSRW A,R0 LSLW A,R0 ASRL A,R0 LSRL A,R0 LSLL A,R0 *1: 6 when R0 is 0;...
Page 625 Table B.8-13 31 Branch 1 Instructions Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS addr16 @ear @eam 4+(a) JMPP @ear *3 JMPP @eam *3 6+(a) JMPP addr24 CALL @ear *4 CALL addr16 *5 7+(a) CALL @eam *4 CALLV #vct4 *5 CALLP @ear *6 CALLP @eam *6 11+(a)
Page 626 APPENDIX Table B.8-14 19 Branch 2 Instructions Mnemonic CBNE A,#imm8,rel CWBNE A,#imm16,rel CBNE ear,#imm8,rel CBNE eam,#imm8,rel *9 CWBNE ear,#imm16,rel CWBNE eam,#imm16,rel*9 DBNZ ear,rel DBNZ eam,rel DWBNZ ear,rel DWBNZ eam,rel #vct8 addr16 INTP addr24 INT9 RETI LINK #imm8 UNLINK RETP *1: 5 when a branch is made; otherwise, 4 *2: 13 when a branch is made;...
Page 627 Table B.8-15 28 Other Control Instructions (byte, word, long word) Mnemonic PUSHW PUSHW PUSHW PUSHW rlst POPW POPW POPW POPW rlst JCTX CCR,#imm8 CCR,#imm8 RP,#imm8 ILM,#imm8 MOVEA RWi,ear MOVEA RWi,eam 2+(a) MOVEA A,ear MOVEA A,eam 1+(a) ADDSP #imm8 ADDSP #imm16 A,brg1 brg2,A *1: PCB, ADB, SSB, USB, SPB: 1, DTB, DPR: 2...
Page 628 APPENDIX Table B.8-16 21 Bit Operand Instructions Mnemonic MOVB A,dir:bp MOVB A,addr16:bp MOVB A,io:bp MOVB dir:bp,A MOVB addr16:bp,A MOVB io:bp,A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp dir:bp,rel addr16:bp,rel io:bp,rel dir:bp,rel addr16:bp,rel io:bp,rel SBBS addr16:bp,rel WBTS io:bp WBTC...
Page 629 Table B.8-18 10 String Instructions Mnemonic MOVS / MOVSI MOVSD SCEQ / SCEQI SCEQD FILS / FILSI 6m+6 MOVSW / MOVSWI MOVSWD SCWEQ / SCWEQI SCWEQD FILSW / FILSWI 6m+6 *1: 5 when RW0 is 0, 4 + 7 x (RW0) when the counter expires, or 7n + 5 when a match occurs *2: 5 when RW0 is 0;...
Page 630: Instruction Map
APPENDIX Instruction Map Each F MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 to Table B.9-21 summarize the F instruction map. Structure of Instruction Map Bit operation Character string operation instructions instructions An instruction such as the NOP instruction that ends in one byte is completed within the basic page.
Page 631 Figure B.9-2 Correspondence between Actual Instruction Code and Instruction Map Byte 1 Instruction code Byte 2 *1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions. An example of an instruction code is shown in Table B.9-1 .
Page 632 APPENDIX Table B.9-2 Basic Page Map...
Page 633 APPENDIX B Instructions Table B.9-3 Bit Operation Instruction Map (first byte = 6C...
Page 634 APPENDIX Table B.9-4 Character String Operation Instruction Map (first byte = 6E...
Page 635 APPENDIX B Instructions Table B.9-5 2-byte Instruction Map (first byte = 6F...
Page 636 APPENDIX Table B.9-6 ea Instruction 1 (first byte = 70...
Page 637 APPENDIX B Instructions Table B.9-7 ea Instruction 2 (first byte = 71...
Page 638 APPENDIX Table B.9-8 ea Instruction 3 (first byte = 72...
Page 639 APPENDIX B Instructions Table B.9-9 ea Instruction 4 (first byte = 73...
Page 640 APPENDIX Table B.9-10 ea Instruction 5 (first byte = 74...
Page 641 APPENDIX B Instructions Table B.9-11 ea Instruction 6 (first byte = 75...
Page 642 APPENDIX Table B.9-12 ea Instruction 7 (first byte = 76...
Page 643 APPENDIX B Instructions Table B.9-13 ea Instruction 8 (first byte = 77...
Page 644 APPENDIX Table B.9-14 ea Instruction 9 (first byte = 78...
Page 645 APPENDIX B Instructions Table B.9-15 MOVEA RWi, ea Instruction (first byte = 79...
Page 646 APPENDIX Table B.9-16 MOV Ri, ea Instruction (first byte = 7A...
Page 647 APPENDIX B Instructions Table B.9-17 MOVW RWi, ea Instruction (first byte = 7B...
Page 648 APPENDIX Table B.9-18 MOV Ri, ea Instruction (first byte = 7C...
Page 649 APPENDIX B Instructions Table B.9-19 MOVW ea, Rwi Instruction (first byte = 7D...
Page 650 APPENDIX Table B.9-20 XCH Ri, ea Instruction (first byte = 7E...
Page 651 APPENDIX B Instructions Table B.9-21 XCHW RWi, ea Instruction (first byte = 7F...
Page 652: Appendix C Timing Diagrams In Flash Memory Mode
APPENDIX APPENDIX C Timing Diagrams in Flash Memory Mode Each timing diagram for the external pins of the Flash devices in MB90360 series during Flash Memory mode is shown below. Data Read by Read Access AQ16 Figure C-1 Timing Diagram for Read Access Address stable High-Z Output defined...
Page 653 Write, Data Polling, Read (WE control) Figure C-2 Write, Data Polling, Read (WE control) 3rd bus cycle FxAAAA AQ18 to AQ0 GHWL DQ7 to DQ0 : Write address : Write data : Reverse output of write data : Output of write data Note: •...
Page 654 APPENDIX Write, Data Polling, Read (CE control) Figure C-3 Timing Diagram for Write Access (CE control) 3rd bus cycle AQ18 FxAAAA : Write address : Write data : Reverse output of write data : Output of write data Note: • Describes the last 2-bus cycle of 4-bus cycle sequences. •...
Page 655: Chip Erase/Sector Erase Command Sequence
Chip Erase/sector Erase Command Sequence Figure C-4 Timing Diagram for Write Access (chip erasing/sector erasing) AQ18 to FxAAAA GHWL DQ7 to DQ0 Notes: • SA is the sector address at erasing sector. • The address is FxAAAA • "Fx" in "FxAAAA" described as address is any of F. APPENDIX C Timing Diagrams in Flash Memory Mode Fx5555 FxAAAA...
Page 656: Toggle Bit
APPENDIX Data Polling Note: DQ7 is valid data (The device terminates automatic operation). Toggle Bit Data (DQ7 to DQ0) Note: DQ6 stops toggling (The device terminates automatic operation). Figure C-5 Timing Diagram for Data Polling or t WHWH1 WHWH2 DQ6 to DQ0 flag output Figure C-6 Timing Diagram for Toggle Bit DQ6 = Toggle DQ6 = Toggle...
Page 657: Ry/By Timing During Writing/Erasing
RY/BY Timing during Writing/erasing Figure C-7 Timing Diagram for Output of RY/BY Signal during Writing/erasing RY/BY RST and RY/BY Timing Figure C-8 Timing Diagram for Output of RY/BY Signal at Hardware Reset RY/BY APPENDIX C Timing Diagrams in Flash Memory Mode Rising edge of last write pulse Writing or erasing BUSY...
Page 658: Enable Sector Protect/Verify Sector Protect
APPENDIX Enable Sector Protect/verify Sector Protect Figure C-9 Enable Sector Protect/verify Sector Protect AQ18 AQ8, AQ2, AQ1 12 V 12 V SAX: First sector address SAY: Next sector address (AQ8, AQ2, AQ1) = (0, 1, 0) VLHT OESP VLHT...
Page 659: Temporary Sector Protect Cancellation
APPENDIX C Timing Diagrams in Flash Memory Mode Temporary Sector Protect Cancellation Figure C-10 Temporary Sector Protect Cancellation 12 V Write/erase command sequence VLHT RY/BY...
Page 660: Appendix D List Of Interrupt Vectors
APPENDIX APPENDIX D List of Interrupt Vectors The interrupt vector table to be referenced for interrupt processing is allocated to FFFC00 to FFFFFF in the memory area and also used for software interrupts. List of Interrupt Vectors Table D-1 lists the interrupt vectors for the MB90360 series. Table D-1 Interrupt Vectors (1/2) Interrupt Interrupt cause...
Page 661 Table D-1 Interrupt Vectors (2/2) Interrupt Interrupt cause request INT 31 Reserved INT 32 Reserved INT 33 Input capture 0 to 3 INT 34 Reserved INT 35 UART 0 RX INT 36 UART 0 TX INT 37 UART 1 RX INT 38 UART 1 TX INT 39...
Page 662 APPENDIX Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers Table D-2 summarizes the relationships among the interrupt causes, interrupt vectors, and interrupt control registers of the MB90360 series. Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (1/2) Interrupt cause Reset INT9 instruction Exception...
Page 663 Table D-2 Interrupt Causes, Interrupt Vectors, and Interrupt Control Registers (2/2) Interrupt cause UART 1 RX UART 1 TX Reserved Reserved Flash memory Delayed interrupt generation module Y1: An EI OS interrupt clear signal or EI Y2: An EI OS interrupt clear signal or EI N: An EI OS interrupt clear signal does not clear the interrupt request flag.
Page 664 APPENDIX...
Page 665 INDEX INDEX The index follows on the next page. This is listed in alphabetic order.
Page 666 INDEX Index Numerics 16-bit Free-run Timer Block Diagram of 16-bit Free-run Timer ...213 Explanation of Operation of 16-bit Free-run Timer ... 229 16-bit I/O Timer 16-bit I/O Timer Interrupt and EI Block Diagram of 16-bit I/O Timer ... 211 Functions of 16-bit I/O Timer... 210 Generation of Interrupt Request from 16-bit I/O Timer ...
Page 667 Accumulator (A) ... 40 A/D Control Status Register A/D Control Status Register (High) (ADCS1)... 346 A/D Control Status Register (Low) (ADCS0) ... 349 A/D Converter 8-/10-bit A/D Converter Interrupt and EI A/D-converted Data Protection Function in 8-/10-bit A/D Converter... 367 Block Diagram of 8-/10-bit A/D Converter...
Page 668 INDEX Bidirectional Communication Bidirectional Communication Function ... 433 Bit Timing Setting Bit Timing...494 Block Diagram Block Diagram of 16-bit Free-run Timer ...213 Block Diagram of 16-bit I/O Timer ... 211 Block Diagram of 16-bit Reload Timer... 240 Block Diagram of 8-/10-bit A/D Converter ... 341 Block Diagram of 8-/16-bit PPG Timer C...
Page 669 Clock Supervisor Control Register Clock Supervisor Control Register (CSVCR)... 113 Clock Supply Cycle of Clock Supply... 269 Clocks Clocks... 92 Common Register Bank Prefix (CMR)... 49 Command Sequence Chip Erase/sector Erase Command Sequence... 639 Command Sequence Table... 538 Common Register Bank Prefix Common Register Bank Prefix (CMR)...
Page 670 INDEX Data Polling Flag Data Polling Flag (DQ7) ... 541 Data Read Data Read by Read Access... 636 Data Register List of Message Buffer (data register)... 451 List of Message Buffers (DLC registers and Data registers) ... 450 Data Counter (DCT) ... 76 Port Direction Register (DDR)...
Page 671 Correspondence between 16-bit Reload Timer OS... 251 Interrupt and EI Correspondence between Timebase Timer Interrupt and EI OS ... 187 Correspondence to EI OS Function ... 228 OS Function of 16-bit Reload Timer ... 251 OS Function of 8-/10-bit A/D Converter... 358 OS Operation Flow...
Page 672 INDEX Sector Configuration of the 512K-bit Flash Memory ... 531 Setting the Flash Memory to the Read/reset State ... 545 Writing Data to the Flash Memory ... 546 Writing to the Flash Memory... 546 Writing to/erasing Flash Memory... 530 Flash Memory Control Status Register Flash Memory Control Status Register (FMCS) ...
Page 673 Precautions for Use of "DIV A,Ri" and "DIVW A,RWi" Instructions... 52 Restrictions on Interrupt Disable Instructions and Prefix Instructions... 51 Use of the "DIV A,Ri" and "DIVW A,RWi" Instructions without Precautions ... 53 Instruction List MC-16LX Instruction List ... 600 Instruction Map Structure of Instruction Map ...
Page 674 INDEX LIN-master-slave Communication LIN-master-slave Communication Function... 438 LIN-UART Block Diagram of LIN-UART ... 387 Block Diagram of LIN-UART Pins... 391 LIN-UART as LIN Master Device ... 439 LIN-UART Baud Rate Selection... 413 LIN-UART Direct Pin Access ... 432 LIN-UART Functions... 382 LIN-UART Interrupts ...
Page 675 Message Buffer Control Registers Message Buffer Control Registers ... 452 Microcontroller Connection of an Oscillator or an External Clock to the Microcontroller... 108 Minimum Connection Example of Minimum Connection to Flash Microcomputer Programmer ... 563 Example of Minimum Connection to Flash microcontroller Programmer ...
Page 676 INDEX Patch Processing Flow of Patch Processing for Patch Program... 520 Patch Program Flow of Patch Processing for Patch Program... 520 Pause-conversion Mode Operation of Pause-conversion Mode ... 365 Pause-conversion Mode (ADCS:MD1,MD0= "11 Setting of Pause-conversion Mode ... 364 Program Counter (PC) ... 45 Port Data Register (PDR) ...
Page 677 PSCCR Configuration of the PLL/Subclock Control Register (PSCCR) ... 101 PUCR Block Diagram of Pull-up Control Register (PUCR) ... 174 Pull-up Control Register (PUCR) ... 174 Pull-up Control Register Block Diagram of Pull-up Control Register (PUCR) ... 174 Pull-up Control Register (PUCR) ... 174 RAM area ...
Page 678 INDEX List of Registers and Reset Values of ROM Mirroring Function Select Module ... 527 ROM Mirroring Function Select Register ROM Mirroring Function Select Register (ROMM) ... 528 ROMM ROM Mirroring Function Select Register (ROMM) ... 528 ROM Security Function Overview of ROM Security Function ...
Page 679 Sub-clock Oscillation Stabilization Wait Time Timer of Subclock ... 277 Sub-clock Mode... 116 Sub-clock Mode Transition Operating When Sub-clock Has Already Stopped ... 116 Sub-clock Mode with External Single Clock Product ... 116 Symbols Description of Instruction Presentation Items and symbols...
Page 680 INDEX LIN-UART as LIN Master Device ... 439 LIN-UART Baud Rate Selection... 413 LIN-UART Direct Pin Access ... 432 LIN-UART Functions... 382 LIN-UART Interrupts ... 406 OS... 408 LIN-UART Interrupts and EI LIN-UART Pins... 391 LIN-UART Registers... 392 LIN-UART Serial Mode Register (SMR) ... 395 Notes on Using LIN-UART...
Page 681 FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL -16LX 16-BIT MICROCONTROLLER MB90360 Series HARDWARE MANUAL FUJITSU LIMITED Published Business Promotion Dept. Edited CM44-10136-1E April 2005 the first edition Electronic Devices...

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Mb90360 series

Fujitsu F2MCTM-16LX Hardware Manual

Table of Contents

Chapter 1 Overview

Chapter 2 Cpu

Chapter 3 Interrupts

Chapter 4 Delayed Interrupt Generation Module

Chapter 5 Clocks

Chapter 6 Clock Supervisor

Chapter 7 Resets

Chapter 8 Low-Power Consumption Mode

Chapter 9 Memory Access Modes

Chapter 10 I/O Ports

Chapter 11 Timebase Timer

Chapter 12 Watchdog Timer

CHAPTER 13 16-Bit I/O TIMER

Chapter 14 16-Bit Reload Timer

Chapter 15 Watch Timer

Chapter 16 8-/16-Bit Ppg Timer

Chapter 17 Dtp/External Interrupts

Chapter 18 8-/10-Bit A/D Converter

Chapter 19 Low Voltage Detection/Cpu Operating Detection Reset

Chapter 20 Lin-Uart

Chapter 21 Can Controller

Chapter 22 Address Match Detection Function

Chapter 23 Rom Mirroring Module

Chapter 24 512K-Bit Flash Memory

Chapter 25 Examples of Mb90F362/T(S), Mb90F367/T(S)Serial Programming Connection

Chapter 26 Rom Security Function

Appendix

APPENDIX A I/O Maps

APPENDIX B Instructions

APPENDIX C Timing Diagrams in Flash Memory Mode

APPENDIX D List of Interrupt Vectors

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Summary of Contents for Fujitsu F2MCTM-16LX