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Model 5304A
Theory of Operation
signal from the 5300A A1J 1(18) is gated through
Q18, U17F, U9B, and U16B to be counted (except
in the .1 fjsec position, where the 10 MHz clock is
gated through U12A and U16B).
The TIME BASE
OUTPUT signal is a 10 MHz clock signal divided
down by the time base to allow counting in incre-
ments of 1 fjsec, 10 fjsec etc.
9D-4-26.
The main gate closes when Channel B
"clocks" U15A and a display cycle is initiated by
the positive-going edge of the
M G F F signal
at
A1P1(12).
This signal is inverted through U17I)
and differentiated by C14 and R69.
The negative
pulse of the differentiated waveform gates U16A
"on" and the narrow positive-going pulse is inverted
through U17E as the MAX TIME signal.
9D-4-27.
At the end of the display cycle, the
RESET signal at AlPl(15) is inverted through
U13E and sets U15B(9) low. U15A(5) is set high by
the PRESET signal a t U15A(4). The INHIBIT signal
goes "high" and sets U15B(12) so that U15B changes
states on the positive-going transition from U18B(6).
This produces two results:
1. U9C(8) goes low which set the OPEN signal
at A1P1(10) low through U19B and opens
the 5300A main gate.
2. Q16 turns off and allows C12 to charge
through R43 and R61.
9D-4-28.
Transistor Q15 is an emitter-follower in-
put to Schmitt-Trigger Q13, Q14.
The output from
Q13 is level-shifted by CR15 and inverted by Q17.
Q15, 14, 13, and 17 form a one-shot multivibrator
with a very wide timing range. U15A cannot change
states until Q17 output goes low; then U15A(3) is
clocked to its opposite state by the positive trans-
ition of U18C (Channel B switch output).
The
U15A(5) output is gated and inverted through U14I)
and U22A.
This causes the CLOSE signal line to
go low which in turn closes the 5300A main gate.
9D-4-29. The 5300A main gate cannot be re-opened
until U15B is cleared by the RESET signal at
A1PK15) and until the INHIBIT signal at AlPl(8)
sets U15B(12) high.
U15B(8) goes high a t RESET
and turns on QI8 which discharges C12.
When
R43(S2) is open (full ccw), CI2 is not charged
up and the one-shot time-interval is very short
(about 200 nsec).
The time-interval is the interval
from the time U15B(8) goes low and Q17 collector
goes low.
9D-4-30. A buffered DELAY OUT signal is provided
at J 3 and may be used for intensifying the oscil-
loscope Z axis which permits observing the start
and stop period in a time interval measurement.
A buffered GATE OUT signal is also provided at J4
which permits observing the gate signal duration
in a time interval measurement
9D-4-31.
EXPONENT
COUNTER;
EXPONENT
STORAGE.
Outputs from the 5300A, U5 EXP line
are appli< J to exponent counter U8A, U8B "Clock
input". The RESET signal at A1 Pi(15) clears USA
and presets U8B for another measurement.
Ex-
ponent signals "clocked" into U8 indicate length
of measurements (10 ms,
100 ms, or
1 sec in
FREQ AUTO mode; 1, 10, 100, 1000 periods in
PERIOD AVG mode).
During the measurement
cycle,
information
is
transferred
into
U7A,
B
exponent storage by the TRANSFER signal. There-
fore, the displayed measurement, the decimal point
and the units, change simultaneously.
9D-4-32. Exponent storage U7A, B is disabled (both
flip-flops are cleared), except in AUTO measure-
ments, by U6I). Manual reset also clears U7A, U7B,
the decimal point and measurement units.
9D-4-33.
The remainder of the gates with the
exception of U5B provide time base, decimal point,
annunciator, and function decoding.
The U3A out-
put is high in any of the four frequency-measuring
positions. U5B locks out the LOG OUTPUT signal
in OPEN CLOSE A and TIME INTERVAL A B,
when the open and closing of the main gate is con-
trolled by OPEN and CLOSE.
9D-4-34.
Q19 normally turns off the 9 line except
during frequency Auto or
Period
Average; this
allows overflow to occur, if desired, in manual fre-
quency position.
9D-4-3
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