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Interconnectivity
PDIUSBD12 Evaluation Board (PC Kit) User's Manual
On USB host side, a
sample application program
D12TEST.EXE and a
general purpose minidriver
D12TEST.SYS are
provided.
USB Host PC
D12 Sample Applet
D12TEST.EXE
D12 Sample Driver
D12TEST.SYS
USBD
USB Host Controller
Driver
USB Host Controller
Block Diagram
Above block diagram shows 5 main components on the PDIUSBD12 evaluation board. Beside bus
transceiver, address/command decoder and PDIUSBD12, a general input port and a general output
port are included in the design. These input and output ports are designed for test purposes, such as
test switches and test LEDs. They also act as glue logic to adapt the PDIUSBD12 to the ISA bus. For
example, ISA interrupt is edge triggered, but PDIUSBD12 interrupt is level triggered. The MSB of the
general output port is used as interrupt enable to convert level triggered interrupt to edge triggered.
I/O Mapping
PDIUSBD12 evaluation board uses 8 I/O addresses:
Offset
0
1
2
3
4 to 7
_______________________________________________________________________________________________
HARDWARE DESCRIPTION
System Block
Diagram of D12
Evaluation Kit
25 Pin Interface
1. VCC, GND
2. D0 - D7
3. ADDRESS ENABLE
4. IOW, IOR, IRQ, RESET
5. DREQ, DACK, EOT
D12 Evaluation Board
Test
General
Key
Input port
Test
General
LED
Output port
PDIUSBD12
Usage
D12 data register, R/W
D12 command register, W only
General input port, R only
General output port, W only
Reserved for expansion board
Philips Semiconductors - Asia Product Innovation Centre
Visit
http://www.flexiusb.com
On device side, sample firmware
D12FW.EXE is provided for
running on device PC. The
firmware is written in C for easily
portable to other CPU platforms.
25
Command
Pin
and Address
I/F
Decoder
Bi-direction
Bus
Transceiver
Page 9 of 14
REV. 2.1
Customer's System
25
CPU,
Pin
Memory,
I/F
and DMA
Controller
USB Device PC
D12 ISA Bridging Board
25
ISA
Pin
Slot
I/F
DIP
Switches
and
Jumpers
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