Schematic Diagram - Yamaha YSP-1 Service Manual

A B C
SCHEMATIC DIAGRAM (DSP 1/2)
1
IC3 and IC4 can not be supplied. /
2
3.3 0
3.0 3.1
3.2 0
3.1 3.1
3.1 3.1
0 3.2
3.1
3.1 3.1
3.2 0
3.1 3.1
3.1 3.1
0 3.2
3.1 3.1
3.3 0
3.1 3.2
3
3.1
0
3.2
3.2 3.2
0 0
3.2 0
0 0
0 0
0 0
0 0
3.2 0
3.2 3.2
3.3 0
3.1 3.1
0 3.2
3.1 3.2
3.1 3.0
3.2 0
3.1 3.0
4 3.1 3.0
0 3.2
3.1 3.2
3.1 3.1
3.2 0
3.2 3.1
3.3 0
SYNCHRONOUS
DRAM
5
0 0
0 3.2
0
0
0 3.1
0 3.1
0 3.1
0 3.1
0 3.1
0 3.1
3.1
3.2 3.1
3.2 3.2
0 3.1
3.1
3.2 3.1
0 3.1
0 3.1
1.6 3.1
1.6
3.1
2.1 3.0
6
3.1 3.2
3.2 0
3.2 3.2
0 0
7
IC1: MT48LC2M32B2P-6
SYNCHRONOUS DRAM
8
CKE
CLK
CONTROL
CS#
LOGIC
WE#
BANK3
CAS#
BANK2
BANK1
RAS#
BANK0
REFRESH
11
MODE REGISTER COUNTER
9
ROW- 11 BANK0
ADDRESS ROW-
BANK0
ADDRESS
M UX MEMORY
11 2048
LATCH ARRAY
11 &
(2,048 x 256 x 32)
DECODER
SENSE AMPLIFIERS
8192
2 I/O GATING
DQM MASK LOGIC
BANK READ DATA L ATCH
A0-A10, ADDRESS CONTROL WRITE DRIVERS
13
BA0, BA1
REGISTER LOGIC
2
256
(x32)
COLUMN
DECODER
COLUMN-
10
ADDRESS 8
8
COUNTER/
LATCH
D E F
This part can not be supplied
This part can not be supplied
3.3 3.2
0
This part can not be supplied
3.2
This part can not be supplied
Page 54 G1
to DSP_CB302 (T, A, G, J models)
3.3
3.3
0
A-2
L
Page 54 F2 Page 54 F2
to AMP_CB3 to AMP_CB3
IC2: MBM29LV160BE-70
16M-bit, 3.0 V-only Flash memory
V 1 86 V
DD SS
DQ0 2 85 DQ15
V DD Q 3 84 V SS Q
DQ1 4 83 DQ14
DQ2 5 82 DQ13
V Q 6 81 V Q
SS DD
V
DQ3 7 80 DQ12 CC RY/BY
DQ4 8 79 DQ11 V Buffer
SS
V DD Q 9 78 V SS Q
DQ5 10 77 DQ10
DQ6 11 76 DQ9
V SS Q 12 75 V DD Q
DQ7 13 74 DQ8
NC 14 73 NC
V 15 72 V
DD SS
WE
DQM0 16 71 DQM1
WE# 17 70 NC
BYTE
Control
CAS# 18 69 NC
RAS# 19 68 CLK
RESET
CS# 20 67 CKE
NC 21 66 A9
Command
BA0 22 65 A8 Register
BA1 23 64 A7
A10 24 63 A6
A0 25 62 A5
4 4
DQM0- A1 26 61 A4
DQM3 A2 27 60 A3
CE
DQM2 28 59 DQM3
V DD 29 58 V SS OE
NC 30 57 NC
DATA
OUTPUT DQ16 31 56 DQ31
32
V Q 32 55 V Q
REGISTER SS DD
DQ17 33 54 DQ30
DQ18 34 53 DQ29
V DD Q 35 52 V SS Q
32 DQ0-
DQ19 36 51 DQ28
DQ31
DQ20 37 50 DQ27
V SS Q 38 49 V DD Q
DATA
DQ21 39 48 DQ26
32 INPUT
DQ22 40 47 DQ25
REGISTER
V Q 41 46 V Q Low V
DD SS
DQ23 42 45 DQ24
V DD 43 44 V SS
A to A
0 19
A
-1
G H I
0
3.2
3.2
1.6
3.2 3.2
This part can not be supplied
1.6
0
This part can not be supplied This part can not be supplied
DQ 0 to DQ 15
RY/BY
Erase Voltage Input/Output
Generator Buffer
State
Program Voltage
Generator STB
Chip Enable
Data Latch
Output Enable
Logic
A 1
15
A 2
14
A 3
13
A 4
12
A 11 5
A 10 6
Y-Decoder Y-Gating
STB A 9 7
A 8
8
A 9
19
N.C. 10
Timer for Address WE 11
CC Detector
Program/Erase RESET 12
Latch
X-Decoder N.C. 13
Cell Matrix
N.C. 14
RY/BY 15
A 18 16
A 17
17
A 18
7
A 19
6
A 20
5
A 4 21
A 3 22
A 2 23
A 1 24
J K
3.3
3.3
3.3 3.3
3.3 3.3
3.3
0
3.3
3.3
1.3
1.3
0
0
3.3
3.3
0
1.3 3.3
1.3
2.8
This part can not be supplied 3.3
0
3.3
1.3
1.3 3.3
1.3 0
1.3 0
1.3
0
2.6
PWM
0
3.3 0.9 3.3
0
2.8
0 3.3
3.3
0
2.6 3.3
2.6 0
2.6
0
2.6 0
2.6
2.5
2.5
2.5 2.5
0
2.6
0
This part can not be supplied
1.3
3.3
3.2
0
IC6: LC4032V-75TN48C IC7, 8: TPS54310PWPR
Complex Programmable Logic Device Low-input-voltage high-output-current synchronous-buck PWM converter
VIN
Enable
Comparator
SS/ENA
0.8 V
I/O I/O
Block 16 16 Block
Generic Generic
ORP 16 Logic Logic 16 ORP
Block 36 36 Block
VIN
Offset
VSENSE
I/O I/O
16 16
Block Block
Generic Generic
ORP 16 Logic Logic 16 ORP
36 36
Block Block
AGND
48 A
16
47 BYTE
46 V
SS
45 DQ /A
15 -1
44 DQ 7
43 DQ 14
42 DQ 6
41 DQ
13
40 DQ
5
39 DQ
12
38 DQ
4
37 V
CC
36 DQ 11
35 DQ 3
34 DQ 10
33 DQ 2
32 DQ
9
31 DQ
1
30 DQ
8
29 DQ
0
28 OE
27 V SS
26 CE
★ All voltages are measured with a 10MΩ/V DC electronic volt meter.
25 A 0
★ Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
★ Schematic diagram is subject to change without notice.
L M N
YSP-1
IC5: SN74LVC74APWR
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
PRE
C
CLK C
C
Q
TG
C C C
C
D TG TG TG
Q
C C C
CLR
1CLR VCC
1 14
1D 2CLR
2 13
1CLK 3 12 2D
1PRE 4 11 2CLK
1Q 5 10 2PRE
1Q 6 9 2Q
GND 7 8 2Q
POINT A-2 pin 3 of IC5
0
0
IC9: TPS2034D
POWER-DISTRIBUTION SWITCHES
Power Switch
†
IN CS OUT
Charge
Pump
Current
EN Driver
Limit
OC
UVLO
Thermal
GND
Sense
† Current Sense
VBIAS
SHUTDOWN
VBIAS
Highin Highdr
UVLO UVLO REG
VIN
Sampling
Falling VPHASE VIN
Logic
Edge Rising
Delay Edge
Delay VI(LIM)
1–4 s BOOT
T_SUNT
SHUTDOWN
VIN UVLO
SS_DIS
Comparator Bias UVLO
ILIM
BG GOOD
Comparator
Highdr
Delay
Rising
Edge
SHUTDOWN SHUTDOWN
VIN_UVLO Delay
Reference/DAC
Error PWM Highin
Amplifier Comparator
MUX + L(out) VO
PH
R Q
– Deadtime
S Co
PGND
SHUTDOWN
OSC s
20–50
Ct Falling
VSENSE PWRGD
Edge
Iset
Vpgd Delay
Powergood
Comparator SHUTDOWN
SYNC RT
AGND 1 20 RT
VSENSE 2 19 SYNC
COMP 3 18 SS/ENA
PWRGD 4 17 VBIAS
BOOT 5 16 VIN
PH 6 15 VIN
PH 7 14 VIN
PH 8 13 PGND
PH 9 12 PGND
PH 10 11 PGND
51