Sbep Serial Interface; Microprocessor (Open Controller) - Motorola GTX/LCS 2000 Service Manual

SBEP Serial Interface

Microprocessor (Open
Controller)
SPI BUS is also used for the control head. U0106 buffers the SPI TRANSMIT
DATA and CLK lines to the control head. U0106 serves also to switch off the CLK
signal for the LCD display while it is not selected via LCD CE signal.
When the µP needs to program any of these ICs, it drops down the chip select line
of the specific IC to a logic 0 and then sends the proper data and clock signals. The
data sent to the various ICs are different. For example the ASFIC receives 21 bytes
(168 bits) while the DAC needs 3 bytes (24 bits). After the data has been sent the
chip select line is returned to a logic 1.
The SBEP serial interface line allows the radio to communicate with the Dealer
Programming Software (DPS). This interface connects to the Microphone
connector (J0902) via Control Head connector (J0101) and comprises BUS+
(J0101-15). The line is bi-directional, meaning that either the radio or the DPS can
drive the line.
The connection from the Control Head is made through the BUS+ line, via L421
(SCI_RSS line) and diode CR151 to the K1µP-TxD and K1µP-RxD ports.
For this radio, the K1µP is configured to operate in the expanded or bootstrap
modes. In expanded mode the K1µP uses external memory ICs, whereas in
bootstrap mode it uses only its internal memory. In normal radio operation, the
K1µP is operating in the expanded mode.
In the radio expanded mode, the K1µP (U0101) has access to three external
memory ICs: U0102 (OTP memory), U0103 (SRAM), U0104 (EEPROM). Also,
within the K1µP there are 768 bytes of internal RAM and 640 bytes of internal
EEPROM, as well as glue logic circuitry to select external memory ICs.
The external EEPROM (U0104) as well as the K1µP's own internal EEPROM
contain the radio information which is customer specific, referred to as the
codeplug. This information consists of items such as: 1) frequency operating band,
2) channel frequencies, and 3) general tuning information. General tuning
information and other more frequently accessed items are stored in the internal
EEPROM (within the 68HC11K1), while the remaining data is stored in the
external EEPROM. (See the particular IC subsection for more details.)
The external SRAM (U0103) as well as the K1µP's own internal RAM are used
for temporary calculations required by the software during normal radio
operation. All of the data stored in both of these locations is lost when the radio is
powered off. (See the particular IC subsection for more details.)
The OTP memroy contains the actual Radio Operating Software. This software is
common to all radios for the same model type. For example Securenet radios may
have a different version of software in the OTP memory than a non-secure radio.
(See the particular IC subsection for more details.)
The K1µP has an address bus of 16 address lines (A0-A15), a data bus of 8 data
lines (D0-D7). and three control lines; CSPROG (U0101-29) to select U0102-30
(OTP memory), CSGP2 (U0101-28) to select U0103-20 (SRAM) and PG7_R_W
for read and write. All other chips (ASFIC/PENDULLUM/DAC/FRACN/LCD/
LED/EEPROM) are selected by 3 lines of the K1µP using chip select decoder
U0105. While the K1µP is functioning normally, the address and data lines should
be within CMOS logic levels.
The low-order address lines (A0-A7) and the data lines (D0-D7) should change.
Theory of Operation 7-11